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perf/x86/intel/uncore: Add infrastructure for free running counters
There are a number of free running counters introduced for uncore, which provide highly valuable information to a wide array of customers. However, the generic uncore code doesn't support them yet. The free running counters will be specially handled based on their unique attributes: - They are read-only. They cannot be enabled/disabled. - The event and the counter are always 1:1 mapped. It doesn't need to be assigned nor tracked by event_list. - They are always active. It doesn't need to check the availability. - They have different bit width. Also, using inline helpers to replace the check for fixed counter and free running counter. Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: acme@kernel.org Cc: eranian@google.com Link: http://lkml.kernel.org/r/1525371913-10597-5-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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927b2deb06
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@ -203,7 +203,7 @@ static void uncore_assign_hw_event(struct intel_uncore_box *box,
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hwc->idx = idx;
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hwc->last_tag = ++box->tags[idx];
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if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
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if (uncore_pmc_fixed(hwc->idx)) {
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hwc->event_base = uncore_fixed_ctr(box);
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hwc->config_base = uncore_fixed_ctl(box);
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return;
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@ -218,7 +218,9 @@ void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *e
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u64 prev_count, new_count, delta;
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int shift;
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if (event->hw.idx == UNCORE_PMC_IDX_FIXED)
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if (uncore_pmc_freerunning(event->hw.idx))
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shift = 64 - uncore_freerunning_bits(box, event);
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else if (uncore_pmc_fixed(event->hw.idx))
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shift = 64 - uncore_fixed_ctr_bits(box);
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else
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shift = 64 - uncore_perf_ctr_bits(box);
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@ -454,10 +456,25 @@ static void uncore_pmu_event_start(struct perf_event *event, int flags)
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struct intel_uncore_box *box = uncore_event_to_box(event);
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int idx = event->hw.idx;
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
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if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
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return;
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if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
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/*
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* Free running counter is read-only and always active.
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* Use the current counter value as start point.
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* There is no overflow interrupt for free running counter.
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* Use hrtimer to periodically poll the counter to avoid overflow.
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*/
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if (uncore_pmc_freerunning(event->hw.idx)) {
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list_add_tail(&event->active_entry, &box->active_list);
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local64_set(&event->hw.prev_count,
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uncore_read_counter(box, event));
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if (box->n_active++ == 0)
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uncore_pmu_start_hrtimer(box);
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return;
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}
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
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return;
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event->hw.state = 0;
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@ -479,6 +496,15 @@ static void uncore_pmu_event_stop(struct perf_event *event, int flags)
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struct intel_uncore_box *box = uncore_event_to_box(event);
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struct hw_perf_event *hwc = &event->hw;
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/* Cannot disable free running counter which is read-only */
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if (uncore_pmc_freerunning(hwc->idx)) {
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list_del(&event->active_entry);
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if (--box->n_active == 0)
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uncore_pmu_cancel_hrtimer(box);
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uncore_perf_event_update(box, event);
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return;
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}
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if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
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uncore_disable_event(box, event);
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box->n_active--;
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@ -512,6 +538,17 @@ static int uncore_pmu_event_add(struct perf_event *event, int flags)
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if (!box)
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return -ENODEV;
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/*
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* The free funning counter is assigned in event_init().
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* The free running counter event and free running counter
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* are 1:1 mapped. It doesn't need to be tracked in event_list.
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*/
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if (uncore_pmc_freerunning(hwc->idx)) {
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if (flags & PERF_EF_START)
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uncore_pmu_event_start(event, 0);
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return 0;
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}
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ret = n = uncore_collect_events(box, event, false);
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if (ret < 0)
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return ret;
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@ -570,6 +607,14 @@ static void uncore_pmu_event_del(struct perf_event *event, int flags)
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uncore_pmu_event_stop(event, PERF_EF_UPDATE);
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/*
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* The event for free running counter is not tracked by event_list.
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* It doesn't need to force event->hw.idx = -1 to reassign the counter.
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* Because the event and the free running counter are 1:1 mapped.
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*/
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if (uncore_pmc_freerunning(event->hw.idx))
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return;
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for (i = 0; i < box->n_events; i++) {
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if (event == box->event_list[i]) {
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uncore_put_event_constraint(box, event);
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@ -603,6 +648,10 @@ static int uncore_validate_group(struct intel_uncore_pmu *pmu,
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struct intel_uncore_box *fake_box;
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int ret = -EINVAL, n;
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/* The free running counter is always active. */
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if (uncore_pmc_freerunning(event->hw.idx))
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return 0;
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fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
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if (!fake_box)
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return -ENOMEM;
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@ -690,6 +739,17 @@ static int uncore_pmu_event_init(struct perf_event *event)
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/* fixed counters have event field hardcoded to zero */
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hwc->config = 0ULL;
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} else if (is_freerunning_event(event)) {
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if (!check_valid_freerunning_event(box, event))
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return -EINVAL;
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event->hw.idx = UNCORE_PMC_IDX_FREERUNNING;
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/*
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* The free running counter event and free running counter
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* are always 1:1 mapped.
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* The free running counter is always active.
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* Assign the free running counter here.
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*/
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event->hw.event_base = uncore_freerunning_counter(box, event);
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} else {
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hwc->config = event->attr.config &
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(pmu->type->event_mask | ((u64)pmu->type->event_mask_ext << 32));
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