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net: phy: mscc: fix initialization of the MACsec protocol mode

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At the very end of the MACsec block initialization in the MSCC PHY
driver, the MACsec "protocol mode" is set. This setting should be set
based on the PHY id within the package, as the bank used to access the
register used depends on this. This was not done correctly, and only the
first bank was used leading to the two upper PHYs being unstable when
using the VSC8584. This patch fixes it.

Fixes: 1bbe0ecc2a ("net: phy: mscc: macsec initialization")
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Antoine Tenart 2020-05-22 17:55:45 +02:00 committed by David S. Miller
parent 31096c3e8b
commit 0ddfee1fee
5 changed files with 21 additions and 10 deletions
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2
drivers/net/phy/mscc/mscc.h
View File

@ -354,6 +354,8 @@ struct vsc8531_private {
u64 *stats;
int nstats;
bool pkg_init;
/* PHY address within the package. */
u8 addr;
/* For multiple port PHYs; the MDIO address of the base PHY in the
* package.
*/

6
drivers/net/phy/mscc/mscc_mac.h
View File

@ -152,8 +152,8 @@
#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0)
#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4)
#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2
#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)
#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)
#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2
#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)
#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)
#endif /* _MSCC_PHY_LINE_MAC_H_ */

16
drivers/net/phy/mscc/mscc_macsec.c
View File

@ -316,6 +316,8 @@ static void vsc8584_macsec_mac_init(struct phy_device *phydev,
/* Must be called with mdio_lock taken */
static int __vsc8584_macsec_init(struct phy_device *phydev)
{
struct vsc8531_private *priv = phydev->priv;
enum macsec_bank proc_bank;
u32 val;
vsc8584_macsec_block_init(phydev, MACSEC_INGR);
@ -351,12 +353,14 @@ static int __vsc8584_macsec_init(struct phy_device *phydev)
val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
val = vsc8584_macsec_phy_read(phydev, IP_1588,
MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL);
val &= ~MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
val |= MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
vsc8584_macsec_phy_write(phydev, IP_1588,
MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
val = vsc8584_macsec_phy_read(phydev, proc_bank,
MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
vsc8584_macsec_phy_write(phydev, proc_bank,
MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
return 0;
}

3
drivers/net/phy/mscc/mscc_macsec.h
View File

@ -64,7 +64,8 @@ enum macsec_bank {
FC_BUFFER = 0x04,
HOST_MAC = 0x05,
LINE_MAC = 0x06,
IP_1588 = 0x0e,
PROC_0 = 0x0e,
PROC_2 = 0x0f,
MACSEC_INGR = 0x38,
MACSEC_EGR = 0x3c,
};

4
drivers/net/phy/mscc/mscc_main.c
View File

@ -1347,6 +1347,8 @@ static int vsc8584_config_init(struct phy_device *phydev)
else
vsc8531->base_addr = phydev->mdio.addr - addr;
vsc8531->addr = addr;
/* Some parts of the init sequence are identical for every PHY in the
* package. Some parts are modifying the GPIO register bank which is a
* set of registers that are affecting all PHYs, a few resetting the
@ -1771,6 +1773,8 @@ static int vsc8514_config_init(struct phy_device *phydev)
else
vsc8531->base_addr = phydev->mdio.addr - addr;
vsc8531->addr = addr;
/* Some parts of the init sequence are identical for every PHY in the
* package. Some parts are modifying the GPIO register bank which is a
* set of registers that are affecting all PHYs, a few resetting the