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ARM: shmobile: Initial r8a7794 SoC device tree
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> [uli: reduced to minimum, added cmt, enabled scif2, split off board part] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Ulrich Hecht
Simon Horman
parent
126f998e4a
commit
0dce5454d5
531
arch/arm/boot/dts/r8a7794.dtsi
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531
arch/arm/boot/dts/r8a7794.dtsi
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/*
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* Device Tree Source for the r8a7794 SoC
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7794-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7794";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clock-frequency = <1000000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <1>;
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clock-frequency = <1000000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
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clock-names = "fck";
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renesas,channels-mask = <0x60>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 124 IRQ_TYPE_LEVEL_HIGH>,
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<0 125 IRQ_TYPE_LEVEL_HIGH>,
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<0 126 IRQ_TYPE_LEVEL_HIGH>,
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<0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
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clock-names = "fck";
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renesas,channels-mask = <0xff>;
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status = "disabled";
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7794", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c60000 0 64>;
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interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c70000 0 64>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa4: serial@e6c78000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c78000 0 64>;
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interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa5: serial@e6c80000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c80000 0 64>;
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifb0: serial@e6c20000 {
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compatible = "renesas,scifb-r8a7794", "renesas,scifb";
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reg = <0 0xe6c20000 0 64>;
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interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifb1: serial@e6c30000 {
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compatible = "renesas,scifb-r8a7794", "renesas,scifb";
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reg = <0 0xe6c30000 0 64>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifb2: serial@e6ce0000 {
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compatible = "renesas,scifb-r8a7794", "renesas,scifb";
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reg = <0 0xe6ce0000 0 64>;
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interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif2: serial@e6e58000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6e58000 0 64>;
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interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif3: serial@e6ea8000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6ea8000 0 64>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif4: serial@e6ee0000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6ee0000 0 64>;
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interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif5: serial@e6ee8000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6ee8000 0 64>;
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interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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hscif0: serial@e62c0000 {
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compatible = "renesas,hscif-r8a7794", "renesas,hscif";
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reg = <0 0xe62c0000 0 96>;
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interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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hscif1: serial@e62c8000 {
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compatible = "renesas,hscif-r8a7794", "renesas,hscif";
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reg = <0 0xe62c8000 0 96>;
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interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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hscif2: serial@e62d0000 {
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compatible = "renesas,hscif-r8a7794", "renesas,hscif";
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reg = <0 0xe62d0000 0 96>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overriden by the board. */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7794-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "z";
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};
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/* Fixed factor clocks */
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pll1_div2_clk: pll1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll1_div2";
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};
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zg_clk: zg_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <6>;
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clock-mult = <1>;
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clock-output-names = "zg";
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};
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zx_clk: zx_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <3>;
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clock-mult = <1>;
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clock-output-names = "zx";
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};
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zs_clk: zs_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <6>;
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clock-mult = <1>;
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clock-output-names = "zs";
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};
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hp_clk: hp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "hp";
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};
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i_clk: i_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "i";
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};
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b_clk: b_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "b";
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};
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p_clk: p_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <24>;
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clock-mult = <1>;
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clock-output-names = "p";
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};
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cl_clk: cl_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <48>;
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clock-mult = <1>;
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clock-output-names = "cl";
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};
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m2_clk: m2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "m2";
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};
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imp_clk: imp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "imp";
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};
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rclk_clk: rclk_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <(48 * 1024)>;
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clock-mult = <1>;
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clock-output-names = "rclk";
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};
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oscclk_clk: oscclk_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <(12 * 1024)>;
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clock-mult = <1>;
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clock-output-names = "oscclk";
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};
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zb3_clk: zb3_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "zb3";
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};
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zb3d2_clk: zb3d2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "zb3d2";
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};
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ddr_clk: ddr_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "ddr";
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};
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mp_clk: mp_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <15>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "mp";
|
||||
};
|
||||
cp_clk: cp_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <48>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cp";
|
||||
};
|
||||
|
||||
acp_clk: acp_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "acp";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
mstp0_clks: mstp0_clks@e6150130 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
||||
clocks = <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
|
||||
clock-output-names = "msiof0";
|
||||
};
|
||||
mstp1_clks: mstp1_clks@e6150134 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
|
||||
clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
|
||||
<&cp_clk>,
|
||||
<&zs_clk>, <&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
|
||||
R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
|
||||
>;
|
||||
clock-output-names =
|
||||
"tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
|
||||
};
|
||||
mstp2_clks: mstp2_clks@e6150138 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&mp_clk>, <&mp_clk>, <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
|
||||
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
|
||||
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
||||
"scifb1", "msiof1", "scifb2";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&rclk_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_CMT1
|
||||
>;
|
||||
clock-output-names =
|
||||
"cmt1";
|
||||
};
|
||||
mstp7_clks: mstp7_clks@e615014c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
||||
clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
||||
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
|
||||
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
|
||||
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
|
||||
R8A7794_CLK_SCIF0
|
||||
>;
|
||||
clock-output-names =
|
||||
"hscif2", "scif5", "scif4", "hscif1", "hscif0",
|
||||
"scif3", "scif2", "scif1", "scif0";
|
||||
};
|
||||
mstp8_clks: mstp8_clks@e6150990 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
||||
clocks = <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_ETHER
|
||||
>;
|
||||
clock-output-names =
|
||||
"ether";
|
||||
};
|
||||
mstp11_clks: mstp11_clks@e615099c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
|
||||
>;
|
||||
clock-output-names = "scifa3", "scifa4", "scifa5";
|
||||
};
|
||||
};
|
||||
};
|
||||
80
include/dt-bindings/clock/r8a7794-clock.h
Normal file
80
include/dt-bindings/clock/r8a7794-clock.h
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7794_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7794_CLK_MAIN 0
|
||||
#define R8A7794_CLK_PLL0 1
|
||||
#define R8A7794_CLK_PLL1 2
|
||||
#define R8A7794_CLK_PLL3 3
|
||||
#define R8A7794_CLK_LB 4
|
||||
#define R8A7794_CLK_QSPI 5
|
||||
#define R8A7794_CLK_SDH 6
|
||||
#define R8A7794_CLK_SD0 7
|
||||
#define R8A7794_CLK_Z 8
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7794_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7794_CLK_TMU1 11
|
||||
#define R8A7794_CLK_TMU3 21
|
||||
#define R8A7794_CLK_TMU2 22
|
||||
#define R8A7794_CLK_CMT0 24
|
||||
#define R8A7794_CLK_TMU0 25
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7794_CLK_SCIFA2 2
|
||||
#define R8A7794_CLK_SCIFA1 3
|
||||
#define R8A7794_CLK_SCIFA0 4
|
||||
#define R8A7794_CLK_MSIOF2 5
|
||||
#define R8A7794_CLK_SCIFB0 6
|
||||
#define R8A7794_CLK_SCIFB1 7
|
||||
#define R8A7794_CLK_MSIOF1 8
|
||||
#define R8A7794_CLK_SCIFB2 16
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7794_CLK_CMT1 29
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7794_CLK_THERMAL 22
|
||||
#define R8A7794_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7794_CLK_HSCIF2 13
|
||||
#define R8A7794_CLK_SCIF5 14
|
||||
#define R8A7794_CLK_SCIF4 15
|
||||
#define R8A7794_CLK_HSCIF1 16
|
||||
#define R8A7794_CLK_HSCIF0 17
|
||||
#define R8A7794_CLK_SCIF3 18
|
||||
#define R8A7794_CLK_SCIF2 19
|
||||
#define R8A7794_CLK_SCIF1 20
|
||||
#define R8A7794_CLK_SCIF0 21
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7794_CLK_ETHER 13
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7794_CLK_GPIO6 5
|
||||
#define R8A7794_CLK_GPIO5 7
|
||||
#define R8A7794_CLK_GPIO4 8
|
||||
#define R8A7794_CLK_GPIO3 9
|
||||
#define R8A7794_CLK_GPIO2 10
|
||||
#define R8A7794_CLK_GPIO1 11
|
||||
#define R8A7794_CLK_GPIO0 12
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7794_CLK_SCIFA3 6
|
||||
#define R8A7794_CLK_SCIFA4 7
|
||||
#define R8A7794_CLK_SCIFA5 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
|
||||
Loading…
Reference in New Issue
Block a user