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Arm Vexpress updates for v6.11
Remove obsolete RTSM DCSCB support which was only ever implemented on a software model which is neither available to download nor maintained. It predates the very first bL cluster based platforms. Other change include addition of the missing MODULE_DESCRIPTION macro in vexpress config bus driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmZz7QIACgkQAEG6vDF+ 4phSjBAAuuUpgUrG/LOniUoyOPXvX4SXGmwuSKMpicsgj9ojIlYjkVEeQGt67ERY abTZhyOO3l/6hhs0j1YeB2H0C5VgJMwgBG1ZObaD6QM6PtTvlJU5h5f1VSLFv7YY wV9SE2BQbfVjf4cH9U/p2r90VM+SZIjTcGpzgIB6d2/XdNnEMyohmuBhXsOtuS4C I5yfVKiAiT4AJdmO32JDmGvio5sudFQbBk3Q5y3ofukdxNVmeo1SHC3MasSakQt8 T0TLaRa3UqEAIw93hKzhp1/k8K4uzYQyDbVB/PCao8rOlPeR6A3WOu1qpfv7FFp5 noIS+87eAak2fILtFBGWpbun/gR+ewINJrP4iV8LiOIw4HLT6hKzANzKDztXeWAe yWs7A8xaC67DFygrRGSq9yxnElRBOEhegdaBY++2cG6jGzI3EJze1ufYmdKJ+WyF C8PIubi5IGzPN0NPQivui3fedT3mEV/Bv7NjiD7jx8auTOtxASqGMYY/rmiz4nJQ Dzd2kJ/b+4Tx9oIONfbB/4HsA5tkcdwh/aylsdhLKACrmREZVWQ2NzFtKnfA0fQv 2+Dvmnw0NisQfXbHT0B5bp7beYg24pEJuzSGGapPaY4WzNTGFCNg6MRtR/dEiLJN UG6lobFmUKzs9KGMWorXKhlp+OhqQbNb2c8rYH8qA2QQo6ZcIAE= =VAfv -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmZ+yKsACgkQYKtH/8kJ Uid8pw/5AeAKo8906bIaKuwrXy1s/iJaC+bfbxX5sQqbalLPwsifRtNGsx0E0FcT K+uh46GEt2Gczq8GMBmJjlDVK++xm+MszUdZV2qhtf+eF4tDiPHZAzuXTTzt5wgG rbjPeJu6HhMDPO9s9+xDSilcnQ4FB/24+9s3PIiV9zx83fBKnIfr7rb53XJKUh3p sgz6iHHkCtlmZB3+oHPlK+bd63j7lnbpdOBVOEUGZccZZu5xJ0xNg2br1b1nQkpN xgD4JkKNqqfA6LO2DziAAOR/LCRJGff1BmwaRAMX+hWNqGbRRGlbShZIIKwQ4ejQ OHDm43yvJNEVeCqKj4Cqa6gesUB9Myl2Pu8bKnjk7gm4P+LOpNQpNtMb5v7bgGd0 /wX02IA5Y8RN+wDkYAaI08Eb8bmaJ8EdY73fUhNGQutNKiCzCEM38QRmvsBCEio8 z6qLTXnZl/lFEp0q442ZPB6gxo6CwB2FgRBWrNLlPuPU2S2pnUcgh+FZQGipJklA RnODnMiZuNrlWkicb5nagX7X+INs3d81R23C/eJz8VapTlHPO36I2ZMIMPWbnln/ WRFoIzv+tUWe1Z4HQ6nw7N+o3k/TPijlN9/YC8s+O2xN9cVPu9g4rcmy8fWFF3Q4 UpehJDEfAFH8b2Smkfcbmx8uWe2pZZLoE4S2lLMYykvr5+6tZvk= =jv0e -----END PGP SIGNATURE----- Merge tag 'vexpress-updates-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/arm Arm Vexpress updates for v6.11 Remove obsolete RTSM DCSCB support which was only ever implemented on a software model which is neither available to download nor maintained. It predates the very first bL cluster based platforms. Other change include addition of the missing MODULE_DESCRIPTION macro in vexpress config bus driver. * tag 'vexpress-updates-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: bus: vexpress-config: Add missing MODULE_DESCRIPTION() macro dt-bindings: arm: Remove obsolete RTSM DCSCB binding arm: vexpress: Remove obsolete RTSM DCSCB support Link: https://lore.kernel.org/r/20240620093924.375244-4-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
0dabf24cf4
@ -1,19 +0,0 @@
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ARM Dual Cluster System Configuration Block
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-------------------------------------------
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The Dual Cluster System Configuration Block (DCSCB) provides basic
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functionality for controlling clocks, resets and configuration pins in
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the Dual Cluster System implemented by the Real-Time System Model (RTSM).
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Required properties:
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- compatible : should be "arm,rtsm,dcscb"
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- reg : physical base address and the size of the registers window
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Example:
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dcscb@60000000 {
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compatible = "arm,rtsm,dcscb";
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reg = <0x60000000 0x1000>;
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};
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@ -14,7 +14,6 @@ CONFIG_CPUSETS=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_PROFILING=y
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CONFIG_ARCH_VEXPRESS=y
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CONFIG_ARCH_VEXPRESS_DCSCB=y
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CONFIG_ARCH_VEXPRESS_TC2_PM=y
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CONFIG_SMP=y
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CONFIG_HAVE_ARM_ARCH_TIMER=y
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@ -278,15 +278,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
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build a working kernel, you must also enable relevant core
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tile support or Flattened Device Tree based support options.
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config ARCH_VEXPRESS_DCSCB
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bool "Dual Cluster System Control Block (DCSCB) support"
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depends on MCPM
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select ARM_CCI400_PORT_CTRL
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help
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Support for the Dual Cluster System Configuration Block (DCSCB).
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This is needed to provide CPU and cluster power management
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on RTSM implementing big.LITTLE.
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config ARCH_VEXPRESS_SPC
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bool "Versatile Express Serial Power Controller (SPC)"
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select PM_OPP
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@ -16,9 +16,6 @@ obj-$(CONFIG_ARCH_REALVIEW) += realview.o
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# vexpress
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obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o
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obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
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CFLAGS_dcscb.o += -march=armv7-a
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CFLAGS_REMOVE_dcscb.o = -pg
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obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o
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CFLAGS_REMOVE_spc.o = -pg
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obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o
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@ -1,173 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* dcscb.c - Dual Cluster System Configuration Block
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*
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* Created by: Nicolas Pitre, May 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/of_address.h>
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#include <linux/vexpress.h>
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#include <linux/arm-cci.h>
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include "vexpress.h"
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#define RST_HOLD0 0x0
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#define RST_HOLD1 0x4
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#define SYS_SWRESET 0x8
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#define RST_STAT0 0xc
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#define RST_STAT1 0x10
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#define EAG_CFG_R 0x20
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#define EAG_CFG_W 0x24
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#define KFC_CFG_R 0x28
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#define KFC_CFG_W 0x2c
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#define DCS_CFG_R 0x30
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static void __iomem *dcscb_base;
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static int dcscb_allcpus_mask[2];
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static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster)
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{
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unsigned int rst_hold, cpumask = (1 << cpu);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]))
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return -EINVAL;
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold &= ~(cpumask | (cpumask << 4));
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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return 0;
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}
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static int dcscb_cluster_powerup(unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cluster %u\n", __func__, cluster);
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if (cluster >= 2)
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return -EINVAL;
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/* remove cluster reset and add individual CPU's reset */
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold &= ~(1 << 8);
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rst_hold |= dcscb_allcpus_mask[cluster];
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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return 0;
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}
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static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster]));
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= (1 << cpu);
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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}
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static void dcscb_cluster_powerdown_prepare(unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= 2);
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= (1 << 8);
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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}
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static void dcscb_cpu_cache_disable(void)
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{
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/* Disable and flush the local CPU cache. */
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v7_exit_coherency_flush(louis);
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}
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static void dcscb_cluster_cache_disable(void)
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{
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/* Flush all cache levels for this cluster. */
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v7_exit_coherency_flush(all);
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/*
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* A full outer cache flush could be needed at this point
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* on platforms with such a cache, depending on where the
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* outer cache sits. In some cases the notion of a "last
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* cluster standing" would need to be implemented if the
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* outer cache is shared across clusters. In any case, when
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* the outer cache needs flushing, there is no concurrent
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* access to the cache controller to worry about and no
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* special locking besides what is already provided by the
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* MCPM state machinery is needed.
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*/
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(read_cpuid_mpidr());
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}
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static const struct mcpm_platform_ops dcscb_power_ops = {
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.cpu_powerup = dcscb_cpu_powerup,
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.cluster_powerup = dcscb_cluster_powerup,
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.cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare,
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.cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare,
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.cpu_cache_disable = dcscb_cpu_cache_disable,
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.cluster_cache_disable = dcscb_cluster_cache_disable,
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};
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extern void dcscb_power_up_setup(unsigned int affinity_level);
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static int __init dcscb_init(void)
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{
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struct device_node *node;
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unsigned int cfg;
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int ret;
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if (!cci_probed())
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return -ENODEV;
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node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
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if (!node)
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return -ENODEV;
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dcscb_base = of_iomap(node, 0);
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of_node_put(node);
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if (!dcscb_base)
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return -EADDRNOTAVAIL;
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cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
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dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
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dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
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ret = mcpm_platform_register(&dcscb_power_ops);
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if (!ret)
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ret = mcpm_sync_init(dcscb_power_up_setup);
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if (ret) {
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iounmap(dcscb_base);
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return ret;
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}
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pr_info("VExpress DCSCB support installed\n");
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/*
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* Future entries into the kernel can now go
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* through the cluster entry vectors.
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*/
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vexpress_flags_set(__pa_symbol(mcpm_entry_point));
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return 0;
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}
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early_initcall(dcscb_init);
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@ -1,33 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Created by: Dave Martin, 2012-06-22
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* Copyright: (C) 2012-2013 Linaro Limited
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*/
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#include <linux/linkage.h>
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ENTRY(dcscb_power_up_setup)
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cmp r0, #0 @ check affinity level
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beq 2f
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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* The ACTLR SMP bit does not need to be set here, because cpu_resume()
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* already restores that.
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*
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* A15/A7 may not require explicit L2 invalidation on reset, dependent
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* on hardware integration decisions.
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* For now, this code assumes that L2 is either already invalidated,
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* or invalidation is not required.
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*/
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b cci_enable_port_for_self
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2: @ Implementation-specific local CPU setup operations should go here,
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@ if any. In this case, there is nothing to do.
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bx lr
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ENDPROC(dcscb_power_up_setup)
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@ -414,4 +414,5 @@ static struct platform_driver vexpress_syscfg_driver = {
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.probe = vexpress_syscfg_probe,
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};
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module_platform_driver(vexpress_syscfg_driver);
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MODULE_DESCRIPTION("Versatile Express configuration bus");
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MODULE_LICENSE("GPL v2");
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