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[PATCH] ARM: 2784/1: Fix the block cache flush operation range

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Patch from Catalin Marinas

The range for the ARMv6 block cache operations is inclusive but the
kernel doesn't re-calculate the end address, causing a page fault when
used (this only happens with support for cache aliasing, otherwise the
blk_flush_kern_dcache_page() is not called). This patch subtracts
L1_CACHE_BYTES from the end address.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2005-07-03 17:53:25 +01:00 committed by Russell King
parent 75f631dc45
commit 0d670b413f
1 changed files with 2 additions and 1 deletions
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3
arch/arm/mm/blockops.c
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@ -25,13 +25,14 @@ blk_flush_kern_dcache_page(void *kaddr)
{ {
asm( asm(
"add r1, r0, %0 \n\ "add r1, r0, %0 \n\
sub r1, r1, %1 \n\
1: .word 0xec401f0e @ mcrr p15, 0, r0, r1, c14, 0 @ blocking \n\ 1: .word 0xec401f0e @ mcrr p15, 0, r0, r1, c14, 0 @ blocking \n\
mov r0, #0 \n\ mov r0, #0 \n\
mcr p15, 0, r0, c7, c5, 0 \n\ mcr p15, 0, r0, c7, c5, 0 \n\
mcr p15, 0, r0, c7, c10, 4 \n\ mcr p15, 0, r0, c7, c10, 4 \n\
mov pc, lr" mov pc, lr"
: :
: "I" (PAGE_SIZE)); : "I" (PAGE_SIZE), "I" (L1_CACHE_BYTES));
} }
/* /*