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Revert "cxl: Add support for interrupts on the Mellanox CX4"
Remove abandonned capi support for the Mellanox CX4.
This reverts commit a2f67d5ee8
.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
parent
c582815006
commit
0cfd7335d1
@ -8,7 +8,6 @@
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*/
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <asm/pci-bridge.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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@ -292,86 +291,3 @@ void pnv_cxl_disable_device(struct pci_dev *dev)
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cxl_pci_disable_device(dev);
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cxl_afu_put(afu);
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}
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/*
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* This is a special version of pnv_setup_msi_irqs for cards in cxl mode. This
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* function handles setting up the IVTE entries for the XSL to use.
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*
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* We are currently not filling out the MSIX table, since the only currently
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* supported adapter (CX4) uses a custom MSIX table format in cxl mode and it
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* is up to their driver to fill that out. In the future we may fill out the
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* MSIX table (and change the IVTE entries to be an index to the MSIX table)
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* for adapters implementing the Full MSI-X mode described in the CAIA.
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*/
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int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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struct cxl_context *ctx = NULL;
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unsigned int virq;
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int hwirq;
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int afu_irq = 0;
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int rc;
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if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
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return -ENODEV;
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if (pdev->no_64bit_msi && !phb->msi32_support)
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return -ENODEV;
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rc = cxl_cx4_setup_msi_irqs(pdev, nvec, type);
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if (rc)
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return rc;
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for_each_pci_msi_entry(entry, pdev) {
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if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
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pr_warn("%s: Supports only 64-bit MSIs\n",
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pci_name(pdev));
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return -ENXIO;
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}
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hwirq = cxl_next_msi_hwirq(pdev, &ctx, &afu_irq);
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if (WARN_ON(hwirq <= 0))
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return (hwirq ? hwirq : -ENOMEM);
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virq = irq_create_mapping(NULL, hwirq);
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if (!virq) {
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pr_warn("%s: Failed to map cxl mode MSI to linux irq\n",
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pci_name(pdev));
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return -ENOMEM;
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}
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rc = pnv_cxl_ioda_msi_setup(pdev, hwirq, virq);
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if (rc) {
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pr_warn("%s: Failed to setup cxl mode MSI\n", pci_name(pdev));
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irq_dispose_mapping(virq);
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return rc;
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}
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irq_set_msi_desc(virq, entry);
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}
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return 0;
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}
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void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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irq_hw_number_t hwirq;
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if (WARN_ON(!phb))
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return;
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for_each_pci_msi_entry(entry, pdev) {
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if (!entry->irq)
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continue;
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hwirq = virq_to_hw(entry->irq);
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irq_set_msi_desc(entry->irq, NULL);
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irq_dispose_mapping(entry->irq);
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}
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cxl_cx4_teardown_msi_irqs(pdev);
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}
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@ -3847,10 +3847,6 @@ static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
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const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
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.dma_dev_setup = pnv_pci_dma_dev_setup,
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.dma_bus_setup = pnv_pci_dma_bus_setup,
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#ifdef CONFIG_PCI_MSI
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.setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
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.teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
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#endif
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.enable_device_hook = pnv_cxl_enable_device_hook,
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.disable_device = pnv_cxl_disable_device,
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.release_device = pnv_pci_release_device,
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@ -265,8 +265,6 @@ extern int pnv_npu2_init(struct pnv_phb *phb);
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/* cxl functions */
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extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
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extern void pnv_cxl_disable_device(struct pci_dev *dev);
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extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
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/* phb ops (cxl switches these when enabling the kernel api on the phb) */
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@ -11,7 +11,6 @@
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#include <linux/slab.h>
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#include <linux/file.h>
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#include <misc/cxl.h>
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#include <linux/msi.h>
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#include <linux/module.h>
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#include <linux/mount.h>
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#include <linux/sched/mm.h>
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@ -595,73 +594,3 @@ int cxl_get_max_irqs_per_process(struct pci_dev *dev)
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return afu->irqs_max;
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}
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EXPORT_SYMBOL_GPL(cxl_get_max_irqs_per_process);
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/*
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* This is a special interrupt allocation routine called from the PHB's MSI
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* setup function. When capi interrupts are allocated in this manner they must
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* still be associated with a running context, but since the MSI APIs have no
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* way to specify this we use the default context associated with the device.
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*
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* The Mellanox CX4 has a hardware limitation that restricts the maximum AFU
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* interrupt number, so in order to overcome this their driver informs us of
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* the restriction by setting the maximum interrupts per context, and we
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* allocate additional contexts as necessary so that we can keep the AFU
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* interrupt number within the supported range.
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*/
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int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct cxl_context *ctx, *new_ctx, *default_ctx;
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int remaining;
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int rc;
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ctx = default_ctx = cxl_get_context(pdev);
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if (WARN_ON(!default_ctx))
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return -ENODEV;
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remaining = nvec;
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while (remaining > 0) {
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rc = cxl_allocate_afu_irqs(ctx, min(remaining, ctx->afu->irqs_max));
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if (rc) {
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pr_warn("%s: Failed to find enough free MSIs\n", pci_name(pdev));
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return rc;
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}
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remaining -= ctx->afu->irqs_max;
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if (ctx != default_ctx && default_ctx->status == STARTED) {
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WARN_ON(cxl_start_context(ctx,
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be64_to_cpu(default_ctx->elem->common.wed),
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NULL));
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}
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if (remaining > 0) {
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new_ctx = cxl_dev_context_init(pdev);
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if (IS_ERR(new_ctx)) {
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pr_warn("%s: Failed to allocate enough contexts for MSIs\n", pci_name(pdev));
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return -ENOSPC;
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}
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list_add(&new_ctx->extra_irq_contexts, &ctx->extra_irq_contexts);
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ctx = new_ctx;
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}
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}
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return 0;
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}
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/* Exported via cxl_base */
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void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct cxl_context *ctx, *pos, *tmp;
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ctx = cxl_get_context(pdev);
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if (WARN_ON(!ctx))
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return;
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cxl_free_afu_irqs(ctx);
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list_for_each_entry_safe(pos, tmp, &ctx->extra_irq_contexts, extra_irq_contexts) {
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cxl_stop_context(pos);
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cxl_free_afu_irqs(pos);
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list_del(&pos->extra_irq_contexts);
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cxl_release_context(pos);
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}
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}
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/* Exported via cxl_base */
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@ -158,37 +158,6 @@ int cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_
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}
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EXPORT_SYMBOL_GPL(cxl_next_msi_hwirq);
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int cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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int ret;
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struct cxl_calls *calls;
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calls = cxl_calls_get();
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if (!calls)
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return false;
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ret = calls->cxl_cx4_setup_msi_irqs(pdev, nvec, type);
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cxl_calls_put(calls);
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return ret;
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}
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EXPORT_SYMBOL_GPL(cxl_cx4_setup_msi_irqs);
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void cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct cxl_calls *calls;
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calls = cxl_calls_get();
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if (!calls)
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return;
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calls->cxl_cx4_teardown_msi_irqs(pdev);
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cxl_calls_put(calls);
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}
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EXPORT_SYMBOL_GPL(cxl_cx4_teardown_msi_irqs);
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static int __init cxl_base_init(void)
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{
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struct device_node *np;
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@ -879,16 +879,12 @@ ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
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bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
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void _cxl_pci_disable_device(struct pci_dev *dev);
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int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
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int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
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struct cxl_calls {
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void (*cxl_slbia)(struct mm_struct *mm);
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bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
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void (*cxl_pci_disable_device)(struct pci_dev *dev);
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int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
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int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
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void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
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struct module *owner;
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};
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@ -107,8 +107,6 @@ static struct cxl_calls cxl_calls = {
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.cxl_pci_associate_default_context = _cxl_pci_associate_default_context,
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.cxl_pci_disable_device = _cxl_pci_disable_device,
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.cxl_next_msi_hwirq = _cxl_next_msi_hwirq,
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.cxl_cx4_setup_msi_irqs = _cxl_cx4_setup_msi_irqs,
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.cxl_cx4_teardown_msi_irqs = _cxl_cx4_teardown_msi_irqs,
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.owner = THIS_MODULE,
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};
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@ -43,8 +43,6 @@ void cxl_afu_put(struct cxl_afu *afu);
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void cxl_slbia(struct mm_struct *mm);
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bool cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
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void cxl_pci_disable_device(struct pci_dev *dev);
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int cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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void cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
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#else /* CONFIG_CXL_BASE */
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@ -54,8 +52,6 @@ static inline void cxl_afu_put(struct cxl_afu *afu) {}
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static inline void cxl_slbia(struct mm_struct *mm) {}
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static inline bool cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu) { return false; }
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static inline void cxl_pci_disable_device(struct pci_dev *dev) {}
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static inline int cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) { return -ENODEV; }
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static inline void cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev) {}
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#endif /* CONFIG_CXL_BASE */
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