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MIPS: CMP: Fix physical core number calculation logic

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The CPUNum Field in EBase register is 10bit wide, so after 1 bit right
shift, the mask value should be 0x1ff.

Signed-off-by: jerin jacob <jerinjacobk@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4420/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
jerin jacob 2012-10-11 22:18:51 +05:30 committed by Ralf Baechle
parent a12265400c
commit 0cc40dac86
1 changed files with 1 additions and 1 deletions
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2
arch/mips/kernel/smp-cmp.c
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@ -97,7 +97,7 @@ static void cmp_init_secondary(void)
/* Enable per-cpu interrupts: platform specific */
c->core = (read_c0_ebase() >> 1) & 0xff;
c->core = (read_c0_ebase() >> 1) & 0x1ff;
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
#endif