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RISC-V: KVM: Implement perf support without sampling
RISC-V SBI PMU & Sscofpmf ISA extension allows supporting perf in the virtualization enviornment as well. KVM implementation relies on SBI PMU extension for the most part while trapping & emulating the CSRs read for counter access. This patch doesn't have the event sampling support yet. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Atish Patra
Anup Patel
parent
a9ac6c3752
commit
0cb74b65d2
@ -14,8 +14,187 @@
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#include <asm/csr.h>
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#include <asm/kvm_vcpu_sbi.h>
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#include <asm/kvm_vcpu_pmu.h>
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#include <linux/bitops.h>
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#define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs)
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#define get_event_type(x) (((x) & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16)
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#define get_event_code(x) ((x) & SBI_PMU_EVENT_IDX_CODE_MASK)
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static enum perf_hw_id hw_event_perf_map[SBI_PMU_HW_GENERAL_MAX] = {
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[SBI_PMU_HW_CPU_CYCLES] = PERF_COUNT_HW_CPU_CYCLES,
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[SBI_PMU_HW_INSTRUCTIONS] = PERF_COUNT_HW_INSTRUCTIONS,
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[SBI_PMU_HW_CACHE_REFERENCES] = PERF_COUNT_HW_CACHE_REFERENCES,
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[SBI_PMU_HW_CACHE_MISSES] = PERF_COUNT_HW_CACHE_MISSES,
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[SBI_PMU_HW_BRANCH_INSTRUCTIONS] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
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[SBI_PMU_HW_BRANCH_MISSES] = PERF_COUNT_HW_BRANCH_MISSES,
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[SBI_PMU_HW_BUS_CYCLES] = PERF_COUNT_HW_BUS_CYCLES,
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[SBI_PMU_HW_STALLED_CYCLES_FRONTEND] = PERF_COUNT_HW_STALLED_CYCLES_FRONTEND,
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[SBI_PMU_HW_STALLED_CYCLES_BACKEND] = PERF_COUNT_HW_STALLED_CYCLES_BACKEND,
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[SBI_PMU_HW_REF_CPU_CYCLES] = PERF_COUNT_HW_REF_CPU_CYCLES,
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};
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static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc)
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{
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u64 counter_val_mask = GENMASK(pmc->cinfo.width, 0);
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u64 sample_period;
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if (!pmc->counter_val)
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sample_period = counter_val_mask + 1;
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else
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sample_period = (-pmc->counter_val) & counter_val_mask;
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return sample_period;
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}
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static u32 kvm_pmu_get_perf_event_type(unsigned long eidx)
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{
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enum sbi_pmu_event_type etype = get_event_type(eidx);
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u32 type = PERF_TYPE_MAX;
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switch (etype) {
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case SBI_PMU_EVENT_TYPE_HW:
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type = PERF_TYPE_HARDWARE;
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break;
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case SBI_PMU_EVENT_TYPE_CACHE:
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type = PERF_TYPE_HW_CACHE;
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break;
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case SBI_PMU_EVENT_TYPE_RAW:
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case SBI_PMU_EVENT_TYPE_FW:
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type = PERF_TYPE_RAW;
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break;
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default:
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break;
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}
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return type;
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}
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static bool kvm_pmu_is_fw_event(unsigned long eidx)
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{
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return get_event_type(eidx) == SBI_PMU_EVENT_TYPE_FW;
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}
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static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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perf_event_disable(pmc->perf_event);
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perf_event_release_kernel(pmc->perf_event);
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pmc->perf_event = NULL;
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}
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}
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static u64 kvm_pmu_get_perf_event_hw_config(u32 sbi_event_code)
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{
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return hw_event_perf_map[sbi_event_code];
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}
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static u64 kvm_pmu_get_perf_event_cache_config(u32 sbi_event_code)
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{
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u64 config = U64_MAX;
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unsigned int cache_type, cache_op, cache_result;
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/* All the cache event masks lie within 0xFF. No separate masking is necessary */
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cache_type = (sbi_event_code & SBI_PMU_EVENT_CACHE_ID_CODE_MASK) >>
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SBI_PMU_EVENT_CACHE_ID_SHIFT;
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cache_op = (sbi_event_code & SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK) >>
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SBI_PMU_EVENT_CACHE_OP_SHIFT;
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cache_result = sbi_event_code & SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX ||
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cache_op >= PERF_COUNT_HW_CACHE_OP_MAX ||
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cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return config;
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config = cache_type | (cache_op << 8) | (cache_result << 16);
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return config;
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}
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static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data)
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{
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enum sbi_pmu_event_type etype = get_event_type(eidx);
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u32 ecode = get_event_code(eidx);
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u64 config = U64_MAX;
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switch (etype) {
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case SBI_PMU_EVENT_TYPE_HW:
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if (ecode < SBI_PMU_HW_GENERAL_MAX)
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config = kvm_pmu_get_perf_event_hw_config(ecode);
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break;
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case SBI_PMU_EVENT_TYPE_CACHE:
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config = kvm_pmu_get_perf_event_cache_config(ecode);
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break;
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case SBI_PMU_EVENT_TYPE_RAW:
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config = evt_data & RISCV_PMU_RAW_EVENT_MASK;
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break;
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case SBI_PMU_EVENT_TYPE_FW:
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if (ecode < SBI_PMU_FW_MAX)
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config = (1ULL << 63) | ecode;
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break;
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default:
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break;
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}
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return config;
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}
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static int kvm_pmu_get_fixed_pmc_index(unsigned long eidx)
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{
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u32 etype = kvm_pmu_get_perf_event_type(eidx);
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u32 ecode = get_event_code(eidx);
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if (etype != SBI_PMU_EVENT_TYPE_HW)
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return -EINVAL;
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if (ecode == SBI_PMU_HW_CPU_CYCLES)
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return 0;
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else if (ecode == SBI_PMU_HW_INSTRUCTIONS)
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return 2;
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else
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return -EINVAL;
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}
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static int kvm_pmu_get_programmable_pmc_index(struct kvm_pmu *kvpmu, unsigned long eidx,
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unsigned long cbase, unsigned long cmask)
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{
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int ctr_idx = -1;
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int i, pmc_idx;
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int min, max;
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if (kvm_pmu_is_fw_event(eidx)) {
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/* Firmware counters are mapped 1:1 starting from num_hw_ctrs for simplicity */
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min = kvpmu->num_hw_ctrs;
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max = min + kvpmu->num_fw_ctrs;
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} else {
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/* First 3 counters are reserved for fixed counters */
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min = 3;
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max = kvpmu->num_hw_ctrs;
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}
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for_each_set_bit(i, &cmask, BITS_PER_LONG) {
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pmc_idx = i + cbase;
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if ((pmc_idx >= min && pmc_idx < max) &&
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!test_bit(pmc_idx, kvpmu->pmc_in_use)) {
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ctr_idx = pmc_idx;
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break;
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}
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}
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return ctr_idx;
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}
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static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsigned long eidx,
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unsigned long cbase, unsigned long cmask)
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{
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int ret;
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/* Fixed counters need to be have fixed mapping as they have different width */
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ret = kvm_pmu_get_fixed_pmc_index(eidx);
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if (ret >= 0)
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return ret;
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return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask);
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}
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static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
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unsigned long *out_val)
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@ -34,6 +213,16 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
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return 0;
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}
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static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned long ctr_base,
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unsigned long ctr_mask)
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{
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/* Make sure the we have a valid counter mask requested from the caller */
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if (!ctr_mask || (ctr_base + __fls(ctr_mask) >= kvm_pmu_num_counters(kvpmu)))
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return -EINVAL;
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return 0;
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}
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int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask)
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@ -98,7 +287,39 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags, u64 ival,
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struct kvm_vcpu_sbi_return *retdata)
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{
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/* TODO */
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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int i, pmc_index, sbiret = 0;
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struct kvm_pmc *pmc;
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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/* Start the counters that have been configured and requested by the guest */
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for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) {
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pmc_index = i + ctr_base;
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if (!test_bit(pmc_index, kvpmu->pmc_in_use))
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continue;
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pmc = &kvpmu->pmc[pmc_index];
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if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
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pmc->counter_val = ival;
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if (pmc->perf_event) {
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if (unlikely(pmc->started)) {
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sbiret = SBI_ERR_ALREADY_STARTED;
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continue;
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}
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perf_event_period(pmc->perf_event, kvm_pmu_get_sample_period(pmc));
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perf_event_enable(pmc->perf_event);
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pmc->started = true;
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} else {
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sbiret = SBI_ERR_INVALID_PARAM;
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}
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}
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out:
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retdata->err_val = sbiret;
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return 0;
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}
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@ -106,7 +327,46 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags,
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struct kvm_vcpu_sbi_return *retdata)
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{
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/* TODO */
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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int i, pmc_index, sbiret = 0;
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u64 enabled, running;
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struct kvm_pmc *pmc;
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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/* Stop the counters that have been configured and requested by the guest */
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for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) {
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pmc_index = i + ctr_base;
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if (!test_bit(pmc_index, kvpmu->pmc_in_use))
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continue;
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pmc = &kvpmu->pmc[pmc_index];
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if (pmc->perf_event) {
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if (pmc->started) {
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/* Stop counting the counter */
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perf_event_disable(pmc->perf_event);
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pmc->started = false;
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} else {
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sbiret = SBI_ERR_ALREADY_STOPPED;
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}
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if (flags & SBI_PMU_STOP_FLAG_RESET) {
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/* Relase the counter if this is a reset request */
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pmc->counter_val += perf_event_read_value(pmc->perf_event,
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&enabled, &running);
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kvm_pmu_release_perf_event(pmc);
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clear_bit(pmc_index, kvpmu->pmc_in_use);
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}
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} else {
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sbiret = SBI_ERR_INVALID_PARAM;
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}
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}
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out:
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retdata->err_val = sbiret;
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return 0;
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}
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@ -115,7 +375,87 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
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unsigned long eidx, u64 evtdata,
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struct kvm_vcpu_sbi_return *retdata)
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{
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/* TODO */
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int ctr_idx, sbiret = 0;
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u64 config;
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u32 etype = kvm_pmu_get_perf_event_type(eidx);
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct perf_event *event;
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struct kvm_pmc *pmc;
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struct perf_event_attr attr = {
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.type = etype,
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.size = sizeof(struct perf_event_attr),
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.pinned = true,
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/*
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* It should never reach here if the platform doesn't support the sscofpmf
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* extension as mode filtering won't work without it.
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*/
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.exclude_host = true,
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.exclude_hv = true,
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.exclude_user = !!(flags & SBI_PMU_CFG_FLAG_SET_UINH),
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.exclude_kernel = !!(flags & SBI_PMU_CFG_FLAG_SET_SINH),
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.config1 = RISCV_PMU_CONFIG1_GUEST_EVENTS,
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};
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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if (kvm_pmu_is_fw_event(eidx)) {
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sbiret = SBI_ERR_NOT_SUPPORTED;
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goto out;
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}
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/*
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* SKIP_MATCH flag indicates the caller is aware of the assigned counter
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* for this event. Just do a sanity check if it already marked used.
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*/
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if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) {
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if (!test_bit(ctr_base + __ffs(ctr_mask), kvpmu->pmc_in_use)) {
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sbiret = SBI_ERR_FAILURE;
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goto out;
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}
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ctr_idx = ctr_base + __ffs(ctr_mask);
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} else {
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ctr_idx = pmu_get_pmc_index(kvpmu, eidx, ctr_base, ctr_mask);
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if (ctr_idx < 0) {
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sbiret = SBI_ERR_NOT_SUPPORTED;
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goto out;
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}
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}
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pmc = &kvpmu->pmc[ctr_idx];
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kvm_pmu_release_perf_event(pmc);
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pmc->idx = ctr_idx;
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config = kvm_pmu_get_perf_event_config(eidx, evtdata);
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attr.config = config;
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if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) {
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//TODO: Do we really want to clear the value in hardware counter
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pmc->counter_val = 0;
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}
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/*
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* Set the default sample_period for now. The guest specified value
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* will be updated in the start call.
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*/
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attr.sample_period = kvm_pmu_get_sample_period(pmc);
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event = perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc);
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if (IS_ERR(event)) {
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pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ERR(event));
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return PTR_ERR(event);
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}
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set_bit(ctr_idx, kvpmu->pmc_in_use);
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pmc->perf_event = event;
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if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
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perf_event_enable(pmc->perf_event);
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retdata->out_val = ctr_idx;
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out:
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retdata->err_val = sbiret;
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return 0;
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}
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@ -197,7 +537,19 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
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void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu)
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{
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/* TODO */
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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int i;
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if (!kvpmu)
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return;
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for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) {
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pmc = &kvpmu->pmc[i];
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pmc->counter_val = 0;
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kvm_pmu_release_perf_event(pmc);
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}
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bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS);
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}
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void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu)
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