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clk: mvebu: adjust AP806 CPU clock frequencies to production chip

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This commit adjusts the list of possible "Sample At Reset" values that
define the CPU clock frequency of the AP806 (part of Marvell Armada
7K/8K) to the values that have been validated with the production
chip. Earlier values were preliminary.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Thomas Petazzoni 2016-12-22 13:08:14 +01:00 committed by Stephen Boyd
parent a2d6ef3a23
commit 0c70ffc5f3
1 changed files with 23 additions and 5 deletions
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28
drivers/clk/mvebu/ap806-system-controller.c
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@ -55,21 +55,39 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
switch (freq_mode) { switch (freq_mode) {
case 0x0 ... 0x5: case 0x0:
case 0x1:
cpuclk_freq = 2000; cpuclk_freq = 2000;
break; break;
case 0x6 ... 0xB: case 0x6:
case 0x7:
cpuclk_freq = 1800; cpuclk_freq = 1800;
break; break;
case 0xC ... 0x11: case 0x4:
case 0xB:
case 0xD:
cpuclk_freq = 1600; cpuclk_freq = 1600;
break; break;
case 0x12 ... 0x16: case 0x1a:
cpuclk_freq = 1400; cpuclk_freq = 1400;
break; break;
case 0x17 ... 0x19: case 0x14:
case 0x17:
cpuclk_freq = 1300; cpuclk_freq = 1300;
break; break;
case 0x19:
cpuclk_freq = 1200;
break;
case 0x13:
case 0x1d:
cpuclk_freq = 1000;
break;
case 0x1c:
cpuclk_freq = 800;
break;
case 0x1b:
cpuclk_freq = 600;
break;
default: default:
dev_err(&pdev->dev, "invalid SAR value\n"); dev_err(&pdev->dev, "invalid SAR value\n");
return -EINVAL; return -EINVAL;