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wireless-drivers-next patches for v5.14
First set of patches for v5.14. Major new features are here support WCN6855 PCI in ath11k and WoWLAN support for wcn36xx. Also smaller fixes and cleanups all over. ath9k * provide STBC info in the received frames brcmfmac * fix setting of station info chains bitmask * correctly report average RSSI in station info rsi * support for changing beacon interval in AP mode ath11k * support for WCN6855 PCI hardware wcn36xx * WoWLAN support with magic packets and GTK rekeying -----BEGIN PGP SIGNATURE----- iQFJBAABCgAzFiEEiBjanGPFTz4PRfLobhckVSbrbZsFAmDKKuIVHGt2YWxvQGNv ZGVhdXJvcmEub3JnAAoJEG4XJFUm622bHU4H/RCyZikVvzFsP2ZHt6WzSlTionTt FN4DZgg3GkgAmpQymR+hdZsen/1DYFB7PiQslfgNCQgRekayRQqbGLcTSbPNsXRg reBVPScdpOm7I1iqcFvJxKXJz2o+HRX9SOY+RGuw9YpzOkfSdXcHfVZHjnfWgmlN xGZY+bPUJRJRKTbALWG8hvVixSQbnIt1H/d55dgXcu/QYsnkDc1xGTWEtYM+/MhU rQrlKk3HrMb7K6t4RYaRd5zANv0XRI3HCJMyVEmut38xH/d79fCGs4dbswZSlt1B 542O21s1wlBdztDjeE30o9ua4zi0b5Pzpnh/tPxaffyUIfFoEnofmqzI0QM= =0pDk -----END PGP SIGNATURE----- Merge tag 'wireless-drivers-next-2021-06-16' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Valo says: ==================== wireless-drivers-next patches for v5.14 First set of patches for v5.14. Major new features are here support WCN6855 PCI in ath11k and WoWLAN support for wcn36xx. Also smaller fixes and cleanups all over. ath9k * provide STBC info in the received frames brcmfmac * fix setting of station info chains bitmask * correctly report average RSSI in station info rsi * support for changing beacon interval in AP mode ath11k * support for WCN6855 PCI hardware wcn36xx * WoWLAN support with magic packets and GTK rekeying ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
0c33795231
@ -442,14 +442,7 @@ static int ath10k_ahb_resource_init(struct ath10k *ar)
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pdev = ar_ahb->pdev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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ath10k_err(ar, "failed to get memory resource\n");
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ret = -ENXIO;
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goto out;
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}
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ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res);
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ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(ar_ahb->mem)) {
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ath10k_err(ar, "mem ioremap error\n");
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ret = PTR_ERR(ar_ahb->mem);
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@ -301,7 +301,7 @@ struct ath10k_fw_stats_pdev {
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s32 underrun;
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u32 hw_paused;
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s32 tx_abort;
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s32 mpdus_requed;
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s32 mpdus_requeued;
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u32 tx_ko;
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u32 data_rc;
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u32 self_triggers;
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@ -1105,7 +1105,7 @@ static const char ath10k_gstrings_stats[][ETH_GSTRING_LEN] = {
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"d_tx_ppdu_reaped",
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"d_tx_fifo_underrun",
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"d_tx_ppdu_abort",
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"d_tx_mpdu_requed",
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"d_tx_mpdu_requeued",
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"d_tx_excessive_retries",
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"d_tx_hw_rate",
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"d_tx_dropped_sw_retries",
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@ -1205,7 +1205,7 @@ void ath10k_debug_get_et_stats(struct ieee80211_hw *hw,
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data[i++] = pdev_stats->hw_reaped;
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data[i++] = pdev_stats->underrun;
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data[i++] = pdev_stats->tx_abort;
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data[i++] = pdev_stats->mpdus_requed;
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data[i++] = pdev_stats->mpdus_requeued;
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data[i++] = pdev_stats->tx_ko;
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data[i++] = pdev_stats->data_rc;
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data[i++] = pdev_stats->sw_retry_failure;
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@ -1283,8 +1283,8 @@ struct htt_dbg_stats_wal_tx_stats {
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/* Num PPDUs cleaned up in TX abort */
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__le32 tx_abort;
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/* Num MPDUs requed by SW */
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__le32 mpdus_requed;
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/* Num MPDUs requeued by SW */
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__le32 mpdus_requeued;
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/* excessive retries */
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__le32 tx_ko;
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@ -1787,7 +1787,6 @@ static bool ath10k_htt_rx_h_frag_pn_check(struct ath10k *ar,
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struct ath10k_peer *peer;
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union htt_rx_pn_t *last_pn, new_pn = {0};
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struct ieee80211_hdr *hdr;
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bool more_frags;
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u8 tid, frag_number;
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u32 seq;
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@ -1805,7 +1804,6 @@ static bool ath10k_htt_rx_h_frag_pn_check(struct ath10k *ar,
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last_pn = &peer->frag_tids_last_pn[tid];
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new_pn.pn48 = ath10k_htt_rx_h_get_pn(ar, skb, offset, enctype);
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more_frags = ieee80211_has_morefrags(hdr->frame_control);
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frag_number = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
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seq = (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
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@ -5592,6 +5592,7 @@ static int ath10k_add_interface(struct ieee80211_hw *hw,
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if (arvif->nohwcrypt &&
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!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
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ret = -EINVAL;
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ath10k_warn(ar, "cryptmode module param needed for sw crypto\n");
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goto err;
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}
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@ -3685,8 +3685,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
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if (bus_params.chip_id != 0xffffffff) {
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if (!ath10k_pci_chip_is_supported(pdev->device,
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bus_params.chip_id))
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bus_params.chip_id)) {
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ret = -ENODEV;
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goto err_unsupported;
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}
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}
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}
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@ -3697,11 +3699,15 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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}
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bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
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if (bus_params.chip_id == 0xffffffff)
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if (bus_params.chip_id == 0xffffffff) {
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ret = -ENODEV;
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goto err_unsupported;
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}
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if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id))
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goto err_free_irq;
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if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
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ret = -ENODEV;
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goto err_unsupported;
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}
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ret = ath10k_core_register(ar, &bus_params);
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if (ret) {
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@ -235,7 +235,6 @@ u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
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void ath10k_pci_hif_power_down(struct ath10k *ar);
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int ath10k_pci_alloc_pipes(struct ath10k *ar);
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void ath10k_pci_free_pipes(struct ath10k *ar);
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void ath10k_pci_free_pipes(struct ath10k *ar);
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void ath10k_pci_rx_replenish_retry(struct timer_list *t);
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void ath10k_pci_ce_deinit(struct ath10k *ar);
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void ath10k_pci_init_napi(struct ath10k *ar);
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@ -2867,7 +2867,7 @@ void ath10k_wmi_pull_pdev_stats_tx(const struct wmi_pdev_stats_tx *src,
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dst->hw_reaped = __le32_to_cpu(src->hw_reaped);
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dst->underrun = __le32_to_cpu(src->underrun);
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dst->tx_abort = __le32_to_cpu(src->tx_abort);
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dst->mpdus_requed = __le32_to_cpu(src->mpdus_requed);
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dst->mpdus_requeued = __le32_to_cpu(src->mpdus_requeued);
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dst->tx_ko = __le32_to_cpu(src->tx_ko);
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dst->data_rc = __le32_to_cpu(src->data_rc);
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dst->self_triggers = __le32_to_cpu(src->self_triggers);
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@ -2895,7 +2895,7 @@ ath10k_wmi_10_4_pull_pdev_stats_tx(const struct wmi_10_4_pdev_stats_tx *src,
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dst->hw_reaped = __le32_to_cpu(src->hw_reaped);
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dst->underrun = __le32_to_cpu(src->underrun);
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dst->tx_abort = __le32_to_cpu(src->tx_abort);
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dst->mpdus_requed = __le32_to_cpu(src->mpdus_requed);
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dst->mpdus_requeued = __le32_to_cpu(src->mpdus_requeued);
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dst->tx_ko = __le32_to_cpu(src->tx_ko);
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dst->data_rc = __le32_to_cpu(src->data_rc);
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dst->self_triggers = __le32_to_cpu(src->self_triggers);
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@ -8270,7 +8270,7 @@ ath10k_wmi_fw_pdev_tx_stats_fill(const struct ath10k_fw_stats_pdev *pdev,
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len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
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"PPDUs cleaned", pdev->tx_abort);
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len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
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"MPDUs requed", pdev->mpdus_requed);
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"MPDUs requeued", pdev->mpdus_requeued);
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len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
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"Excessive retries", pdev->tx_ko);
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len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
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@ -4371,8 +4371,8 @@ struct wmi_pdev_stats_tx {
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/* Num PPDUs cleaned up in TX abort */
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__le32 tx_abort;
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/* Num MPDUs requed by SW */
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__le32 mpdus_requed;
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/* Num MPDUs requeued by SW */
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__le32 mpdus_requeued;
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/* excessive retries */
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__le32 tx_ko;
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@ -4444,8 +4444,8 @@ struct wmi_10_4_pdev_stats_tx {
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/* Num PPDUs cleaned up in TX abort */
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__le32 tx_abort;
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/* Num MPDUs requed by SW */
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__le32 mpdus_requed;
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/* Num MPDUs requeued by SW */
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__le32 mpdus_requeued;
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/* excessive retries */
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__le32 tx_ko;
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@ -7418,7 +7418,6 @@ int ath10k_wmi_wait_for_unified_ready(struct ath10k *ar);
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struct sk_buff *ath10k_wmi_alloc_skb(struct ath10k *ar, u32 len);
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int ath10k_wmi_connect(struct ath10k *ar);
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struct sk_buff *ath10k_wmi_alloc_skb(struct ath10k *ar, u32 len);
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int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id);
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int ath10k_wmi_cmd_send_nowait(struct ath10k *ar, struct sk_buff *skb,
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u32 cmd_id);
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@ -70,6 +70,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.cold_boot_calib = true,
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.supports_suspend = false,
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.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
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.fix_l1ss = true,
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},
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{
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.hw_rev = ATH11K_HW_IPQ6018_HW10,
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@ -110,6 +111,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.cold_boot_calib = true,
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.supports_suspend = false,
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.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
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.fix_l1ss = true,
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},
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{
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.name = "qca6390 hw2.0",
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@ -149,6 +151,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.cold_boot_calib = false,
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.supports_suspend = true,
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.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
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.fix_l1ss = true,
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},
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{
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.name = "qcn9074 hw1.0",
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@ -186,6 +189,47 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.cold_boot_calib = false,
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.supports_suspend = false,
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.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
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.fix_l1ss = true,
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},
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{
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.name = "wcn6855 hw2.0",
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.hw_rev = ATH11K_HW_WCN6855_HW20,
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.fw = {
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.dir = "WCN6855/hw2.0",
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.board_size = 256 * 1024,
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.cal_size = 256 * 1024,
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},
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.max_radios = 3,
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.bdf_addr = 0x4B0C0000,
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.hw_ops = &wcn6855_ops,
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.ring_mask = &ath11k_hw_ring_mask_qca6390,
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.internal_sleep_clock = true,
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.regs = &wcn6855_regs,
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.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
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.host_ce_config = ath11k_host_ce_config_qca6390,
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.ce_count = 9,
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.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
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.target_ce_count = 9,
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.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
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.svc_to_ce_map_len = 14,
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.single_pdev_only = true,
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.rxdma1_enable = false,
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.num_rxmda_per_pdev = 2,
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.rx_mac_buf_ring = true,
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.vdev_start_delay = true,
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.htt_peer_map_v2 = false,
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.tcl_0_only = true,
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.spectral_fft_sz = 0,
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.interface_modes = BIT(NL80211_IFTYPE_STATION) |
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BIT(NL80211_IFTYPE_AP),
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.supports_monitor = false,
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.supports_shadow_regs = true,
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.idle_ps = true,
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.cold_boot_calib = false,
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.supports_suspend = true,
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.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
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.fix_l1ss = false,
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},
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};
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@ -488,7 +532,8 @@ static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
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if (len < ALIGN(ie_len, 4)) {
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ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
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ie_id, ie_len, len);
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return -EINVAL;
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ret = -EINVAL;
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goto err;
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}
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switch (ie_id) {
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|
@ -107,6 +107,7 @@ enum ath11k_hw_rev {
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ATH11K_HW_QCA6390_HW20,
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ATH11K_HW_IPQ6018_HW10,
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ATH11K_HW_QCN9074_HW10,
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ATH11K_HW_WCN6855_HW20,
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};
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|
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enum ath11k_firmware_mode {
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@ -795,8 +796,8 @@ struct ath11k_fw_stats_pdev {
|
||||
s32 underrun;
|
||||
/* Num PPDUs cleaned up in TX abort */
|
||||
s32 tx_abort;
|
||||
/* Num MPDUs requed by SW */
|
||||
s32 mpdus_requed;
|
||||
/* Num MPDUs requeued by SW */
|
||||
s32 mpdus_requeued;
|
||||
/* excessive retries */
|
||||
u32 tx_ko;
|
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/* data hw rate code */
|
||||
|
@ -89,7 +89,7 @@ static inline void htt_print_tx_pdev_stats_cmn_tlv(const void *tag_buf,
|
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len += HTT_DBG_OUT(buf + len, buf_len - len, "tx_abort = %u",
|
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htt_stats_buf->tx_abort);
|
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len += HTT_DBG_OUT(buf + len, buf_len - len, "mpdu_requeued = %u",
|
||||
htt_stats_buf->mpdu_requed);
|
||||
htt_stats_buf->mpdu_requeued);
|
||||
len += HTT_DBG_OUT(buf + len, buf_len - len, "tx_xretry = %u",
|
||||
htt_stats_buf->tx_xretry);
|
||||
len += HTT_DBG_OUT(buf + len, buf_len - len, "data_rc = %u",
|
||||
|
@ -147,7 +147,7 @@ struct htt_tx_pdev_stats_cmn_tlv {
|
||||
u32 hw_flush;
|
||||
u32 hw_filt;
|
||||
u32 tx_abort;
|
||||
u32 mpdu_requed;
|
||||
u32 mpdu_requeued;
|
||||
u32 tx_xretry;
|
||||
u32 data_rc;
|
||||
u32 mpdu_dropped_xretry;
|
||||
|
@ -342,7 +342,6 @@ static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
|
||||
struct ath11k_dp *dp = &ab->dp;
|
||||
struct hal_srng *srng;
|
||||
int i, ret;
|
||||
u32 ring_hash_map;
|
||||
|
||||
ret = ath11k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
|
||||
HAL_SW2WBM_RELEASE, 0, 0,
|
||||
@ -439,20 +438,9 @@ static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
|
||||
}
|
||||
|
||||
/* When hash based routing of rx packet is enabled, 32 entries to map
|
||||
* the hash values to the ring will be configured. Each hash entry uses
|
||||
* three bits to map to a particular ring. The ring mapping will be
|
||||
* 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:Not used.
|
||||
* the hash values to the ring will be configured.
|
||||
*/
|
||||
ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
|
||||
HAL_HASH_ROUTING_RING_SW2 << 3 |
|
||||
HAL_HASH_ROUTING_RING_SW3 << 6 |
|
||||
HAL_HASH_ROUTING_RING_SW4 << 9 |
|
||||
HAL_HASH_ROUTING_RING_SW1 << 12 |
|
||||
HAL_HASH_ROUTING_RING_SW2 << 15 |
|
||||
HAL_HASH_ROUTING_RING_SW3 << 18 |
|
||||
HAL_HASH_ROUTING_RING_SW4 << 21;
|
||||
|
||||
ath11k_hal_reo_hw_setup(ab, ring_hash_map);
|
||||
ab->hw_params.hw_ops->reo_setup(ab);
|
||||
|
||||
return 0;
|
||||
|
||||
|
@ -382,6 +382,16 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
||||
val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
|
||||
|
||||
if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) {
|
||||
ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
|
||||
val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
|
||||
((u64)srng->ring_base_paddr >>
|
||||
HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE,
|
||||
(srng->entry_size * srng->num_entries));
|
||||
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
|
||||
}
|
||||
|
||||
/* interrupt setup */
|
||||
/* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the
|
||||
* unit of 8 usecs instead of 1 usec (as required by v1).
|
||||
|
@ -120,6 +120,7 @@ struct ath11k_base;
|
||||
#define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
|
||||
#define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
|
||||
#define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
|
||||
#define HAL_REO1_MISC_CTL 0x00000630
|
||||
#define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb
|
||||
#define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb
|
||||
#define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id
|
||||
@ -280,6 +281,7 @@ struct ath11k_base;
|
||||
#define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23)
|
||||
#define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2)
|
||||
#define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
|
||||
#define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17)
|
||||
|
||||
/* CE ring bit field mask and shift */
|
||||
#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
|
||||
@ -906,7 +908,6 @@ void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
|
||||
u32 start_seq, enum hal_pn_type type);
|
||||
void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
|
||||
struct hal_srng *srng);
|
||||
void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map);
|
||||
void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
|
||||
struct hal_wbm_idle_scatter_list *sbuf,
|
||||
u32 nsbufs, u32 tot_link_desc,
|
||||
|
@ -801,43 +801,6 @@ void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
|
||||
}
|
||||
}
|
||||
|
||||
void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map)
|
||||
{
|
||||
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
|
||||
u32 val;
|
||||
|
||||
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
|
||||
|
||||
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
|
||||
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
|
||||
HAL_SRNG_RING_ID_REO2SW1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
|
||||
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
}
|
||||
|
||||
static enum hal_rx_mon_status
|
||||
ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
|
||||
struct hal_rx_mon_ppdu_info *ppdu_info,
|
||||
@ -1128,12 +1091,9 @@ ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
|
||||
break;
|
||||
}
|
||||
case HAL_RX_MPDU_START: {
|
||||
struct hal_rx_mpdu_info *mpdu_info =
|
||||
(struct hal_rx_mpdu_info *)tlv_data;
|
||||
u16 peer_id;
|
||||
|
||||
peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
|
||||
__le32_to_cpu(mpdu_info->info0));
|
||||
peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data);
|
||||
if (peer_id)
|
||||
ppdu_info->peer_id = peer_id;
|
||||
break;
|
||||
|
@ -254,12 +254,20 @@ struct hal_rx_phyrx_rssi_legacy_info {
|
||||
} __packed;
|
||||
|
||||
#define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)
|
||||
#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0)
|
||||
|
||||
struct hal_rx_mpdu_info {
|
||||
__le32 rsvd0;
|
||||
__le32 info0;
|
||||
__le32 rsvd1[21];
|
||||
} __packed;
|
||||
|
||||
struct hal_rx_mpdu_info_wcn6855 {
|
||||
__le32 rsvd0[8];
|
||||
__le32 info0;
|
||||
__le32 rsvd1[14];
|
||||
} __packed;
|
||||
|
||||
#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
|
||||
struct hal_rx_ppdu_end_duration {
|
||||
__le32 rsvd0[9];
|
||||
|
@ -10,6 +10,7 @@
|
||||
#include "hw.h"
|
||||
#include "core.h"
|
||||
#include "ce.h"
|
||||
#include "hif.h"
|
||||
|
||||
/* Map from pdev index to hw mac index */
|
||||
static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
|
||||
@ -45,6 +46,13 @@ static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
|
||||
true);
|
||||
}
|
||||
|
||||
static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
|
||||
struct hal_tcl_data_cmd *tcl_cmd)
|
||||
{
|
||||
tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
|
||||
true);
|
||||
}
|
||||
|
||||
static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
|
||||
struct target_resource_config *config)
|
||||
{
|
||||
@ -91,6 +99,52 @@ static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
|
||||
config->num_keep_alive_pattern = 0;
|
||||
}
|
||||
|
||||
static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
|
||||
{
|
||||
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
|
||||
u32 val;
|
||||
/* Each hash entry uses three bits to map to a particular ring. */
|
||||
u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
|
||||
HAL_HASH_ROUTING_RING_SW2 << 3 |
|
||||
HAL_HASH_ROUTING_RING_SW3 << 6 |
|
||||
HAL_HASH_ROUTING_RING_SW4 << 9 |
|
||||
HAL_HASH_ROUTING_RING_SW1 << 12 |
|
||||
HAL_HASH_ROUTING_RING_SW2 << 15 |
|
||||
HAL_HASH_ROUTING_RING_SW3 << 18 |
|
||||
HAL_HASH_ROUTING_RING_SW4 << 21;
|
||||
|
||||
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
|
||||
|
||||
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
|
||||
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
|
||||
HAL_SRNG_RING_ID_REO2SW1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
|
||||
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
}
|
||||
|
||||
static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
|
||||
struct target_resource_config *config)
|
||||
{
|
||||
@ -489,6 +543,228 @@ static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
|
||||
return &desc->u.qcn9074.msdu_payload[0];
|
||||
}
|
||||
|
||||
static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
|
||||
{
|
||||
return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
|
||||
}
|
||||
|
||||
static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
|
||||
{
|
||||
return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
|
||||
}
|
||||
|
||||
static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
|
||||
{
|
||||
return desc->u.wcn6855.hdr_status;
|
||||
}
|
||||
|
||||
static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
|
||||
{
|
||||
return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
|
||||
RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
|
||||
}
|
||||
|
||||
static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
|
||||
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
|
||||
}
|
||||
|
||||
static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
|
||||
{
|
||||
return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
|
||||
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
|
||||
}
|
||||
|
||||
static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
|
||||
{
|
||||
return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
|
||||
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
|
||||
}
|
||||
|
||||
static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
|
||||
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
|
||||
}
|
||||
|
||||
static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO3_SGI,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
|
||||
}
|
||||
|
||||
static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
|
||||
{
|
||||
return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
|
||||
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
|
||||
}
|
||||
|
||||
static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
|
||||
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
|
||||
}
|
||||
|
||||
static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
|
||||
{
|
||||
return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
|
||||
}
|
||||
|
||||
static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
|
||||
struct hal_rx_desc *ldesc)
|
||||
{
|
||||
memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
|
||||
sizeof(struct rx_msdu_end_wcn6855));
|
||||
memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
|
||||
sizeof(struct rx_attention));
|
||||
memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
|
||||
sizeof(struct rx_mpdu_end));
|
||||
}
|
||||
|
||||
static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
|
||||
{
|
||||
return FIELD_GET(HAL_TLV_HDR_TAG,
|
||||
__le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
|
||||
}
|
||||
|
||||
static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
|
||||
{
|
||||
return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
|
||||
}
|
||||
|
||||
static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
|
||||
{
|
||||
u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
|
||||
|
||||
info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
|
||||
info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
|
||||
|
||||
desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
|
||||
}
|
||||
|
||||
static
|
||||
struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
|
||||
{
|
||||
return &desc->u.wcn6855.attention;
|
||||
}
|
||||
|
||||
static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
|
||||
{
|
||||
return &desc->u.wcn6855.msdu_payload[0];
|
||||
}
|
||||
|
||||
static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
|
||||
{
|
||||
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
|
||||
u32 val;
|
||||
/* Each hash entry uses four bits to map to a particular ring. */
|
||||
u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
|
||||
HAL_HASH_ROUTING_RING_SW2 << 4 |
|
||||
HAL_HASH_ROUTING_RING_SW3 << 8 |
|
||||
HAL_HASH_ROUTING_RING_SW4 << 12 |
|
||||
HAL_HASH_ROUTING_RING_SW1 << 16 |
|
||||
HAL_HASH_ROUTING_RING_SW2 << 20 |
|
||||
HAL_HASH_ROUTING_RING_SW3 << 24 |
|
||||
HAL_HASH_ROUTING_RING_SW4 << 28;
|
||||
|
||||
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
|
||||
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
|
||||
|
||||
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL);
|
||||
val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
|
||||
val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val);
|
||||
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
|
||||
ring_hash_map);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
|
||||
ring_hash_map);
|
||||
}
|
||||
|
||||
static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
|
||||
{
|
||||
u16 peer_id = 0;
|
||||
struct hal_rx_mpdu_info *mpdu_info =
|
||||
(struct hal_rx_mpdu_info *)tlv_data;
|
||||
|
||||
peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
|
||||
__le32_to_cpu(mpdu_info->info0));
|
||||
|
||||
return peer_id;
|
||||
}
|
||||
|
||||
static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data)
|
||||
{
|
||||
u16 peer_id = 0;
|
||||
struct hal_rx_mpdu_info_wcn6855 *mpdu_info =
|
||||
(struct hal_rx_mpdu_info_wcn6855 *)tlv_data;
|
||||
|
||||
peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
|
||||
__le32_to_cpu(mpdu_info->info0));
|
||||
return peer_id;
|
||||
}
|
||||
|
||||
const struct ath11k_hw_ops ipq8074_ops = {
|
||||
.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
|
||||
.wmi_init_config = ath11k_init_wmi_config_ipq8074,
|
||||
@ -521,6 +797,8 @@ const struct ath11k_hw_ops ipq8074_ops = {
|
||||
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
|
||||
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
|
||||
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
|
||||
.reo_setup = ath11k_hw_ipq8074_reo_setup,
|
||||
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
|
||||
};
|
||||
|
||||
const struct ath11k_hw_ops ipq6018_ops = {
|
||||
@ -555,6 +833,8 @@ const struct ath11k_hw_ops ipq6018_ops = {
|
||||
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
|
||||
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
|
||||
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
|
||||
.reo_setup = ath11k_hw_ipq8074_reo_setup,
|
||||
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
|
||||
};
|
||||
|
||||
const struct ath11k_hw_ops qca6390_ops = {
|
||||
@ -589,6 +869,8 @@ const struct ath11k_hw_ops qca6390_ops = {
|
||||
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
|
||||
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
|
||||
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
|
||||
.reo_setup = ath11k_hw_ipq8074_reo_setup,
|
||||
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
|
||||
};
|
||||
|
||||
const struct ath11k_hw_ops qcn9074_ops = {
|
||||
@ -623,6 +905,44 @@ const struct ath11k_hw_ops qcn9074_ops = {
|
||||
.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
|
||||
.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
|
||||
.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
|
||||
.reo_setup = ath11k_hw_ipq8074_reo_setup,
|
||||
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
|
||||
};
|
||||
|
||||
const struct ath11k_hw_ops wcn6855_ops = {
|
||||
.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
|
||||
.wmi_init_config = ath11k_init_wmi_config_qca6390,
|
||||
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
|
||||
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
|
||||
.tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
|
||||
.rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
|
||||
.rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
|
||||
.rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
|
||||
.rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
|
||||
.rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
|
||||
.rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
|
||||
.rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
|
||||
.rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
|
||||
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
|
||||
.rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
|
||||
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
|
||||
.rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
|
||||
.rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
|
||||
.rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
|
||||
.rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
|
||||
.rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
|
||||
.rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
|
||||
.rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
|
||||
.rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
|
||||
.rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
|
||||
.rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
|
||||
.rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
|
||||
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
|
||||
.rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
|
||||
.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
|
||||
.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
|
||||
.reo_setup = ath11k_hw_wcn6855_reo_setup,
|
||||
.mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
|
||||
};
|
||||
|
||||
#define ATH11K_TX_RING_MASK_0 0x1
|
||||
@ -1688,3 +2008,74 @@ const struct ath11k_hw_regs qcn9074_regs = {
|
||||
.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
|
||||
.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
|
||||
};
|
||||
|
||||
const struct ath11k_hw_regs wcn6855_regs = {
|
||||
/* SW2TCL(x) R0 ring configuration address */
|
||||
.hal_tcl1_ring_base_lsb = 0x00000690,
|
||||
.hal_tcl1_ring_base_msb = 0x00000694,
|
||||
.hal_tcl1_ring_id = 0x00000698,
|
||||
.hal_tcl1_ring_misc = 0x000006a0,
|
||||
.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
|
||||
.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
|
||||
.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
|
||||
.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
|
||||
.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
|
||||
.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
|
||||
.hal_tcl1_ring_msi1_data = 0x000006e0,
|
||||
.hal_tcl2_ring_base_lsb = 0x000006e8,
|
||||
.hal_tcl_ring_base_lsb = 0x00000798,
|
||||
|
||||
/* TCL STATUS ring address */
|
||||
.hal_tcl_status_ring_base_lsb = 0x000008a0,
|
||||
|
||||
/* REO2SW(x) R0 ring configuration address */
|
||||
.hal_reo1_ring_base_lsb = 0x00000244,
|
||||
.hal_reo1_ring_base_msb = 0x00000248,
|
||||
.hal_reo1_ring_id = 0x0000024c,
|
||||
.hal_reo1_ring_misc = 0x00000254,
|
||||
.hal_reo1_ring_hp_addr_lsb = 0x00000258,
|
||||
.hal_reo1_ring_hp_addr_msb = 0x0000025c,
|
||||
.hal_reo1_ring_producer_int_setup = 0x00000268,
|
||||
.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
|
||||
.hal_reo1_ring_msi1_base_msb = 0x00000290,
|
||||
.hal_reo1_ring_msi1_data = 0x00000294,
|
||||
.hal_reo2_ring_base_lsb = 0x0000029c,
|
||||
.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
|
||||
.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
|
||||
.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
|
||||
.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
|
||||
|
||||
/* REO2SW(x) R2 ring pointers (head/tail) address */
|
||||
.hal_reo1_ring_hp = 0x00003030,
|
||||
.hal_reo1_ring_tp = 0x00003034,
|
||||
.hal_reo2_ring_hp = 0x00003038,
|
||||
|
||||
/* REO2TCL R0 ring configuration address */
|
||||
.hal_reo_tcl_ring_base_lsb = 0x00000454,
|
||||
.hal_reo_tcl_ring_hp = 0x00003060,
|
||||
|
||||
/* REO status address */
|
||||
.hal_reo_status_ring_base_lsb = 0x0000055c,
|
||||
.hal_reo_status_hp = 0x00003078,
|
||||
|
||||
/* WCSS relative address */
|
||||
.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
|
||||
.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
|
||||
.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
|
||||
.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
|
||||
|
||||
/* WBM Idle address */
|
||||
.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
|
||||
.hal_wbm_idle_link_ring_misc = 0x00000880,
|
||||
|
||||
/* SW2WBM release address */
|
||||
.hal_wbm_release_ring_base_lsb = 0x000001e8,
|
||||
|
||||
/* WBM2SW release address */
|
||||
.hal_wbm0_release_ring_base_lsb = 0x00000920,
|
||||
.hal_wbm1_release_ring_base_lsb = 0x00000978,
|
||||
|
||||
/* PCIe base address */
|
||||
.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
|
||||
.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
|
||||
};
|
||||
|
@ -162,6 +162,7 @@ struct ath11k_hw_params {
|
||||
bool cold_boot_calib;
|
||||
bool supports_suspend;
|
||||
u32 hal_desc_sz;
|
||||
bool fix_l1ss;
|
||||
};
|
||||
|
||||
struct ath11k_hw_ops {
|
||||
@ -199,12 +200,15 @@ struct ath11k_hw_ops {
|
||||
void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
|
||||
struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
|
||||
u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
|
||||
void (*reo_setup)(struct ath11k_base *ab);
|
||||
u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
|
||||
};
|
||||
|
||||
extern const struct ath11k_hw_ops ipq8074_ops;
|
||||
extern const struct ath11k_hw_ops ipq6018_ops;
|
||||
extern const struct ath11k_hw_ops qca6390_ops;
|
||||
extern const struct ath11k_hw_ops qcn9074_ops;
|
||||
extern const struct ath11k_hw_ops wcn6855_ops;
|
||||
|
||||
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
|
||||
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
|
||||
@ -318,5 +322,6 @@ struct ath11k_hw_regs {
|
||||
extern const struct ath11k_hw_regs ipq8074_regs;
|
||||
extern const struct ath11k_hw_regs qca6390_regs;
|
||||
extern const struct ath11k_hw_regs qcn9074_regs;
|
||||
extern const struct ath11k_hw_regs wcn6855_regs;
|
||||
|
||||
#endif
|
||||
|
@ -5379,11 +5379,6 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
|
||||
if (WARN_ON(!arvif->is_up))
|
||||
continue;
|
||||
|
||||
ret = ath11k_mac_setup_bcn_tmpl(arvif);
|
||||
if (ret)
|
||||
ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
|
||||
ret);
|
||||
|
||||
ret = ath11k_mac_vdev_restart(arvif, &vifs[i].new_ctx->def);
|
||||
if (ret) {
|
||||
ath11k_warn(ab, "failed to restart vdev %d: %d\n",
|
||||
@ -5391,6 +5386,11 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = ath11k_mac_setup_bcn_tmpl(arvif);
|
||||
if (ret)
|
||||
ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
|
||||
ret);
|
||||
|
||||
ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
|
||||
arvif->bssid);
|
||||
if (ret) {
|
||||
|
@ -354,6 +354,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
|
||||
ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
|
||||
break;
|
||||
case ATH11K_HW_QCA6390_HW20:
|
||||
case ATH11K_HW_WCN6855_HW20:
|
||||
ath11k_mhi_config = &ath11k_mhi_config_qca6390;
|
||||
break;
|
||||
default:
|
||||
|
@ -36,9 +36,11 @@
|
||||
|
||||
#define QCA6390_DEVICE_ID 0x1101
|
||||
#define QCN9074_DEVICE_ID 0x1104
|
||||
#define WCN6855_DEVICE_ID 0x1103
|
||||
|
||||
static const struct pci_device_id ath11k_pci_id_table[] = {
|
||||
{ PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
|
||||
{ PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
|
||||
/* TODO: add QCN9074_DEVICE_ID) once firmware issues are resolved */
|
||||
{0}
|
||||
};
|
||||
@ -432,7 +434,8 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
|
||||
ath11k_pci_enable_ltssm(ab);
|
||||
ath11k_pci_clear_all_intrs(ab);
|
||||
ath11k_pci_set_wlaon_pwr_ctrl(ab);
|
||||
ath11k_pci_fix_l1ss(ab);
|
||||
if (ab->hw_params.fix_l1ss)
|
||||
ath11k_pci_fix_l1ss(ab);
|
||||
}
|
||||
|
||||
ath11k_mhi_clear_vector(ab);
|
||||
@ -1176,12 +1179,26 @@ static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
|
||||
.get_ce_msi_idx = ath11k_pci_get_ce_msi_idx,
|
||||
};
|
||||
|
||||
static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
|
||||
{
|
||||
u32 soc_hw_version;
|
||||
|
||||
soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
|
||||
*major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
|
||||
soc_hw_version);
|
||||
*minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
|
||||
soc_hw_version);
|
||||
|
||||
ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
|
||||
*major, *minor);
|
||||
}
|
||||
|
||||
static int ath11k_pci_probe(struct pci_dev *pdev,
|
||||
const struct pci_device_id *pci_dev)
|
||||
{
|
||||
struct ath11k_base *ab;
|
||||
struct ath11k_pci *ab_pci;
|
||||
u32 soc_hw_version, soc_hw_version_major, soc_hw_version_minor;
|
||||
u32 soc_hw_version_major, soc_hw_version_minor;
|
||||
int ret;
|
||||
|
||||
ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI,
|
||||
@ -1209,15 +1226,8 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
|
||||
|
||||
switch (pci_dev->device) {
|
||||
case QCA6390_DEVICE_ID:
|
||||
soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
|
||||
soc_hw_version_major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
|
||||
soc_hw_version);
|
||||
soc_hw_version_minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
|
||||
soc_hw_version);
|
||||
|
||||
ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
|
||||
soc_hw_version_major, soc_hw_version_minor);
|
||||
|
||||
ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
|
||||
&soc_hw_version_minor);
|
||||
switch (soc_hw_version_major) {
|
||||
case 2:
|
||||
ab->hw_rev = ATH11K_HW_QCA6390_HW20;
|
||||
@ -1235,6 +1245,21 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
|
||||
ab->bus_params.static_window_map = true;
|
||||
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
|
||||
break;
|
||||
case WCN6855_DEVICE_ID:
|
||||
ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
|
||||
&soc_hw_version_minor);
|
||||
switch (soc_hw_version_major) {
|
||||
case 2:
|
||||
ab->hw_rev = ATH11K_HW_WCN6855_HW20;
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
|
||||
soc_hw_version_major, soc_hw_version_minor);
|
||||
ret = -EOPNOTSUPP;
|
||||
goto err_pci_free_region;
|
||||
}
|
||||
ab_pci->msi_config = &ath11k_msi_config[0];
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
|
||||
pci_dev->device);
|
||||
|
@ -368,6 +368,7 @@ struct rx_attention {
|
||||
#define RX_MPDU_START_INFO2_BSSID_HIT BIT(9)
|
||||
#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10)
|
||||
#define RX_MPDU_START_INFO2_TID GENMASK(17, 14)
|
||||
#define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15)
|
||||
|
||||
#define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0)
|
||||
#define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7)
|
||||
@ -546,6 +547,31 @@ struct rx_mpdu_start_qcn9074 {
|
||||
__le32 ht_ctrl;
|
||||
} __packed;
|
||||
|
||||
struct rx_mpdu_start_wcn6855 {
|
||||
__le32 info3;
|
||||
__le32 reo_queue_desc_lo;
|
||||
__le32 info4;
|
||||
__le32 pn[4];
|
||||
__le32 info2;
|
||||
__le32 peer_meta_data;
|
||||
__le16 info0;
|
||||
__le16 phy_ppdu_id;
|
||||
__le16 ast_index;
|
||||
__le16 sw_peer_id;
|
||||
__le32 info1;
|
||||
__le32 info5;
|
||||
__le32 info6;
|
||||
__le16 frame_ctrl;
|
||||
__le16 duration;
|
||||
u8 addr1[ETH_ALEN];
|
||||
u8 addr2[ETH_ALEN];
|
||||
u8 addr3[ETH_ALEN];
|
||||
__le16 seq_ctrl;
|
||||
u8 addr4[ETH_ALEN];
|
||||
__le16 qos_ctrl;
|
||||
__le32 ht_ctrl;
|
||||
} __packed;
|
||||
|
||||
/* rx_mpdu_start
|
||||
*
|
||||
* rxpcu_mpdu_filter_in_category
|
||||
@ -804,6 +830,20 @@ struct rx_msdu_start_qcn9074 {
|
||||
__le16 vlan_stag_c1;
|
||||
} __packed;
|
||||
|
||||
struct rx_msdu_start_wcn6855 {
|
||||
__le16 info0;
|
||||
__le16 phy_ppdu_id;
|
||||
__le32 info1;
|
||||
__le32 info2;
|
||||
__le32 toeplitz_hash;
|
||||
__le32 flow_id_toeplitz;
|
||||
__le32 info3;
|
||||
__le32 ppdu_start_timestamp;
|
||||
__le32 phy_meta_data;
|
||||
__le16 vlan_ctag_ci;
|
||||
__le16 vlan_stag_ci;
|
||||
} __packed;
|
||||
|
||||
/* rx_msdu_start
|
||||
*
|
||||
* rxpcu_mpdu_filter_in_category
|
||||
@ -988,7 +1028,9 @@ struct rx_msdu_start_qcn9074 {
|
||||
|
||||
#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0)
|
||||
#define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14)
|
||||
#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855 BIT(28)
|
||||
#define RX_MSDU_END_INFO2_LAST_MSDU BIT(15)
|
||||
#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855 BIT(29)
|
||||
#define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16)
|
||||
#define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17)
|
||||
#define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18)
|
||||
@ -1037,6 +1079,31 @@ struct rx_msdu_end_ipq8074 {
|
||||
__le16 sa_sw_peer_id;
|
||||
} __packed;
|
||||
|
||||
struct rx_msdu_end_wcn6855 {
|
||||
__le16 info0;
|
||||
__le16 phy_ppdu_id;
|
||||
__le16 ip_hdr_cksum;
|
||||
__le16 reported_mpdu_len;
|
||||
__le32 info1;
|
||||
__le32 ext_wapi_pn[2];
|
||||
__le32 info4;
|
||||
__le32 ipv6_options_crc;
|
||||
__le32 tcp_seq_num;
|
||||
__le32 tcp_ack_num;
|
||||
__le16 info3;
|
||||
__le16 window_size;
|
||||
__le32 info2;
|
||||
__le16 sa_idx;
|
||||
__le16 da_idx;
|
||||
__le32 info5;
|
||||
__le32 fse_metadata;
|
||||
__le16 cce_metadata;
|
||||
__le16 sa_sw_peer_id;
|
||||
__le32 rule_indication[2];
|
||||
__le32 info6;
|
||||
__le32 info7;
|
||||
} __packed;
|
||||
|
||||
#define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0)
|
||||
|
||||
#define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0)
|
||||
@ -1400,10 +1467,30 @@ struct hal_rx_desc_qcn9074 {
|
||||
u8 msdu_payload[0];
|
||||
} __packed;
|
||||
|
||||
struct hal_rx_desc_wcn6855 {
|
||||
__le32 msdu_end_tag;
|
||||
struct rx_msdu_end_wcn6855 msdu_end;
|
||||
__le32 rx_attn_tag;
|
||||
struct rx_attention attention;
|
||||
__le32 msdu_start_tag;
|
||||
struct rx_msdu_start_wcn6855 msdu_start;
|
||||
u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
|
||||
__le32 mpdu_start_tag;
|
||||
struct rx_mpdu_start_wcn6855 mpdu_start;
|
||||
__le32 mpdu_end_tag;
|
||||
struct rx_mpdu_end mpdu_end;
|
||||
u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
|
||||
__le32 hdr_status_tag;
|
||||
__le32 phy_ppdu_id;
|
||||
u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
|
||||
u8 msdu_payload[0];
|
||||
} __packed;
|
||||
|
||||
struct hal_rx_desc {
|
||||
union {
|
||||
struct hal_rx_desc_ipq8074 ipq8074;
|
||||
struct hal_rx_desc_qcn9074 qcn9074;
|
||||
struct hal_rx_desc_wcn6855 wcn6855;
|
||||
} u;
|
||||
} __packed;
|
||||
|
||||
|
@ -5235,7 +5235,7 @@ ath11k_wmi_pull_pdev_stats_tx(const struct wmi_pdev_stats_tx *src,
|
||||
dst->hw_reaped = src->hw_reaped;
|
||||
dst->underrun = src->underrun;
|
||||
dst->tx_abort = src->tx_abort;
|
||||
dst->mpdus_requed = src->mpdus_requed;
|
||||
dst->mpdus_requeued = src->mpdus_requeued;
|
||||
dst->tx_ko = src->tx_ko;
|
||||
dst->data_rc = src->data_rc;
|
||||
dst->self_triggers = src->self_triggers;
|
||||
@ -5505,7 +5505,7 @@ ath11k_wmi_fw_pdev_tx_stats_fill(const struct ath11k_fw_stats_pdev *pdev,
|
||||
len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
|
||||
"PPDUs cleaned", pdev->tx_abort);
|
||||
len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
|
||||
"MPDUs requed", pdev->mpdus_requed);
|
||||
"MPDUs requeued", pdev->mpdus_requeued);
|
||||
len += scnprintf(buf + len, buf_len - len, "%30s %10u\n",
|
||||
"Excessive retries", pdev->tx_ko);
|
||||
len += scnprintf(buf + len, buf_len - len, "%30s %10u\n",
|
||||
|
@ -4171,8 +4171,8 @@ struct wmi_pdev_stats_tx {
|
||||
/* Num PPDUs cleaned up in TX abort */
|
||||
s32 tx_abort;
|
||||
|
||||
/* Num MPDUs requed by SW */
|
||||
s32 mpdus_requed;
|
||||
/* Num MPDUs requeued by SW */
|
||||
s32 mpdus_requeued;
|
||||
|
||||
/* excessive retries */
|
||||
u32 tx_ko;
|
||||
|
@ -855,7 +855,7 @@ ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
|
||||
}
|
||||
|
||||
/**
|
||||
* at5k_hw_stop_rx_pcu() - Stop RX engine
|
||||
* ath5k_hw_stop_rx_pcu() - Stop RX engine
|
||||
* @ah: The &struct ath5k_hw
|
||||
*
|
||||
* Stops RX engine on PCU
|
||||
|
@ -3303,8 +3303,8 @@ static int ath6kl_cfg80211_sscan_start(struct wiphy *wiphy,
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
} else {
|
||||
ret = ath6kl_wmi_bssfilter_cmd(ar->wmi, vif->fw_vif_idx,
|
||||
MATCHED_SSID_FILTER, 0);
|
||||
ret = ath6kl_wmi_bssfilter_cmd(ar->wmi, vif->fw_vif_idx,
|
||||
MATCHED_SSID_FILTER, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
@ -522,6 +522,8 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
|
||||
rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
|
||||
rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
|
||||
rxs->enc_flags |= (rxsp->status4 & AR_GI) ? RX_ENC_FLAG_SHORT_GI : 0;
|
||||
rxs->enc_flags |=
|
||||
(rxsp->status4 & AR_STBC) ? (1 << RX_ENC_FLAG_STBC_SHIFT) : 0;
|
||||
rxs->bw = (rxsp->status4 & AR_2040) ? RATE_INFO_BW_40 : RATE_INFO_BW_20;
|
||||
|
||||
rxs->evm0 = rxsp->status6;
|
||||
|
@ -307,6 +307,11 @@ static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
|
||||
hchan = ah->curchan;
|
||||
}
|
||||
|
||||
if (!hchan) {
|
||||
fastcc = false;
|
||||
hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
|
||||
}
|
||||
|
||||
if (!ath_prepare_reset(sc))
|
||||
fastcc = false;
|
||||
|
||||
|
@ -16,13 +16,11 @@ config CARL9170
|
||||
|
||||
config CARL9170_LEDS
|
||||
bool "SoftLED Support"
|
||||
depends on CARL9170
|
||||
select MAC80211_LEDS
|
||||
select LEDS_CLASS
|
||||
select NEW_LEDS
|
||||
default y
|
||||
depends on CARL9170
|
||||
depends on MAC80211_LEDS
|
||||
help
|
||||
This option is necessary, if you want your device' LEDs to blink
|
||||
This option is necessary, if you want your device's LEDs to blink.
|
||||
|
||||
Say Y, unless you need the LEDs for firmware debugging.
|
||||
|
||||
|
@ -24,7 +24,7 @@
|
||||
#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
|
||||
|
||||
/**
|
||||
* ath_hw_set_bssid_mask - filter out bssids we listen
|
||||
* ath_hw_setbssidmask - filter out bssids we listen
|
||||
*
|
||||
* @common: the ath_common struct for the device.
|
||||
*
|
||||
|
@ -800,7 +800,7 @@ int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
|
||||
(char *)ctl_skb->skb->data, ctl_skb->skb->len);
|
||||
|
||||
/* Move the head of the ring to the next empty descriptor */
|
||||
ch->head_blk_ctl = ctl_skb->next;
|
||||
ch->head_blk_ctl = ctl_skb->next;
|
||||
|
||||
/* Commit all previous writes and set descriptors to VALID */
|
||||
wmb();
|
||||
|
@ -3464,8 +3464,12 @@ struct wcn36xx_hal_rem_bcn_filter_req {
|
||||
#define WCN36XX_HAL_OFFLOAD_DISABLE 0
|
||||
#define WCN36XX_HAL_OFFLOAD_ENABLE 1
|
||||
#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
|
||||
#define WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE 0x4
|
||||
#define WCN36XX_HAL_OFFLOAD_NS_AND_MCAST_FILTER_ENABLE \
|
||||
(WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE)
|
||||
#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
|
||||
(HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
|
||||
(WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE)
|
||||
#define WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX 0x02
|
||||
|
||||
struct wcn36xx_hal_ns_offload_params {
|
||||
u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
|
||||
@ -3487,10 +3491,10 @@ struct wcn36xx_hal_ns_offload_params {
|
||||
/* slot index for this offload */
|
||||
u32 slot_index;
|
||||
u8 bss_index;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct wcn36xx_hal_host_offload_req {
|
||||
u8 offload_Type;
|
||||
u8 offload_type;
|
||||
|
||||
/* enable or disable */
|
||||
u8 enable;
|
||||
@ -3499,13 +3503,13 @@ struct wcn36xx_hal_host_offload_req {
|
||||
u8 host_ipv4_addr[4];
|
||||
u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
|
||||
} u;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct wcn36xx_hal_host_offload_req_msg {
|
||||
struct wcn36xx_hal_msg_header header;
|
||||
struct wcn36xx_hal_host_offload_req host_offload_params;
|
||||
struct wcn36xx_hal_ns_offload_params ns_offload_params;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Packet Types. */
|
||||
#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
|
||||
@ -4901,7 +4905,7 @@ struct wcn36xx_hal_gtk_offload_req_msg {
|
||||
u64 key_replay_counter;
|
||||
|
||||
u8 bss_index;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct wcn36xx_hal_gtk_offload_rsp_msg {
|
||||
struct wcn36xx_hal_msg_header header;
|
||||
@ -4915,7 +4919,7 @@ struct wcn36xx_hal_gtk_offload_rsp_msg {
|
||||
struct wcn36xx_hal_gtk_offload_get_info_req_msg {
|
||||
struct wcn36xx_hal_msg_header header;
|
||||
u8 bss_index;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
|
||||
struct wcn36xx_hal_msg_header header;
|
||||
@ -4939,7 +4943,7 @@ struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
|
||||
u32 igtk_rekey_count;
|
||||
|
||||
u8 bss_index;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct dhcp_info {
|
||||
/* Indicates the device mode which indicates about the DHCP activity */
|
||||
|
@ -25,6 +25,7 @@
|
||||
#include <linux/rpmsg.h>
|
||||
#include <linux/soc/qcom/smem_state.h>
|
||||
#include <linux/soc/qcom/wcnss_ctrl.h>
|
||||
#include <net/ipv6.h>
|
||||
#include "wcn36xx.h"
|
||||
#include "testmode.h"
|
||||
|
||||
@ -172,7 +173,9 @@ static struct ieee80211_supported_band wcn_band_5ghz = {
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static const struct wiphy_wowlan_support wowlan_support = {
|
||||
.flags = WIPHY_WOWLAN_ANY
|
||||
.flags = WIPHY_WOWLAN_ANY |
|
||||
WIPHY_WOWLAN_MAGIC_PKT |
|
||||
WIPHY_WOWLAN_SUPPORTS_GTK_REKEY
|
||||
};
|
||||
|
||||
#endif
|
||||
@ -293,23 +296,16 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
|
||||
goto out_free_dxe_pool;
|
||||
}
|
||||
|
||||
wcn->hal_buf = kmalloc(WCN36XX_HAL_BUF_SIZE, GFP_KERNEL);
|
||||
if (!wcn->hal_buf) {
|
||||
wcn36xx_err("Failed to allocate smd buf\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_free_dxe_ctl;
|
||||
}
|
||||
|
||||
ret = wcn36xx_smd_load_nv(wcn);
|
||||
if (ret) {
|
||||
wcn36xx_err("Failed to push NV to chip\n");
|
||||
goto out_free_smd_buf;
|
||||
goto out_free_dxe_ctl;
|
||||
}
|
||||
|
||||
ret = wcn36xx_smd_start(wcn);
|
||||
if (ret) {
|
||||
wcn36xx_err("Failed to start chip\n");
|
||||
goto out_free_smd_buf;
|
||||
goto out_free_dxe_ctl;
|
||||
}
|
||||
|
||||
if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
|
||||
@ -336,8 +332,6 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
|
||||
|
||||
out_smd_stop:
|
||||
wcn36xx_smd_stop(wcn);
|
||||
out_free_smd_buf:
|
||||
kfree(wcn->hal_buf);
|
||||
out_free_dxe_ctl:
|
||||
wcn36xx_dxe_free_ctl_blks(wcn);
|
||||
out_free_dxe_pool:
|
||||
@ -372,8 +366,6 @@ static void wcn36xx_stop(struct ieee80211_hw *hw)
|
||||
|
||||
wcn36xx_dxe_free_mem_pools(wcn);
|
||||
wcn36xx_dxe_free_ctl_blks(wcn);
|
||||
|
||||
kfree(wcn->hal_buf);
|
||||
}
|
||||
|
||||
static void wcn36xx_change_ps(struct wcn36xx *wcn, bool enable)
|
||||
@ -1088,28 +1080,91 @@ static int wcn36xx_sta_remove(struct ieee80211_hw *hw,
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static struct ieee80211_vif *wcn36xx_get_first_assoc_vif(struct wcn36xx *wcn)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = NULL;
|
||||
struct ieee80211_vif *vif = NULL;
|
||||
|
||||
list_for_each_entry(vif_priv, &wcn->vif_list, list) {
|
||||
if (vif_priv->sta_assoc) {
|
||||
vif = wcn36xx_priv_to_vif(vif_priv);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return vif;
|
||||
}
|
||||
|
||||
static int wcn36xx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wow)
|
||||
{
|
||||
struct wcn36xx *wcn = hw->priv;
|
||||
struct ieee80211_vif *vif = NULL;
|
||||
int ret = 0;
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_MAC, "mac suspend\n");
|
||||
|
||||
flush_workqueue(wcn->hal_ind_wq);
|
||||
wcn36xx_smd_set_power_params(wcn, true);
|
||||
return 0;
|
||||
mutex_lock(&wcn->conf_mutex);
|
||||
|
||||
vif = wcn36xx_get_first_assoc_vif(wcn);
|
||||
if (vif) {
|
||||
ret = wcn36xx_smd_arp_offload(wcn, vif, true);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = wcn36xx_smd_ipv6_ns_offload(wcn, vif, true);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = wcn36xx_smd_gtk_offload(wcn, vif, true);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = wcn36xx_smd_set_power_params(wcn, true);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = wcn36xx_smd_wlan_host_suspend_ind(wcn);
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&wcn->conf_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wcn36xx_resume(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct wcn36xx *wcn = hw->priv;
|
||||
struct ieee80211_vif *vif = NULL;
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_MAC, "mac resume\n");
|
||||
|
||||
flush_workqueue(wcn->hal_ind_wq);
|
||||
wcn36xx_smd_set_power_params(wcn, false);
|
||||
mutex_lock(&wcn->conf_mutex);
|
||||
vif = wcn36xx_get_first_assoc_vif(wcn);
|
||||
if (vif) {
|
||||
wcn36xx_smd_host_resume(wcn);
|
||||
wcn36xx_smd_set_power_params(wcn, false);
|
||||
wcn36xx_smd_gtk_offload_get_info(wcn, vif);
|
||||
wcn36xx_smd_gtk_offload(wcn, vif, false);
|
||||
wcn36xx_smd_ipv6_ns_offload(wcn, vif, false);
|
||||
wcn36xx_smd_arp_offload(wcn, vif, false);
|
||||
}
|
||||
mutex_unlock(&wcn->conf_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void wcn36xx_set_rekey_data(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
struct cfg80211_gtk_rekey_data *data)
|
||||
{
|
||||
struct wcn36xx *wcn = hw->priv;
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
|
||||
mutex_lock(&wcn->conf_mutex);
|
||||
|
||||
memcpy(vif_priv->rekey_data.kek, data->kek, NL80211_KEK_LEN);
|
||||
memcpy(vif_priv->rekey_data.kck, data->kck, NL80211_KCK_LEN);
|
||||
vif_priv->rekey_data.replay_ctr =
|
||||
cpu_to_le64(be64_to_cpup((__be64 *)data->replay_ctr));
|
||||
vif_priv->rekey_data.valid = true;
|
||||
|
||||
mutex_unlock(&wcn->conf_mutex);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static int wcn36xx_ampdu_action(struct ieee80211_hw *hw,
|
||||
@ -1176,6 +1231,34 @@ static int wcn36xx_ampdu_action(struct ieee80211_hw *hw,
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_IPV6)
|
||||
static void wcn36xx_ipv6_addr_change(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
struct inet6_dev *idev)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct inet6_ifaddr *ifa;
|
||||
int idx = 0;
|
||||
|
||||
memset(vif_priv->tentative_addrs, 0, sizeof(vif_priv->tentative_addrs));
|
||||
|
||||
read_lock_bh(&idev->lock);
|
||||
list_for_each_entry(ifa, &idev->addr_list, if_list) {
|
||||
vif_priv->target_ipv6_addrs[idx] = ifa->addr;
|
||||
if (ifa->flags & IFA_F_TENTATIVE)
|
||||
__set_bit(idx, vif_priv->tentative_addrs);
|
||||
idx++;
|
||||
if (idx >= WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX)
|
||||
break;
|
||||
wcn36xx_dbg(WCN36XX_DBG_MAC, "%pI6 %s\n", &ifa->addr,
|
||||
(ifa->flags & IFA_F_TENTATIVE) ? "tentative" : NULL);
|
||||
}
|
||||
read_unlock_bh(&idev->lock);
|
||||
|
||||
vif_priv->num_target_ipv6_addrs = idx;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct ieee80211_ops wcn36xx_ops = {
|
||||
.start = wcn36xx_start,
|
||||
.stop = wcn36xx_stop,
|
||||
@ -1184,6 +1267,7 @@ static const struct ieee80211_ops wcn36xx_ops = {
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = wcn36xx_suspend,
|
||||
.resume = wcn36xx_resume,
|
||||
.set_rekey_data = wcn36xx_set_rekey_data,
|
||||
#endif
|
||||
.config = wcn36xx_config,
|
||||
.prepare_multicast = wcn36xx_prepare_multicast,
|
||||
@ -1199,6 +1283,9 @@ static const struct ieee80211_ops wcn36xx_ops = {
|
||||
.sta_add = wcn36xx_sta_add,
|
||||
.sta_remove = wcn36xx_sta_remove,
|
||||
.ampdu_action = wcn36xx_ampdu_action,
|
||||
#if IS_ENABLED(CONFIG_IPV6)
|
||||
.ipv6_addr_change = wcn36xx_ipv6_addr_change,
|
||||
#endif
|
||||
|
||||
CFG80211_TESTMODE_CMD(wcn36xx_tm_cmd)
|
||||
};
|
||||
@ -1401,6 +1488,12 @@ static int wcn36xx_probe(struct platform_device *pdev)
|
||||
mutex_init(&wcn->hal_mutex);
|
||||
mutex_init(&wcn->scan_lock);
|
||||
|
||||
wcn->hal_buf = devm_kmalloc(wcn->dev, WCN36XX_HAL_BUF_SIZE, GFP_KERNEL);
|
||||
if (!wcn->hal_buf) {
|
||||
ret = -ENOMEM;
|
||||
goto out_wq;
|
||||
}
|
||||
|
||||
ret = dma_set_mask_and_coherent(wcn->dev, DMA_BIT_MASK(32));
|
||||
if (ret < 0) {
|
||||
wcn36xx_err("failed to set DMA mask: %d\n", ret);
|
||||
|
@ -2756,6 +2756,269 @@ out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_arp_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct wcn36xx_hal_host_offload_req_msg msg_body;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_OFFLOAD_REQ);
|
||||
msg_body.host_offload_params.offload_type =
|
||||
WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD;
|
||||
if (enable) {
|
||||
msg_body.host_offload_params.enable =
|
||||
WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE;
|
||||
memcpy(&msg_body.host_offload_params.u,
|
||||
&vif->bss_conf.arp_addr_list[0], sizeof(__be32));
|
||||
}
|
||||
msg_body.ns_offload_params.bss_index = vif_priv->bss_index;
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending host_offload_arp failed\n");
|
||||
goto out;
|
||||
}
|
||||
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
|
||||
if (ret) {
|
||||
wcn36xx_err("host_offload_arp failed err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_IPV6)
|
||||
int wcn36xx_smd_ipv6_ns_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct wcn36xx_hal_host_offload_req_msg msg_body;
|
||||
struct wcn36xx_hal_ns_offload_params *ns_params;
|
||||
struct wcn36xx_hal_host_offload_req *ho_params;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_OFFLOAD_REQ);
|
||||
ho_params = &msg_body.host_offload_params;
|
||||
ns_params = &msg_body.ns_offload_params;
|
||||
|
||||
ho_params->offload_type = WCN36XX_HAL_IPV6_NS_OFFLOAD;
|
||||
if (enable) {
|
||||
ho_params->enable =
|
||||
WCN36XX_HAL_OFFLOAD_NS_AND_MCAST_FILTER_ENABLE;
|
||||
if (vif_priv->num_target_ipv6_addrs) {
|
||||
memcpy(&ho_params->u,
|
||||
&vif_priv->target_ipv6_addrs[0].in6_u,
|
||||
sizeof(struct in6_addr));
|
||||
memcpy(&ns_params->target_ipv6_addr1,
|
||||
&vif_priv->target_ipv6_addrs[0].in6_u,
|
||||
sizeof(struct in6_addr));
|
||||
ns_params->target_ipv6_addr1_valid = 1;
|
||||
}
|
||||
if (vif_priv->num_target_ipv6_addrs > 1) {
|
||||
memcpy(&ns_params->target_ipv6_addr2,
|
||||
&vif_priv->target_ipv6_addrs[1].in6_u,
|
||||
sizeof(struct in6_addr));
|
||||
ns_params->target_ipv6_addr2_valid = 1;
|
||||
}
|
||||
}
|
||||
memcpy(&ns_params->self_addr, vif->addr, ETH_ALEN);
|
||||
ns_params->bss_index = vif_priv->bss_index;
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending host_offload_arp failed\n");
|
||||
goto out;
|
||||
}
|
||||
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
|
||||
if (ret) {
|
||||
wcn36xx_err("host_offload_arp failed err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
int wcn36xx_smd_ipv6_ns_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int wcn36xx_smd_gtk_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct wcn36xx_hal_gtk_offload_req_msg msg_body;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_GTK_OFFLOAD_REQ);
|
||||
|
||||
if (enable) {
|
||||
memcpy(&msg_body.kek, vif_priv->rekey_data.kek, NL80211_KEK_LEN);
|
||||
memcpy(&msg_body.kck, vif_priv->rekey_data.kck, NL80211_KCK_LEN);
|
||||
msg_body.key_replay_counter =
|
||||
le64_to_cpu(vif_priv->rekey_data.replay_ctr);
|
||||
msg_body.bss_index = vif_priv->bss_index;
|
||||
} else {
|
||||
msg_body.flags = WCN36XX_HAL_GTK_OFFLOAD_FLAGS_DISABLE;
|
||||
}
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending host_offload_arp failed\n");
|
||||
goto out;
|
||||
}
|
||||
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
|
||||
if (ret) {
|
||||
wcn36xx_err("host_offload_arp failed err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wcn36xx_smd_gtk_offload_get_info_rsp(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct wcn36xx_hal_gtk_offload_get_info_rsp_msg *rsp;
|
||||
__be64 replay_ctr;
|
||||
|
||||
if (wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len))
|
||||
return -EIO;
|
||||
|
||||
rsp = (struct wcn36xx_hal_gtk_offload_get_info_rsp_msg *)wcn->hal_buf;
|
||||
|
||||
if (rsp->bss_index != vif_priv->bss_index) {
|
||||
wcn36xx_err("gtk_offload_info invalid response bss index %d\n",
|
||||
rsp->bss_index);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
if (vif_priv->rekey_data.replay_ctr != cpu_to_le64(rsp->key_replay_counter)) {
|
||||
replay_ctr = cpu_to_be64(rsp->key_replay_counter);
|
||||
vif_priv->rekey_data.replay_ctr =
|
||||
cpu_to_le64(rsp->key_replay_counter);
|
||||
ieee80211_gtk_rekey_notify(vif, vif->bss_conf.bssid,
|
||||
(void *)&replay_ctr, GFP_KERNEL);
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"GTK replay counter increment %llu\n",
|
||||
rsp->key_replay_counter);
|
||||
}
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"gtk offload info status %d last_rekey_status %d "
|
||||
"replay_counter %llu total_rekey_count %d gtk_rekey_count %d "
|
||||
"igtk_rekey_count %d bss_index %d\n",
|
||||
rsp->status, rsp->last_rekey_status,
|
||||
rsp->key_replay_counter, rsp->total_rekey_count,
|
||||
rsp->gtk_rekey_count, rsp->igtk_rekey_count,
|
||||
rsp->bss_index);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_gtk_offload_get_info(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct wcn36xx_hal_gtk_offload_get_info_req_msg msg_body;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ);
|
||||
|
||||
msg_body.bss_index = vif_priv->bss_index;
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending gtk_offload_get_info failed\n");
|
||||
goto out;
|
||||
}
|
||||
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
|
||||
if (ret) {
|
||||
wcn36xx_err("gtk_offload_get_info failed err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
ret = wcn36xx_smd_gtk_offload_get_info_rsp(wcn, vif);
|
||||
out:
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_wlan_host_suspend_ind(struct wcn36xx *wcn)
|
||||
{
|
||||
struct wcn36xx_hal_wlan_host_suspend_ind_msg msg_body;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_SUSPEND_IND);
|
||||
msg_body.configured_mcst_bcst_filter_setting = 0;
|
||||
msg_body.active_session_count = 1;
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
ret = rpmsg_send(wcn->smd_channel, wcn->hal_buf, msg_body.header.len);
|
||||
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_host_resume(struct wcn36xx *wcn)
|
||||
{
|
||||
struct wcn36xx_hal_wlan_host_resume_req_msg msg_body;
|
||||
struct wcn36xx_hal_host_resume_rsp_msg *rsp;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_RESUME_REQ);
|
||||
msg_body.configured_mcst_bcst_filter_setting = 0;
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending wlan_host_resume failed\n");
|
||||
goto out;
|
||||
}
|
||||
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
|
||||
if (ret) {
|
||||
wcn36xx_err("wlan_host_resume err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
rsp = (struct wcn36xx_hal_host_resume_rsp_msg *)wcn->hal_buf;
|
||||
if (rsp->status)
|
||||
wcn36xx_warn("wlan_host_resume status=%d\n", rsp->status);
|
||||
|
||||
out:
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_rsp_process(struct rpmsg_device *rpdev,
|
||||
void *buf, int len, void *priv, u32 addr)
|
||||
{
|
||||
@ -2804,6 +3067,10 @@ int wcn36xx_smd_rsp_process(struct rpmsg_device *rpdev,
|
||||
case WCN36XX_HAL_8023_MULTICAST_LIST_RSP:
|
||||
case WCN36XX_HAL_START_SCAN_OFFLOAD_RSP:
|
||||
case WCN36XX_HAL_STOP_SCAN_OFFLOAD_RSP:
|
||||
case WCN36XX_HAL_HOST_OFFLOAD_RSP:
|
||||
case WCN36XX_HAL_GTK_OFFLOAD_RSP:
|
||||
case WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP:
|
||||
case WCN36XX_HAL_HOST_RESUME_RSP:
|
||||
memcpy(wcn->hal_buf, buf, len);
|
||||
wcn->hal_rsp_len = len;
|
||||
complete(&wcn->hal_rsp_compl);
|
||||
|
@ -146,4 +146,21 @@ int wcn36xx_smd_rsp_process(struct rpmsg_device *rpdev,
|
||||
int wcn36xx_smd_set_mc_list(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct wcn36xx_hal_rcv_flt_mc_addr_list_type *fp);
|
||||
|
||||
int wcn36xx_smd_arp_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable);
|
||||
|
||||
int wcn36xx_smd_ipv6_ns_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable);
|
||||
|
||||
int wcn36xx_smd_gtk_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
bool enable);
|
||||
|
||||
int wcn36xx_smd_gtk_offload_get_info(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif);
|
||||
|
||||
int wcn36xx_smd_wlan_host_suspend_ind(struct wcn36xx *wcn);
|
||||
|
||||
int wcn36xx_smd_host_resume(struct wcn36xx *wcn);
|
||||
|
||||
#endif /* _SMD_H_ */
|
||||
|
@ -18,6 +18,7 @@
|
||||
#define _WCN36XX_H_
|
||||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/in6.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <net/mac80211.h>
|
||||
@ -136,6 +137,19 @@ struct wcn36xx_vif {
|
||||
u8 self_dpu_desc_index;
|
||||
u8 self_ucast_dpu_sign;
|
||||
|
||||
#if IS_ENABLED(CONFIG_IPV6)
|
||||
/* IPv6 addresses for WoWLAN */
|
||||
struct in6_addr target_ipv6_addrs[WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX];
|
||||
unsigned long tentative_addrs[BITS_TO_LONGS(WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX)];
|
||||
int num_target_ipv6_addrs;
|
||||
#endif
|
||||
/* WoWLAN GTK rekey data */
|
||||
struct {
|
||||
u8 kck[NL80211_KCK_LEN], kek[NL80211_KEK_LEN];
|
||||
__le64 replay_ctr;
|
||||
bool valid;
|
||||
} rekey_data;
|
||||
|
||||
struct list_head sta_list;
|
||||
};
|
||||
|
||||
|
@ -2842,9 +2842,7 @@ void wil_p2p_wdev_free(struct wil6210_priv *wil)
|
||||
wil->radio_wdev = wil->main_ndev->ieee80211_ptr;
|
||||
mutex_unlock(&wil->vif_mutex);
|
||||
if (p2p_wdev) {
|
||||
wiphy_lock(wil->wiphy);
|
||||
cfg80211_unregister_wdev(p2p_wdev);
|
||||
wiphy_unlock(wil->wiphy);
|
||||
kfree(p2p_wdev);
|
||||
}
|
||||
}
|
||||
|
@ -9,7 +9,7 @@
|
||||
#include "wil6210.h"
|
||||
#include "trace.h"
|
||||
|
||||
/**
|
||||
/*
|
||||
* Theory of operation:
|
||||
*
|
||||
* There is ISR pseudo-cause register,
|
||||
|
@ -224,7 +224,7 @@ struct auth_no_hdr {
|
||||
u8 led_polarity = LED_POLARITY_LOW_ACTIVE;
|
||||
|
||||
/**
|
||||
* return AHB address for given firmware internal (linker) address
|
||||
* wmi_addr_remap - return AHB address for given firmware internal (linker) address
|
||||
* @x: internal address
|
||||
* If address have no valid AHB mapping, return 0
|
||||
*/
|
||||
@ -242,7 +242,7 @@ static u32 wmi_addr_remap(u32 x)
|
||||
}
|
||||
|
||||
/**
|
||||
* find fw_mapping entry by section name
|
||||
* wil_find_fw_mapping - find fw_mapping entry by section name
|
||||
* @section: section name
|
||||
*
|
||||
* Return pointer to section or NULL if not found
|
||||
@ -260,7 +260,7 @@ struct fw_map *wil_find_fw_mapping(const char *section)
|
||||
}
|
||||
|
||||
/**
|
||||
* Check address validity for WMI buffer; remap if needed
|
||||
* wmi_buffer_block - Check address validity for WMI buffer; remap if needed
|
||||
* @wil: driver data
|
||||
* @ptr_: internal (linker) fw/ucode address
|
||||
* @size: if non zero, validate the block does not
|
||||
|
@ -4592,58 +4592,11 @@ static void b43_nphy_spur_workaround(struct b43_wldev *dev)
|
||||
{
|
||||
struct b43_phy_n *nphy = dev->phy.n;
|
||||
|
||||
u8 channel = dev->phy.channel;
|
||||
int tone[2] = { 57, 58 };
|
||||
u32 noise[2] = { 0x3FF, 0x3FF };
|
||||
|
||||
B43_WARN_ON(dev->phy.rev < 3);
|
||||
|
||||
if (nphy->hang_avoid)
|
||||
b43_nphy_stay_in_carrier_search(dev, 1);
|
||||
|
||||
if (nphy->gband_spurwar_en) {
|
||||
/* TODO: N PHY Adjust Analog Pfbw (7) */
|
||||
if (channel == 11 && b43_is_40mhz(dev)) {
|
||||
; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
|
||||
} else {
|
||||
; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
|
||||
}
|
||||
/* TODO: N PHY Adjust CRS Min Power (0x1E) */
|
||||
}
|
||||
|
||||
if (nphy->aband_spurwar_en) {
|
||||
if (channel == 54) {
|
||||
tone[0] = 0x20;
|
||||
noise[0] = 0x25F;
|
||||
} else if (channel == 38 || channel == 102 || channel == 118) {
|
||||
if (0 /* FIXME */) {
|
||||
tone[0] = 0x20;
|
||||
noise[0] = 0x21F;
|
||||
} else {
|
||||
tone[0] = 0;
|
||||
noise[0] = 0;
|
||||
}
|
||||
} else if (channel == 134) {
|
||||
tone[0] = 0x20;
|
||||
noise[0] = 0x21F;
|
||||
} else if (channel == 151) {
|
||||
tone[0] = 0x10;
|
||||
noise[0] = 0x23F;
|
||||
} else if (channel == 153 || channel == 161) {
|
||||
tone[0] = 0x30;
|
||||
noise[0] = 0x23F;
|
||||
} else {
|
||||
tone[0] = 0;
|
||||
noise[0] = 0;
|
||||
}
|
||||
|
||||
if (!tone[0] && !noise[0]) {
|
||||
; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
|
||||
} else {
|
||||
; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
|
||||
}
|
||||
}
|
||||
|
||||
if (nphy->hang_avoid)
|
||||
b43_nphy_stay_in_carrier_search(dev, 0);
|
||||
}
|
||||
|
@ -213,19 +213,6 @@ return dev->dma.tx_ring1;
|
||||
return ring;
|
||||
}
|
||||
|
||||
/* Bcm4301-ring to mac80211-queue mapping */
|
||||
static inline int txring_to_priority(struct b43legacy_dmaring *ring)
|
||||
{
|
||||
static const u8 idx_to_prio[] =
|
||||
{ 3, 2, 1, 0, 4, 5, };
|
||||
|
||||
/*FIXME: have only one queue, for now */
|
||||
return 0;
|
||||
|
||||
return idx_to_prio[ring->index];
|
||||
}
|
||||
|
||||
|
||||
static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
|
||||
int controller_idx)
|
||||
{
|
||||
|
@ -391,7 +391,7 @@ void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
|
||||
* registers, we should take care of register overflows.
|
||||
* In theory, the whole tsf read process should be atomic.
|
||||
* We try to be atomic here, by restaring the read process,
|
||||
* if any of the high registers changed (overflew).
|
||||
* if any of the high registers changed (overflowed).
|
||||
*/
|
||||
if (dev->dev->id.revision >= 3) {
|
||||
u32 low;
|
||||
|
@ -2767,8 +2767,9 @@ brcmf_cfg80211_get_station(struct wiphy *wiphy, struct net_device *ndev,
|
||||
struct brcmf_sta_info_le sta_info_le;
|
||||
u32 sta_flags;
|
||||
u32 is_tdls_peer;
|
||||
s32 total_rssi;
|
||||
s32 count_rssi;
|
||||
s32 total_rssi_avg = 0;
|
||||
s32 total_rssi = 0;
|
||||
s32 count_rssi = 0;
|
||||
int rssi;
|
||||
u32 i;
|
||||
|
||||
@ -2834,25 +2835,27 @@ brcmf_cfg80211_get_station(struct wiphy *wiphy, struct net_device *ndev,
|
||||
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES);
|
||||
sinfo->rx_bytes = le64_to_cpu(sta_info_le.rx_tot_bytes);
|
||||
}
|
||||
total_rssi = 0;
|
||||
count_rssi = 0;
|
||||
for (i = 0; i < BRCMF_ANT_MAX; i++) {
|
||||
if (sta_info_le.rssi[i]) {
|
||||
sinfo->chain_signal_avg[count_rssi] =
|
||||
sta_info_le.rssi[i];
|
||||
sinfo->chain_signal[count_rssi] =
|
||||
sta_info_le.rssi[i];
|
||||
total_rssi += sta_info_le.rssi[i];
|
||||
count_rssi++;
|
||||
}
|
||||
if (sta_info_le.rssi[i] == 0 ||
|
||||
sta_info_le.rx_lastpkt_rssi[i] == 0)
|
||||
continue;
|
||||
sinfo->chains |= BIT(count_rssi);
|
||||
sinfo->chain_signal[count_rssi] =
|
||||
sta_info_le.rx_lastpkt_rssi[i];
|
||||
sinfo->chain_signal_avg[count_rssi] =
|
||||
sta_info_le.rssi[i];
|
||||
total_rssi += sta_info_le.rx_lastpkt_rssi[i];
|
||||
total_rssi_avg += sta_info_le.rssi[i];
|
||||
count_rssi++;
|
||||
}
|
||||
if (count_rssi) {
|
||||
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
|
||||
sinfo->chains = count_rssi;
|
||||
|
||||
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
|
||||
total_rssi /= count_rssi;
|
||||
sinfo->signal = total_rssi;
|
||||
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
|
||||
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
|
||||
sinfo->filled |=
|
||||
BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG);
|
||||
sinfo->signal = total_rssi / count_rssi;
|
||||
sinfo->signal_avg = total_rssi_avg / count_rssi;
|
||||
} else if (test_bit(BRCMF_VIF_STATUS_CONNECTED,
|
||||
&ifp->vif->sme_state)) {
|
||||
memset(&scb_val, 0, sizeof(scb_val));
|
||||
@ -7442,18 +7445,23 @@ static s32 brcmf_translate_country_code(struct brcmf_pub *drvr, char alpha2[2],
|
||||
s32 found_index;
|
||||
int i;
|
||||
|
||||
country_codes = drvr->settings->country_codes;
|
||||
if (!country_codes) {
|
||||
brcmf_dbg(TRACE, "No country codes configured for device\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((alpha2[0] == ccreq->country_abbrev[0]) &&
|
||||
(alpha2[1] == ccreq->country_abbrev[1])) {
|
||||
brcmf_dbg(TRACE, "Country code already set\n");
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
country_codes = drvr->settings->country_codes;
|
||||
if (!country_codes) {
|
||||
brcmf_dbg(TRACE, "No country codes configured for device, using ISO3166 code and 0 rev\n");
|
||||
memset(ccreq, 0, sizeof(*ccreq));
|
||||
ccreq->country_abbrev[0] = alpha2[0];
|
||||
ccreq->country_abbrev[1] = alpha2[1];
|
||||
ccreq->ccode[0] = alpha2[0];
|
||||
ccreq->ccode[1] = alpha2[1];
|
||||
return 0;
|
||||
}
|
||||
|
||||
found_index = -1;
|
||||
for (i = 0; i < country_codes->table_size; i++) {
|
||||
cc = &country_codes->table[i];
|
||||
|
@ -32,6 +32,13 @@ static const char BRCM_ ## fw_name ## _FIRMWARE_BASENAME[] = \
|
||||
BRCMF_FW_DEFAULT_PATH fw_base; \
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH fw_base ".bin")
|
||||
|
||||
/* Firmware and Country Local Matrix files */
|
||||
#define BRCMF_FW_CLM_DEF(fw_name, fw_base) \
|
||||
static const char BRCM_ ## fw_name ## _FIRMWARE_BASENAME[] = \
|
||||
BRCMF_FW_DEFAULT_PATH fw_base; \
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH fw_base ".bin"); \
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH fw_base ".clm_blob")
|
||||
|
||||
#define BRCMF_FW_ENTRY(chipid, mask, name) \
|
||||
{ chipid, mask, BRCM_ ## name ## _FIRMWARE_BASENAME }
|
||||
|
||||
|
@ -2037,7 +2037,7 @@ static void brcmf_p2p_get_current_chanspec(struct brcmf_p2p_info *p2p,
|
||||
}
|
||||
|
||||
/**
|
||||
* Change a P2P Role.
|
||||
* brcmf_p2p_ifchange - Change a P2P Role.
|
||||
* @cfg: driver private data for cfg80211 interface.
|
||||
* @if_type: interface type.
|
||||
* Returns 0 if success.
|
||||
|
@ -48,8 +48,8 @@ enum brcmf_pcie_state {
|
||||
BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
|
||||
BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
|
||||
BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
|
||||
BRCMF_FW_DEF(4356, "brcmfmac4356-pcie");
|
||||
BRCMF_FW_DEF(43570, "brcmfmac43570-pcie");
|
||||
BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
|
||||
BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
|
||||
BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
|
||||
BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
|
||||
BRCMF_FW_DEF(4364, "brcmfmac4364-pcie");
|
||||
|
@ -616,18 +616,18 @@ BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
|
||||
BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
|
||||
BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
|
||||
/* Note the names are not postfixed with a1 for backward compatibility */
|
||||
BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio");
|
||||
BRCMF_FW_DEF(43455, "brcmfmac43455-sdio");
|
||||
BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio");
|
||||
BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio");
|
||||
BRCMF_FW_DEF(43456, "brcmfmac43456-sdio");
|
||||
BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
|
||||
BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
|
||||
BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio");
|
||||
BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio");
|
||||
BRCMF_FW_DEF(4359, "brcmfmac4359-sdio");
|
||||
BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
|
||||
BRCMF_FW_DEF(43012, "brcmfmac43012-sdio");
|
||||
BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio");
|
||||
BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio");
|
||||
|
||||
/* firmware config files */
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcm/brcmfmac*-sdio.*.txt");
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcm/brcmfmac*-pcie.*.txt");
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt");
|
||||
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
|
||||
|
||||
static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
|
||||
@ -1291,7 +1291,7 @@ static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
/*
|
||||
* brcmfmac sdio bus specific header
|
||||
* This is the lowest layer header wrapped on the packets transmitted between
|
||||
* host and WiFi dongle which contains information needed for SDIO core and
|
||||
@ -4162,7 +4162,6 @@ static int brcmf_sdio_bus_reset(struct device *dev)
|
||||
if (ret) {
|
||||
brcmf_err("Failed to probe after sdio device reset: ret %d\n",
|
||||
ret);
|
||||
brcmf_sdiod_remove(sdiodev);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
@ -531,9 +531,6 @@ void ai_detach(struct si_pub *sih)
|
||||
|
||||
sii = container_of(sih, struct si_info, pub);
|
||||
|
||||
if (sii == NULL)
|
||||
return;
|
||||
|
||||
kfree(sii);
|
||||
}
|
||||
|
||||
|
@ -1220,6 +1220,7 @@ static int brcms_bcma_probe(struct bcma_device *pdev)
|
||||
{
|
||||
struct brcms_info *wl;
|
||||
struct ieee80211_hw *hw;
|
||||
int ret;
|
||||
|
||||
dev_info(&pdev->dev, "mfg %x core %x rev %d class %d irq %d\n",
|
||||
pdev->id.manuf, pdev->id.id, pdev->id.rev, pdev->id.class,
|
||||
@ -1244,11 +1245,16 @@ static int brcms_bcma_probe(struct bcma_device *pdev)
|
||||
wl = brcms_attach(pdev);
|
||||
if (!wl) {
|
||||
pr_err("%s: brcms_attach failed!\n", __func__);
|
||||
return -ENODEV;
|
||||
ret = -ENODEV;
|
||||
goto err_free_ieee80211;
|
||||
}
|
||||
brcms_led_register(wl);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_ieee80211:
|
||||
ieee80211_free_hw(hw);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int brcms_suspend(struct bcma_device *pdev)
|
||||
|
@ -6607,7 +6607,8 @@ brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
|
||||
rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
|
||||
IEEE80211_STYPE_RTS);
|
||||
|
||||
memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
|
||||
memcpy(&rts->ra, &h->addr1, ETH_ALEN);
|
||||
memcpy(&rts->ta, &h->addr2, ETH_ALEN);
|
||||
}
|
||||
|
||||
/* mainrate
|
||||
|
@ -29,7 +29,6 @@ void brcms_c_stf_ss_update(struct brcms_c_info *wlc, struct brcms_band *band);
|
||||
void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
|
||||
int brcms_c_stf_txchain_set(struct brcms_c_info *wlc, s32 int_val, bool force);
|
||||
bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc, s32 int_val);
|
||||
void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
|
||||
void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc);
|
||||
u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc, u32 rspec);
|
||||
u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc, u32 rspec);
|
||||
|
@ -5356,7 +5356,7 @@ struct ipw2100_wep_key {
|
||||
#define WEP_STR_128(x) x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7],x[8],x[9],x[10]
|
||||
|
||||
/**
|
||||
* Set a the wep key
|
||||
* ipw2100_set_key() - Set a the wep key
|
||||
*
|
||||
* @priv: struct to work on
|
||||
* @idx: index of the key we want to set
|
||||
|
@ -941,7 +941,7 @@ struct lbs_private *lbs_add_card(void *card, struct device *dmdev)
|
||||
wdev->netdev = dev;
|
||||
priv->dev = dev;
|
||||
|
||||
dev->netdev_ops = &lbs_netdev_ops;
|
||||
dev->netdev_ops = &lbs_netdev_ops;
|
||||
dev->watchdog_timeo = 5 * HZ;
|
||||
dev->ethtool_ops = &lbs_ethtool_ops;
|
||||
dev->flags |= IFF_BROADCAST | IFF_MULTICAST;
|
||||
|
@ -151,13 +151,13 @@ static uint16_t lbs_mesh_get_channel(struct lbs_private *priv)
|
||||
*/
|
||||
|
||||
/**
|
||||
* lbs_anycast_get - Get function for sysfs attribute anycast_mask
|
||||
* anycast_mask_show - Get function for sysfs attribute anycast_mask
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t lbs_anycast_get(struct device *dev,
|
||||
struct device_attribute *attr, char * buf)
|
||||
static ssize_t anycast_mask_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_access mesh_access;
|
||||
@ -173,14 +173,15 @@ static ssize_t lbs_anycast_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* lbs_anycast_set - Set function for sysfs attribute anycast_mask
|
||||
* anycast_mask_store - Set function for sysfs attribute anycast_mask
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t lbs_anycast_set(struct device *dev,
|
||||
struct device_attribute *attr, const char * buf, size_t count)
|
||||
static ssize_t anycast_mask_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_access mesh_access;
|
||||
@ -199,13 +200,13 @@ static ssize_t lbs_anycast_set(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* lbs_prb_rsp_limit_get - Get function for sysfs attribute prb_rsp_limit
|
||||
* prb_rsp_limit_show - Get function for sysfs attribute prb_rsp_limit
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t lbs_prb_rsp_limit_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t prb_rsp_limit_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_access mesh_access;
|
||||
@ -225,14 +226,15 @@ static ssize_t lbs_prb_rsp_limit_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* lbs_prb_rsp_limit_set - Set function for sysfs attribute prb_rsp_limit
|
||||
* prb_rsp_limit_store - Set function for sysfs attribute prb_rsp_limit
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t lbs_prb_rsp_limit_set(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
static ssize_t prb_rsp_limit_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_access mesh_access;
|
||||
@ -259,27 +261,28 @@ static ssize_t lbs_prb_rsp_limit_set(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* lbs_mesh_get - Get function for sysfs attribute mesh
|
||||
* lbs_mesh_show - Get function for sysfs attribute mesh
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t lbs_mesh_get(struct device *dev,
|
||||
struct device_attribute *attr, char * buf)
|
||||
static ssize_t lbs_mesh_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
return snprintf(buf, 5, "0x%X\n", !!priv->mesh_dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* lbs_mesh_set - Set function for sysfs attribute mesh
|
||||
* lbs_mesh_store - Set function for sysfs attribute mesh
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t lbs_mesh_set(struct device *dev,
|
||||
struct device_attribute *attr, const char * buf, size_t count)
|
||||
static ssize_t lbs_mesh_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
int enable;
|
||||
@ -301,20 +304,19 @@ static ssize_t lbs_mesh_set(struct device *dev,
|
||||
* lbs_mesh attribute to be exported per ethX interface
|
||||
* through sysfs (/sys/class/net/ethX/lbs_mesh)
|
||||
*/
|
||||
static DEVICE_ATTR(lbs_mesh, 0644, lbs_mesh_get, lbs_mesh_set);
|
||||
static DEVICE_ATTR_RW(lbs_mesh);
|
||||
|
||||
/*
|
||||
* anycast_mask attribute to be exported per mshX interface
|
||||
* through sysfs (/sys/class/net/mshX/anycast_mask)
|
||||
*/
|
||||
static DEVICE_ATTR(anycast_mask, 0644, lbs_anycast_get, lbs_anycast_set);
|
||||
static DEVICE_ATTR_RW(anycast_mask);
|
||||
|
||||
/*
|
||||
* prb_rsp_limit attribute to be exported per mshX interface
|
||||
* through sysfs (/sys/class/net/mshX/prb_rsp_limit)
|
||||
*/
|
||||
static DEVICE_ATTR(prb_rsp_limit, 0644, lbs_prb_rsp_limit_get,
|
||||
lbs_prb_rsp_limit_set);
|
||||
static DEVICE_ATTR_RW(prb_rsp_limit);
|
||||
|
||||
static struct attribute *lbs_mesh_sysfs_entries[] = {
|
||||
&dev_attr_anycast_mask.attr,
|
||||
@ -351,13 +353,13 @@ static int mesh_get_default_parameters(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* bootflag_get - Get function for sysfs attribute bootflag
|
||||
* bootflag_show - Get function for sysfs attribute bootflag
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t bootflag_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t bootflag_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -371,14 +373,14 @@ static ssize_t bootflag_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* bootflag_set - Set function for sysfs attribute bootflag
|
||||
* bootflag_store - Set function for sysfs attribute bootflag
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t bootflag_set(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t bootflag_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
@ -401,13 +403,13 @@ static ssize_t bootflag_set(struct device *dev, struct device_attribute *attr,
|
||||
}
|
||||
|
||||
/**
|
||||
* boottime_get - Get function for sysfs attribute boottime
|
||||
* boottime_show - Get function for sysfs attribute boottime
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t boottime_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t boottime_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -421,14 +423,15 @@ static ssize_t boottime_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* boottime_set - Set function for sysfs attribute boottime
|
||||
* boottime_store - Set function for sysfs attribute boottime
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t boottime_set(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
static ssize_t boottime_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
@ -460,13 +463,13 @@ static ssize_t boottime_set(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* channel_get - Get function for sysfs attribute channel
|
||||
* channel_show - Get function for sysfs attribute channel
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t channel_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t channel_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -480,14 +483,14 @@ static ssize_t channel_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* channel_set - Set function for sysfs attribute channel
|
||||
* channel_store - Set function for sysfs attribute channel
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t channel_set(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t channel_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct lbs_private *priv = to_net_dev(dev)->ml_priv;
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
@ -510,13 +513,13 @@ static ssize_t channel_set(struct device *dev, struct device_attribute *attr,
|
||||
}
|
||||
|
||||
/**
|
||||
* mesh_id_get - Get function for sysfs attribute mesh_id
|
||||
* mesh_id_show - Get function for sysfs attribute mesh_id
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t mesh_id_get(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
static ssize_t mesh_id_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -539,14 +542,14 @@ static ssize_t mesh_id_get(struct device *dev, struct device_attribute *attr,
|
||||
}
|
||||
|
||||
/**
|
||||
* mesh_id_set - Set function for sysfs attribute mesh_id
|
||||
* mesh_id_store - Set function for sysfs attribute mesh_id
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t mesh_id_set(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t mesh_id_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
struct mrvl_mesh_defaults defs;
|
||||
@ -585,13 +588,14 @@ static ssize_t mesh_id_set(struct device *dev, struct device_attribute *attr,
|
||||
}
|
||||
|
||||
/**
|
||||
* protocol_id_get - Get function for sysfs attribute protocol_id
|
||||
* protocol_id_show - Get function for sysfs attribute protocol_id
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t protocol_id_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t protocol_id_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -605,14 +609,15 @@ static ssize_t protocol_id_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* protocol_id_set - Set function for sysfs attribute protocol_id
|
||||
* protocol_id_store - Set function for sysfs attribute protocol_id
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t protocol_id_set(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
static ssize_t protocol_id_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
struct mrvl_mesh_defaults defs;
|
||||
@ -646,13 +651,13 @@ static ssize_t protocol_id_set(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* metric_id_get - Get function for sysfs attribute metric_id
|
||||
* metric_id_show - Get function for sysfs attribute metric_id
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t metric_id_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t metric_id_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -666,14 +671,15 @@ static ssize_t metric_id_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* metric_id_set - Set function for sysfs attribute metric_id
|
||||
* metric_id_store - Set function for sysfs attribute metric_id
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t metric_id_set(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t metric_id_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
struct mrvl_mesh_defaults defs;
|
||||
@ -707,13 +713,13 @@ static ssize_t metric_id_set(struct device *dev, struct device_attribute *attr,
|
||||
}
|
||||
|
||||
/**
|
||||
* capability_get - Get function for sysfs attribute capability
|
||||
* capability_show - Get function for sysfs attribute capability
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer where data will be returned
|
||||
*/
|
||||
static ssize_t capability_get(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
static ssize_t capability_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct mrvl_mesh_defaults defs;
|
||||
int ret;
|
||||
@ -727,14 +733,15 @@ static ssize_t capability_get(struct device *dev,
|
||||
}
|
||||
|
||||
/**
|
||||
* capability_set - Set function for sysfs attribute capability
|
||||
* capability_store - Set function for sysfs attribute capability
|
||||
* @dev: the &struct device
|
||||
* @attr: device attributes
|
||||
* @buf: buffer that contains new attribute value
|
||||
* @count: size of buffer
|
||||
*/
|
||||
static ssize_t capability_set(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t capability_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct cmd_ds_mesh_config cmd;
|
||||
struct mrvl_mesh_defaults defs;
|
||||
@ -768,13 +775,13 @@ static ssize_t capability_set(struct device *dev, struct device_attribute *attr,
|
||||
}
|
||||
|
||||
|
||||
static DEVICE_ATTR(bootflag, 0644, bootflag_get, bootflag_set);
|
||||
static DEVICE_ATTR(boottime, 0644, boottime_get, boottime_set);
|
||||
static DEVICE_ATTR(channel, 0644, channel_get, channel_set);
|
||||
static DEVICE_ATTR(mesh_id, 0644, mesh_id_get, mesh_id_set);
|
||||
static DEVICE_ATTR(protocol_id, 0644, protocol_id_get, protocol_id_set);
|
||||
static DEVICE_ATTR(metric_id, 0644, metric_id_get, metric_id_set);
|
||||
static DEVICE_ATTR(capability, 0644, capability_get, capability_set);
|
||||
static DEVICE_ATTR_RW(bootflag);
|
||||
static DEVICE_ATTR_RW(boottime);
|
||||
static DEVICE_ATTR_RW(channel);
|
||||
static DEVICE_ATTR_RW(mesh_id);
|
||||
static DEVICE_ATTR_RW(protocol_id);
|
||||
static DEVICE_ATTR_RW(metric_id);
|
||||
static DEVICE_ATTR_RW(capability);
|
||||
|
||||
static struct attribute *boot_opts_attrs[] = {
|
||||
&dev_attr_bootflag.attr,
|
||||
|
@ -48,7 +48,7 @@ static int if_usb_submit_rx_urb(struct if_usb_card *cardp);
|
||||
static int if_usb_reset_device(struct lbtf_private *priv);
|
||||
|
||||
/**
|
||||
* if_usb_wrike_bulk_callback - call back to handle URB status
|
||||
* if_usb_write_bulk_callback - call back to handle URB status
|
||||
*
|
||||
* @urb: pointer to urb structure
|
||||
*/
|
||||
|
@ -164,7 +164,7 @@ static int wilc_bus_probe(struct spi_device *spi)
|
||||
wilc->bus_data = spi_priv;
|
||||
wilc->dev_irq_num = spi->irq;
|
||||
|
||||
wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk");
|
||||
wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc");
|
||||
if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) {
|
||||
kfree(spi_priv);
|
||||
return -EPROBE_DEFER;
|
||||
|
@ -1037,7 +1037,7 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
|
||||
* FIXME: if we do not find matching entry, we tell that frame was
|
||||
* posted without any retries. We need to find a way to fix that
|
||||
* and provide retry count.
|
||||
*/
|
||||
*/
|
||||
if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
|
||||
rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
|
||||
mcs = real_mcs;
|
||||
|
@ -446,8 +446,9 @@ static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev,
|
||||
* Beacons and probe responses require the tsf timestamp
|
||||
* to be inserted into the frame.
|
||||
*/
|
||||
if (ieee80211_is_beacon(hdr->frame_control) ||
|
||||
ieee80211_is_probe_resp(hdr->frame_control))
|
||||
if ((ieee80211_is_beacon(hdr->frame_control) ||
|
||||
ieee80211_is_probe_resp(hdr->frame_control)) &&
|
||||
!(tx_info->flags & IEEE80211_TX_CTL_INJECTED))
|
||||
__set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
|
||||
|
||||
if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
|
||||
|
@ -1721,10 +1721,6 @@ static void btc8821a2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 14);
|
||||
coex_dm->ps_tdma_du_adj_type = 14;
|
||||
} else if (max_interval == 3) {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 15);
|
||||
coex_dm->ps_tdma_du_adj_type = 15;
|
||||
} else {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 15);
|
||||
@ -1739,10 +1735,6 @@ static void btc8821a2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 10);
|
||||
coex_dm->ps_tdma_du_adj_type = 10;
|
||||
} else if (max_interval == 3) {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 11);
|
||||
coex_dm->ps_tdma_du_adj_type = 11;
|
||||
} else {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 11);
|
||||
@ -1759,10 +1751,6 @@ static void btc8821a2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 6);
|
||||
coex_dm->ps_tdma_du_adj_type = 6;
|
||||
} else if (max_interval == 3) {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 7);
|
||||
coex_dm->ps_tdma_du_adj_type = 7;
|
||||
} else {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 7);
|
||||
@ -1777,10 +1765,6 @@ static void btc8821a2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 2);
|
||||
coex_dm->ps_tdma_du_adj_type = 2;
|
||||
} else if (max_interval == 3) {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 3);
|
||||
coex_dm->ps_tdma_du_adj_type = 3;
|
||||
} else {
|
||||
btc8821a2ant_ps_tdma(btcoexist,
|
||||
NORMAL_EXEC, true, 3);
|
||||
@ -2810,6 +2794,7 @@ static void btc8821a2ant_action_a2dp(struct btc_coexist *btcoexist)
|
||||
0x4);
|
||||
}
|
||||
|
||||
/* preserve identical branches for further fine-tuning */
|
||||
if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
|
||||
(bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
|
||||
btc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
|
||||
@ -2944,6 +2929,7 @@ static void btc8821a2ant_action_pan_edr(struct btc_coexist *btcoexist)
|
||||
0x4);
|
||||
}
|
||||
|
||||
/* preserve identical branches for further fine-tuning */
|
||||
if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
|
||||
(bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
|
||||
btc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26);
|
||||
@ -3132,6 +3118,7 @@ static void btc8821a2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
|
||||
|
||||
btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
|
||||
|
||||
/* preserve identical branches for further fine-tuning */
|
||||
if (wifi_bw == BTC_WIFI_BW_LEGACY) {
|
||||
/* for HID at 11b/g mode */
|
||||
btc8821a2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff,
|
||||
@ -3321,6 +3308,7 @@ static void btc8821a2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
|
||||
0x4);
|
||||
}
|
||||
|
||||
/* preserve identical branches for further fine-tuning */
|
||||
if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
|
||||
(bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
|
||||
btc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
|
||||
|
@ -167,7 +167,7 @@ void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
|
||||
|
||||
u32 ul_command;
|
||||
u32 ul_content;
|
||||
u32 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
|
||||
u32 ul_enc_algo;
|
||||
|
||||
switch (rtlpriv->sec.pairwise_enc_algorithm) {
|
||||
case WEP40_ENCRYPTION:
|
||||
|
@ -112,7 +112,7 @@ void rtl92c_read_chip_version(struct ieee80211_hw *hw)
|
||||
}
|
||||
|
||||
/**
|
||||
* writeLLT - LLT table write access
|
||||
* rtl92c_llt_write - LLT table write access
|
||||
* @hw: Pointer to the ieee80211_hw structure.
|
||||
* @address: LLT logical address.
|
||||
* @data: LLT data content
|
||||
@ -144,7 +144,7 @@ bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
|
||||
}
|
||||
|
||||
/**
|
||||
* rtl92c_init_LLT_table - Init LLT table
|
||||
* rtl92c_init_llt_table - Init LLT table
|
||||
* @hw: Pointer to the ieee80211_hw structure.
|
||||
* @boundary: Page boundary.
|
||||
*
|
||||
|
@ -513,7 +513,7 @@ void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8,
|
||||
|
||||
/* This bit indicate this packet is used for FW download. */
|
||||
if (tcb_desc->cmd_or_init == DESC_PACKET_TYPE_INIT) {
|
||||
/* For firmware downlaod we only need to set LINIP */
|
||||
/* For firmware download we only need to set LINIP */
|
||||
set_tx_desc_linip(pdesc, tcb_desc->last_inipkt);
|
||||
|
||||
/* 92SE must set as 1 for firmware download HW DMA error */
|
||||
|
@ -915,7 +915,7 @@ int rtl8723e_hw_init(struct ieee80211_hw *hw)
|
||||
struct rtl_phy *rtlphy = &(rtlpriv->phy);
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
|
||||
bool rtstatus = true;
|
||||
bool rtstatus;
|
||||
int err;
|
||||
u8 tmp_u1b;
|
||||
unsigned long flags;
|
||||
|
@ -1036,14 +1036,11 @@ static bool is_associated(struct usbnet *usbdev)
|
||||
{
|
||||
struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev);
|
||||
u8 bssid[ETH_ALEN];
|
||||
int ret;
|
||||
|
||||
if (!priv->radio_on)
|
||||
return false;
|
||||
|
||||
ret = get_bssid(usbdev, bssid);
|
||||
|
||||
return (ret == 0 && !is_zero_ether_addr(bssid));
|
||||
return (get_bssid(usbdev, bssid) == 0 && !is_zero_ether_addr(bssid));
|
||||
}
|
||||
|
||||
static int disassociate(struct usbnet *usbdev, bool reset_ssid)
|
||||
|
@ -203,7 +203,7 @@ int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb)
|
||||
wh->frame_control |= cpu_to_le16(RSI_SET_PS_ENABLE);
|
||||
|
||||
if ((!(info->flags & IEEE80211_TX_INTFL_DONT_ENCRYPT)) &&
|
||||
(common->secinfo.security_enable)) {
|
||||
info->control.hw_key) {
|
||||
if (rsi_is_cipher_wep(common))
|
||||
ieee80211_size += 4;
|
||||
else
|
||||
@ -470,9 +470,9 @@ int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb)
|
||||
}
|
||||
|
||||
if (common->band == NL80211_BAND_2GHZ)
|
||||
bcn_frm->bbp_info |= cpu_to_le16(RSI_RATE_1);
|
||||
bcn_frm->rate_info |= cpu_to_le16(RSI_RATE_1);
|
||||
else
|
||||
bcn_frm->bbp_info |= cpu_to_le16(RSI_RATE_6);
|
||||
bcn_frm->rate_info |= cpu_to_le16(RSI_RATE_6);
|
||||
|
||||
if (mac_bcn->data[tim_offset + 2] == 0)
|
||||
bcn_frm->frame_info |= cpu_to_le16(RSI_DATA_DESC_DTIM_BEACON);
|
||||
|
@ -837,6 +837,23 @@ static void rsi_mac80211_bss_info_changed(struct ieee80211_hw *hw,
|
||||
common->cqm_info.rssi_hyst);
|
||||
}
|
||||
|
||||
if (changed & BSS_CHANGED_BEACON_INT) {
|
||||
rsi_dbg(INFO_ZONE, "%s: Changed Beacon interval: %d\n",
|
||||
__func__, bss_conf->beacon_int);
|
||||
if (common->beacon_interval != bss->beacon_int) {
|
||||
common->beacon_interval = bss->beacon_int;
|
||||
if (vif->type == NL80211_IFTYPE_AP) {
|
||||
struct vif_priv *vif_info = (struct vif_priv *)vif->drv_priv;
|
||||
|
||||
rsi_set_vap_capabilities(common, RSI_OPMODE_AP,
|
||||
vif->addr, vif_info->vap_id,
|
||||
VAP_UPDATE);
|
||||
}
|
||||
}
|
||||
adapter->ps_info.listen_interval =
|
||||
bss->beacon_int * adapter->ps_info.num_bcns_per_lis_int;
|
||||
}
|
||||
|
||||
if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
|
||||
((vif->type == NL80211_IFTYPE_AP) ||
|
||||
(vif->type == NL80211_IFTYPE_P2P_GO))) {
|
||||
@ -1028,7 +1045,6 @@ static int rsi_mac80211_set_key(struct ieee80211_hw *hw,
|
||||
mutex_lock(&common->mutex);
|
||||
switch (cmd) {
|
||||
case SET_KEY:
|
||||
secinfo->security_enable = true;
|
||||
status = rsi_hal_key_config(hw, vif, key, sta);
|
||||
if (status) {
|
||||
mutex_unlock(&common->mutex);
|
||||
@ -1047,8 +1063,6 @@ static int rsi_mac80211_set_key(struct ieee80211_hw *hw,
|
||||
break;
|
||||
|
||||
case DISABLE_KEY:
|
||||
if (vif->type == NL80211_IFTYPE_STATION)
|
||||
secinfo->security_enable = false;
|
||||
rsi_dbg(ERR_ZONE, "%s: RSI del key\n", __func__);
|
||||
memset(key, 0, sizeof(struct ieee80211_key_conf));
|
||||
status = rsi_hal_key_config(hw, vif, key, sta);
|
||||
|
@ -1547,8 +1547,8 @@ static int rsi_eeprom_read(struct rsi_common *common)
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sends a frame to block/unblock
|
||||
* data queues in the firmware
|
||||
* rsi_send_block_unblock_frame() - This function sends a frame to block/unblock
|
||||
* data queues in the firmware
|
||||
*
|
||||
* @common: Pointer to the driver private structure.
|
||||
* @block_event: Event block if true, unblock if false
|
||||
@ -1803,8 +1803,7 @@ int rsi_send_wowlan_request(struct rsi_common *common, u16 flags,
|
||||
RSI_WIFI_MGMT_Q);
|
||||
cmd_frame->desc.desc_dword0.frame_type = WOWLAN_CONFIG_PARAMS;
|
||||
cmd_frame->host_sleep_status = sleep_status;
|
||||
if (common->secinfo.security_enable &&
|
||||
common->secinfo.gtk_cipher)
|
||||
if (common->secinfo.gtk_cipher)
|
||||
flags |= RSI_WOW_GTK_REKEY;
|
||||
if (sleep_status)
|
||||
cmd_frame->wow_flags = flags;
|
||||
|
@ -151,7 +151,6 @@ enum edca_queue {
|
||||
};
|
||||
|
||||
struct security_info {
|
||||
bool security_enable;
|
||||
u32 ptk_cipher;
|
||||
u32 gtk_cipher;
|
||||
};
|
||||
|
@ -53,6 +53,7 @@ static const struct sdio_device_id cw1200_sdio_ids[] = {
|
||||
{ SDIO_DEVICE(SDIO_VENDOR_ID_STE, SDIO_DEVICE_ID_STE_CW1200) },
|
||||
{ /* end: all zeroes */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(sdio, cw1200_sdio_ids);
|
||||
|
||||
/* hwbus_ops implemetation */
|
||||
|
||||
|
@ -75,30 +75,27 @@ int cw1200_hw_scan(struct ieee80211_hw *hw,
|
||||
if (req->n_ssids > WSM_SCAN_MAX_NUM_OF_SSIDS)
|
||||
return -EINVAL;
|
||||
|
||||
/* will be unlocked in cw1200_scan_work() */
|
||||
down(&priv->scan.lock);
|
||||
mutex_lock(&priv->conf_mutex);
|
||||
|
||||
frame.skb = ieee80211_probereq_get(hw, priv->vif->addr, NULL, 0,
|
||||
req->ie_len);
|
||||
if (!frame.skb) {
|
||||
mutex_unlock(&priv->conf_mutex);
|
||||
up(&priv->scan.lock);
|
||||
if (!frame.skb)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (req->ie_len)
|
||||
skb_put_data(frame.skb, req->ie, req->ie_len);
|
||||
|
||||
/* will be unlocked in cw1200_scan_work() */
|
||||
down(&priv->scan.lock);
|
||||
mutex_lock(&priv->conf_mutex);
|
||||
|
||||
ret = wsm_set_template_frame(priv, &frame);
|
||||
if (!ret) {
|
||||
/* Host want to be the probe responder. */
|
||||
ret = wsm_set_probe_responder(priv, true);
|
||||
}
|
||||
if (ret) {
|
||||
dev_kfree_skb(frame.skb);
|
||||
mutex_unlock(&priv->conf_mutex);
|
||||
up(&priv->scan.lock);
|
||||
dev_kfree_skb(frame.skb);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -120,8 +117,8 @@ int cw1200_hw_scan(struct ieee80211_hw *hw,
|
||||
++priv->scan.n_ssids;
|
||||
}
|
||||
|
||||
dev_kfree_skb(frame.skb);
|
||||
mutex_unlock(&priv->conf_mutex);
|
||||
dev_kfree_skb(frame.skb);
|
||||
queue_work(priv->workqueue, &priv->scan.work);
|
||||
return 0;
|
||||
}
|
||||
|
@ -12,7 +12,7 @@
|
||||
#include "acx.h"
|
||||
|
||||
/**
|
||||
* send command to firmware
|
||||
* wl1251_cmd_send - Send command to firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @id: command id
|
||||
@ -59,7 +59,7 @@ out:
|
||||
}
|
||||
|
||||
/**
|
||||
* send test command to firmware
|
||||
* wl1251_cmd_test - Send test command to firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @buf: buffer containing the command, with all headers, must work with dma
|
||||
@ -100,7 +100,7 @@ int wl1251_cmd_test(struct wl1251 *wl, void *buf, size_t buf_len, u8 answer)
|
||||
}
|
||||
|
||||
/**
|
||||
* read acx from firmware
|
||||
* wl1251_cmd_interrogate - Read acx from firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @id: acx id
|
||||
@ -138,7 +138,7 @@ out:
|
||||
}
|
||||
|
||||
/**
|
||||
* write acx value to firmware
|
||||
* wl1251_cmd_configure - Write acx value to firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @id: acx id
|
||||
@ -454,9 +454,12 @@ int wl1251_cmd_scan(struct wl1251 *wl, u8 *ssid, size_t ssid_len,
|
||||
cmd->channels[i].channel = channels[i]->hw_value;
|
||||
}
|
||||
|
||||
cmd->params.ssid_len = ssid_len;
|
||||
if (ssid)
|
||||
memcpy(cmd->params.ssid, ssid, ssid_len);
|
||||
if (ssid) {
|
||||
int len = clamp_val(ssid_len, 0, IEEE80211_MAX_SSID_LEN);
|
||||
|
||||
cmd->params.ssid_len = len;
|
||||
memcpy(cmd->params.ssid, ssid, len);
|
||||
}
|
||||
|
||||
ret = wl1251_cmd_send(wl, CMD_SCAN, cmd, sizeof(*cmd));
|
||||
if (ret < 0) {
|
||||
|
@ -1503,6 +1503,13 @@ static int wl12xx_get_fuse_mac(struct wl1271 *wl)
|
||||
u32 mac1, mac2;
|
||||
int ret;
|
||||
|
||||
/* Device may be in ELP from the bootloader or kexec */
|
||||
ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
usleep_range(500000, 700000);
|
||||
|
||||
ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
@ -821,7 +821,7 @@ out:
|
||||
|
||||
|
||||
/**
|
||||
* send test command to firmware
|
||||
* wl1271_cmd_test - send test command to firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @buf: buffer containing the command, with all headers, must work with dma
|
||||
@ -850,7 +850,7 @@ int wl1271_cmd_test(struct wl1271 *wl, void *buf, size_t buf_len, u8 answer)
|
||||
EXPORT_SYMBOL_GPL(wl1271_cmd_test);
|
||||
|
||||
/**
|
||||
* read acx from firmware
|
||||
* wl1271_cmd_interrogate - read acx from firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @id: acx id
|
||||
@ -879,7 +879,7 @@ int wl1271_cmd_interrogate(struct wl1271 *wl, u16 id, void *buf,
|
||||
}
|
||||
|
||||
/**
|
||||
* write acx value to firmware
|
||||
* wlcore_cmd_configure_failsafe - write acx value to firmware
|
||||
*
|
||||
* @wl: wl struct
|
||||
* @id: acx id
|
||||
|
@ -29,18 +29,20 @@ int wlcore_event_fw_logger(struct wl1271 *wl)
|
||||
u8 *buffer;
|
||||
u32 internal_fw_addrbase = WL18XX_DATA_RAM_BASE_ADDRESS;
|
||||
u32 addr = WL18XX_LOGGER_SDIO_BUFF_ADDR;
|
||||
u32 end_buff_addr = WL18XX_LOGGER_SDIO_BUFF_ADDR +
|
||||
WL18XX_LOGGER_BUFF_OFFSET;
|
||||
u32 addr_ptr;
|
||||
u32 buff_start_ptr;
|
||||
u32 buff_read_ptr;
|
||||
u32 buff_end_ptr;
|
||||
u32 available_len;
|
||||
u32 actual_len;
|
||||
u32 clear_addr;
|
||||
u32 clear_ptr;
|
||||
size_t len;
|
||||
u32 start_loc;
|
||||
|
||||
buffer = kzalloc(WL18XX_LOGGER_SDIO_BUFF_MAX, GFP_KERNEL);
|
||||
if (!buffer) {
|
||||
wl1271_error("Fail to allocate fw logger memory");
|
||||
fw_log.actual_buff_size = cpu_to_le32(0);
|
||||
actual_len = 0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
@ -49,51 +51,58 @@ int wlcore_event_fw_logger(struct wl1271 *wl)
|
||||
if (ret < 0) {
|
||||
wl1271_error("Fail to read logger buffer, error_id = %d",
|
||||
ret);
|
||||
fw_log.actual_buff_size = cpu_to_le32(0);
|
||||
actual_len = 0;
|
||||
goto free_out;
|
||||
}
|
||||
|
||||
memcpy(&fw_log, buffer, sizeof(fw_log));
|
||||
|
||||
if (le32_to_cpu(fw_log.actual_buff_size) == 0)
|
||||
actual_len = le32_to_cpu(fw_log.actual_buff_size);
|
||||
if (actual_len == 0)
|
||||
goto free_out;
|
||||
|
||||
actual_len = le32_to_cpu(fw_log.actual_buff_size);
|
||||
start_loc = (le32_to_cpu(fw_log.buff_read_ptr) -
|
||||
internal_fw_addrbase) - addr;
|
||||
end_buff_addr += le32_to_cpu(fw_log.max_buff_size);
|
||||
available_len = end_buff_addr -
|
||||
(le32_to_cpu(fw_log.buff_read_ptr) -
|
||||
internal_fw_addrbase);
|
||||
actual_len = min(actual_len, available_len);
|
||||
len = actual_len;
|
||||
/* Calculate the internal pointer to the fwlog structure */
|
||||
addr_ptr = internal_fw_addrbase + addr;
|
||||
|
||||
/* Calculate the internal pointers to the start and end of log buffer */
|
||||
buff_start_ptr = addr_ptr + WL18XX_LOGGER_BUFF_OFFSET;
|
||||
buff_end_ptr = buff_start_ptr + le32_to_cpu(fw_log.max_buff_size);
|
||||
|
||||
/* Read the read pointer and validate it */
|
||||
buff_read_ptr = le32_to_cpu(fw_log.buff_read_ptr);
|
||||
if (buff_read_ptr < buff_start_ptr ||
|
||||
buff_read_ptr >= buff_end_ptr) {
|
||||
wl1271_error("buffer read pointer out of bounds: %x not in (%x-%x)\n",
|
||||
buff_read_ptr, buff_start_ptr, buff_end_ptr);
|
||||
goto free_out;
|
||||
}
|
||||
|
||||
start_loc = buff_read_ptr - addr_ptr;
|
||||
available_len = buff_end_ptr - buff_read_ptr;
|
||||
|
||||
/* Copy initial part up to the end of ring buffer */
|
||||
len = min(actual_len, available_len);
|
||||
wl12xx_copy_fwlog(wl, &buffer[start_loc], len);
|
||||
clear_addr = addr + start_loc + le32_to_cpu(fw_log.actual_buff_size) +
|
||||
internal_fw_addrbase;
|
||||
clear_ptr = addr_ptr + start_loc + actual_len;
|
||||
if (clear_ptr == buff_end_ptr)
|
||||
clear_ptr = buff_start_ptr;
|
||||
|
||||
len = le32_to_cpu(fw_log.actual_buff_size) - len;
|
||||
/* Copy any remaining part from beginning of ring buffer */
|
||||
len = actual_len - len;
|
||||
if (len) {
|
||||
wl12xx_copy_fwlog(wl,
|
||||
&buffer[WL18XX_LOGGER_BUFF_OFFSET],
|
||||
len);
|
||||
clear_addr = addr + WL18XX_LOGGER_BUFF_OFFSET + len +
|
||||
internal_fw_addrbase;
|
||||
clear_ptr = addr_ptr + WL18XX_LOGGER_BUFF_OFFSET + len;
|
||||
}
|
||||
|
||||
/* double check that clear address and write pointer are the same */
|
||||
if (clear_addr != le32_to_cpu(fw_log.buff_write_ptr)) {
|
||||
wl1271_error("Calculate of clear addr Clear = %x, write = %x",
|
||||
clear_addr, le32_to_cpu(fw_log.buff_write_ptr));
|
||||
}
|
||||
|
||||
/* indicate FW about Clear buffer */
|
||||
/* Update the read pointer */
|
||||
ret = wlcore_write32(wl, addr + WL18XX_LOGGER_READ_POINT_OFFSET,
|
||||
fw_log.buff_write_ptr);
|
||||
clear_ptr);
|
||||
free_out:
|
||||
kfree(buffer);
|
||||
out:
|
||||
return le32_to_cpu(fw_log.actual_buff_size);
|
||||
return actual_len;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wlcore_event_fw_logger);
|
||||
|
||||
|
@ -3242,8 +3242,8 @@ static void wl1271_op_configure_filter(struct ieee80211_hw *hw,
|
||||
* the firmware filters so that all multicast packets are passed
|
||||
* This is mandatory for MDNS based discovery protocols
|
||||
*/
|
||||
if (wlvif->bss_type == BSS_TYPE_AP_BSS) {
|
||||
if (*total & FIF_ALLMULTI) {
|
||||
if (wlvif->bss_type == BSS_TYPE_AP_BSS) {
|
||||
if (*total & FIF_ALLMULTI) {
|
||||
ret = wl1271_acx_group_address_tbl(wl, wlvif,
|
||||
false,
|
||||
NULL, 0);
|
||||
|
@ -12,9 +12,9 @@
|
||||
#include "debug.h"
|
||||
#include "sysfs.h"
|
||||
|
||||
static ssize_t wl1271_sysfs_show_bt_coex_state(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
static ssize_t bt_coex_state_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct wl1271 *wl = dev_get_drvdata(dev);
|
||||
ssize_t len;
|
||||
@ -30,9 +30,9 @@ static ssize_t wl1271_sysfs_show_bt_coex_state(struct device *dev,
|
||||
|
||||
}
|
||||
|
||||
static ssize_t wl1271_sysfs_store_bt_coex_state(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t bt_coex_state_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct wl1271 *wl = dev_get_drvdata(dev);
|
||||
unsigned long res;
|
||||
@ -71,13 +71,11 @@ static ssize_t wl1271_sysfs_store_bt_coex_state(struct device *dev,
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(bt_coex_state, 0644,
|
||||
wl1271_sysfs_show_bt_coex_state,
|
||||
wl1271_sysfs_store_bt_coex_state);
|
||||
static DEVICE_ATTR_RW(bt_coex_state);
|
||||
|
||||
static ssize_t wl1271_sysfs_show_hw_pg_ver(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
static ssize_t hw_pg_ver_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct wl1271 *wl = dev_get_drvdata(dev);
|
||||
ssize_t len;
|
||||
@ -94,7 +92,7 @@ static ssize_t wl1271_sysfs_show_hw_pg_ver(struct device *dev,
|
||||
return len;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(hw_pg_ver, 0444, wl1271_sysfs_show_hw_pg_ver, NULL);
|
||||
static DEVICE_ATTR_RO(hw_pg_ver);
|
||||
|
||||
static ssize_t wl1271_sysfs_read_fwlog(struct file *filp, struct kobject *kobj,
|
||||
struct bin_attribute *bin_attr,
|
||||
|
@ -1544,14 +1544,14 @@ static int __init usb_init(void)
|
||||
|
||||
zd_workqueue = create_singlethread_workqueue(driver.name);
|
||||
if (zd_workqueue == NULL) {
|
||||
printk(KERN_ERR "%s couldn't create workqueue\n", driver.name);
|
||||
pr_err("%s couldn't create workqueue\n", driver.name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
r = usb_register(&driver);
|
||||
if (r) {
|
||||
destroy_workqueue(zd_workqueue);
|
||||
printk(KERN_ERR "%s usb_register() failed. Error number %d\n",
|
||||
pr_err("%s usb_register() failed. Error number %d\n",
|
||||
driver.name, r);
|
||||
return r;
|
||||
}
|
||||
|
@ -231,7 +231,8 @@ static int ssb_gpio_chipco_init(struct ssb_bus *bus)
|
||||
chip->ngpio = 16;
|
||||
/* There is just one SoC in one device and its GPIO addresses should be
|
||||
* deterministic to address them more easily. The other buses could get
|
||||
* a random base number. */
|
||||
* a random base number.
|
||||
*/
|
||||
if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
chip->base = 0;
|
||||
else
|
||||
@ -424,7 +425,8 @@ static int ssb_gpio_extif_init(struct ssb_bus *bus)
|
||||
chip->ngpio = 5;
|
||||
/* There is just one SoC in one device and its GPIO addresses should be
|
||||
* deterministic to address them more easily. The other buses could get
|
||||
* a random base number. */
|
||||
* a random base number.
|
||||
*/
|
||||
if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
chip->base = 0;
|
||||
else
|
||||
|
@ -55,7 +55,8 @@ void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
|
||||
#include <asm/paccess.h>
|
||||
/* Probe a 32bit value on the bus and catch bus exceptions.
|
||||
* Returns nonzero on a bus exception.
|
||||
* This is MIPS specific */
|
||||
* This is MIPS specific
|
||||
*/
|
||||
#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
|
||||
|
||||
/* Assume one-hot slot wiring */
|
||||
@ -255,7 +256,8 @@ static struct pci_controller ssb_pcicore_controller = {
|
||||
};
|
||||
|
||||
/* This function is called when doing a pci_enable_device().
|
||||
* We must first check if the device is a device on the PCI-core bridge. */
|
||||
* We must first check if the device is a device on the PCI-core bridge.
|
||||
*/
|
||||
int ssb_pcicore_plat_dev_init(struct pci_dev *d)
|
||||
{
|
||||
if (d->bus->ops != &ssb_pcicore_pciops) {
|
||||
@ -381,11 +383,13 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
|
||||
|
||||
/* Ok, ready to run, register it to the system.
|
||||
* The following needs change, if we want to port hostmode
|
||||
* to non-MIPS platform. */
|
||||
* to non-MIPS platform.
|
||||
*/
|
||||
ssb_pcicore_controller.io_map_base = (unsigned long)ioremap(SSB_PCI_MEM, 0x04000000);
|
||||
set_io_port_base(ssb_pcicore_controller.io_map_base);
|
||||
/* Give some time to the PCI controller to configure itself with the new
|
||||
* values. Not waiting at this point causes crashes of the machine. */
|
||||
* values. Not waiting at this point causes crashes of the machine.
|
||||
*/
|
||||
mdelay(10);
|
||||
register_pci_controller(&ssb_pcicore_controller);
|
||||
}
|
||||
@ -405,7 +409,8 @@ static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
|
||||
return 0;
|
||||
|
||||
/* The 200-pin BCM4712 package does not bond out PCI. Even when
|
||||
* PCI is bonded out, some boards may leave the pins floating. */
|
||||
* PCI is bonded out, some boards may leave the pins floating.
|
||||
*/
|
||||
if (bus->chip_id == 0x4712) {
|
||||
if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
|
||||
return 0;
|
||||
@ -685,7 +690,8 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
|
||||
if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
|
||||
/* This SSB device is not on a PCI host-bus. So the IRQs are
|
||||
* not routed through the PCI core.
|
||||
* So we must not enable routing through the PCI core. */
|
||||
* So we must not enable routing through the PCI core.
|
||||
*/
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
@ -37,7 +37,8 @@ static LIST_HEAD(buses);
|
||||
/* Software ID counter */
|
||||
static unsigned int next_busnumber;
|
||||
/* buses_mutes locks the two buslists and the next_busnumber.
|
||||
* Don't lock this directly, but use ssb_buses_[un]lock() below. */
|
||||
* Don't lock this directly, but use ssb_buses_[un]lock() below.
|
||||
*/
|
||||
static DEFINE_MUTEX(buses_mutex);
|
||||
|
||||
/* There are differences in the codeflow, if the bus is
|
||||
@ -45,7 +46,8 @@ static DEFINE_MUTEX(buses_mutex);
|
||||
* are not available early. This is a mechanism to delay
|
||||
* these initializations to after early boot has finished.
|
||||
* It's also used to avoid mutex locking, as that's not
|
||||
* available and needed early. */
|
||||
* available and needed early.
|
||||
*/
|
||||
static bool ssb_is_early_boot = 1;
|
||||
|
||||
static void ssb_buses_lock(void);
|
||||
@ -161,7 +163,8 @@ int ssb_bus_resume(struct ssb_bus *bus)
|
||||
int err;
|
||||
|
||||
/* Reset HW state information in memory, so that HW is
|
||||
* completely reinitialized. */
|
||||
* completely reinitialized.
|
||||
*/
|
||||
bus->mapped_device = NULL;
|
||||
#ifdef CONFIG_SSB_DRIVER_PCICORE
|
||||
bus->pcicore.setup_done = 0;
|
||||
@ -431,9 +434,7 @@ void ssb_bus_unregister(struct ssb_bus *bus)
|
||||
int err;
|
||||
|
||||
err = ssb_gpio_unregister(bus);
|
||||
if (err == -EBUSY)
|
||||
pr_debug("Some GPIOs are still in use\n");
|
||||
else if (err)
|
||||
if (err)
|
||||
pr_debug("Can not unregister GPIO driver: %i\n", err);
|
||||
|
||||
ssb_buses_lock();
|
||||
@ -467,7 +468,8 @@ static int ssb_devices_register(struct ssb_bus *bus)
|
||||
sdev = &(bus->devices[i]);
|
||||
|
||||
/* We don't register SSB-system devices to the kernel,
|
||||
* as the drivers for them are built into SSB. */
|
||||
* as the drivers for them are built into SSB.
|
||||
*/
|
||||
switch (sdev->id.coreid) {
|
||||
case SSB_DEV_CHIPCOMMON:
|
||||
case SSB_DEV_PCI:
|
||||
@ -521,7 +523,8 @@ static int ssb_devices_register(struct ssb_bus *bus)
|
||||
if (err) {
|
||||
pr_err("Could not register %s\n", dev_name(dev));
|
||||
/* Set dev to NULL to not unregister
|
||||
* dev on error unwinding. */
|
||||
* dev on error unwinding.
|
||||
*/
|
||||
sdev->dev = NULL;
|
||||
put_device(dev);
|
||||
goto error;
|
||||
@ -667,7 +670,8 @@ ssb_bus_register(struct ssb_bus *bus,
|
||||
ssb_bus_may_powerdown(bus);
|
||||
|
||||
/* Queue it for attach.
|
||||
* See the comment at the ssb_is_early_boot definition. */
|
||||
* See the comment at the ssb_is_early_boot definition.
|
||||
*/
|
||||
list_add_tail(&bus->list, &attach_queue);
|
||||
if (!ssb_is_early_boot) {
|
||||
/* This is not early boot, so we must attach the bus now */
|
||||
@ -1007,7 +1011,8 @@ static void ssb_flush_tmslow(struct ssb_device *dev)
|
||||
* a machine check exception otherwise.
|
||||
* Do this by reading the register back to commit the
|
||||
* PCI write and delay an additional usec for the device
|
||||
* to react to the change. */
|
||||
* to react to the change.
|
||||
*/
|
||||
ssb_read32(dev, SSB_TMSLOW);
|
||||
udelay(1);
|
||||
}
|
||||
@ -1044,7 +1049,8 @@ void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
|
||||
EXPORT_SYMBOL(ssb_device_enable);
|
||||
|
||||
/* Wait for bitmask in a register to get set or cleared.
|
||||
* timeout is in units of ten-microseconds */
|
||||
* timeout is in units of ten-microseconds
|
||||
*/
|
||||
static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
|
||||
int timeout, int set)
|
||||
{
|
||||
@ -1153,7 +1159,8 @@ int ssb_bus_may_powerdown(struct ssb_bus *bus)
|
||||
|
||||
/* On buses where more than one core may be working
|
||||
* at a time, we must not powerdown stuff if there are
|
||||
* still cores that may want to run. */
|
||||
* still cores that may want to run.
|
||||
*/
|
||||
if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
goto out;
|
||||
|
||||
@ -1303,13 +1310,11 @@ static int __init ssb_modinit(void)
|
||||
if (err) {
|
||||
pr_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
|
||||
/* don't fail SSB init because of this */
|
||||
err = 0;
|
||||
}
|
||||
err = ssb_host_pcmcia_init();
|
||||
if (err) {
|
||||
pr_err("PCMCIA host initialization failed\n");
|
||||
/* don't fail SSB init because of this */
|
||||
err = 0;
|
||||
}
|
||||
err = ssb_gige_init();
|
||||
if (err) {
|
||||
@ -1322,7 +1327,8 @@ out:
|
||||
}
|
||||
/* ssb must be initialized after PCI but before the ssb drivers.
|
||||
* That means we must use some initcall between subsys_initcall
|
||||
* and device_initcall. */
|
||||
* and device_initcall.
|
||||
*/
|
||||
fs_initcall(ssb_modinit);
|
||||
|
||||
static void __exit ssb_modexit(void)
|
||||
|
@ -1117,9 +1117,9 @@ const struct ssb_bus_ops ssb_pci_ops = {
|
||||
#endif
|
||||
};
|
||||
|
||||
static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
static ssize_t ssb_sprom_show(struct device *pcidev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
|
||||
struct ssb_bus *bus;
|
||||
@ -1131,9 +1131,9 @@ static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
|
||||
return ssb_attr_sprom_show(bus, buf, sprom_do_read);
|
||||
}
|
||||
|
||||
static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t ssb_sprom_store(struct device *pcidev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
|
||||
struct ssb_bus *bus;
|
||||
@ -1146,9 +1146,7 @@ static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
|
||||
sprom_check_crc, sprom_do_write);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(ssb_sprom, 0600,
|
||||
ssb_pci_attr_sprom_show,
|
||||
ssb_pci_attr_sprom_store);
|
||||
static DEVICE_ATTR_ADMIN_RW(ssb_sprom);
|
||||
|
||||
void ssb_pci_exit(struct ssb_bus *bus)
|
||||
{
|
||||
|
@ -723,9 +723,9 @@ int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static ssize_t ssb_pcmcia_attr_sprom_show(struct device *pcmciadev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
static ssize_t ssb_sprom_show(struct device *pcmciadev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct pcmcia_device *pdev =
|
||||
container_of(pcmciadev, struct pcmcia_device, dev);
|
||||
@ -739,9 +739,9 @@ static ssize_t ssb_pcmcia_attr_sprom_show(struct device *pcmciadev,
|
||||
ssb_pcmcia_sprom_read_all);
|
||||
}
|
||||
|
||||
static ssize_t ssb_pcmcia_attr_sprom_store(struct device *pcmciadev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
static ssize_t ssb_sprom_store(struct device *pcmciadev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct pcmcia_device *pdev =
|
||||
container_of(pcmciadev, struct pcmcia_device, dev);
|
||||
@ -756,9 +756,7 @@ static ssize_t ssb_pcmcia_attr_sprom_store(struct device *pcmciadev,
|
||||
ssb_pcmcia_sprom_write_all);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(ssb_sprom, 0600,
|
||||
ssb_pcmcia_attr_sprom_show,
|
||||
ssb_pcmcia_attr_sprom_store);
|
||||
static DEVICE_ATTR_ADMIN_RW(ssb_sprom);
|
||||
|
||||
static int ssb_pcmcia_cor_setup(struct ssb_bus *bus, u8 cor)
|
||||
{
|
||||
|
@ -325,6 +325,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
|
||||
if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
|
||||
pr_err("More than %d ssb cores found (%d)\n",
|
||||
SSB_MAX_NR_CORES, bus->nr_devices);
|
||||
err = -EINVAL;
|
||||
goto err_unmap;
|
||||
}
|
||||
if (bus->bustype == SSB_BUSTYPE_SSB) {
|
||||
|
@ -411,7 +411,6 @@ static void ssb_sdio_block_write(struct ssb_device *dev, const void *buffer,
|
||||
sdio_claim_host(bus->host_sdio);
|
||||
if (unlikely(ssb_sdio_switch_core(bus, dev))) {
|
||||
error = -EIO;
|
||||
memset((void *)buffer, 0xff, count);
|
||||
goto err_out;
|
||||
}
|
||||
offset |= bus->sdio_sbaddr & 0xffff;
|
||||
|
Loading…
Reference in New Issue
Block a user