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drm/panfrost: Handle HW_ISSUE_TTRX_3076
Some Valhall GPUs require resets when encountering bus faults due to occlusion query writes. Add the issue bit for this and handle it. Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220525145754.25866-5-alyssa.rosenzweig@collabora.com
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@ -11,6 +11,7 @@
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#include "panfrost_device.h"
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#include "panfrost_device.h"
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#include "panfrost_devfreq.h"
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#include "panfrost_devfreq.h"
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#include "panfrost_features.h"
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#include "panfrost_features.h"
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#include "panfrost_issues.h"
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#include "panfrost_gpu.h"
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#include "panfrost_gpu.h"
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#include "panfrost_job.h"
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#include "panfrost_job.h"
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#include "panfrost_mmu.h"
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#include "panfrost_mmu.h"
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@ -380,9 +381,13 @@ const char *panfrost_exception_name(u32 exception_code)
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bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
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bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
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u32 exception_code)
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u32 exception_code)
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{
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{
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/* Right now, none of the GPU we support need a reset, but this
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/* If an occlusion query write causes a bus fault on affected GPUs,
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* might change.
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* future fragment jobs may hang. Reset to workaround.
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*/
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*/
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if (exception_code == DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT)
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return panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_3076);
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/* No other GPUs we support need a reset */
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return false;
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return false;
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}
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}
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@ -128,6 +128,10 @@ enum panfrost_hw_issue {
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/* Must set SC_VAR_ALGORITHM */
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/* Must set SC_VAR_ALGORITHM */
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HW_ISSUE_TTRX_2968_TTRX_3162,
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HW_ISSUE_TTRX_2968_TTRX_3162,
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/* Bus fault from occlusion query write may cause future fragment jobs
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* to hang */
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HW_ISSUE_TTRX_3076,
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HW_ISSUE_END
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HW_ISSUE_END
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};
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};
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