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Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon: Fix sparc regression in r300_scratch() drm: make sure vblank interrupts are disabled at DPMS time drm/radeon/kms/evergreen: No EnableYUV table drm/radeon: 9800 SE has only one quadpipe drm/radeon/kms: don't print error for legal crtcs. drm/radeon/kms/evergreen: fix LUT setup
This commit is contained in:
commit
0bfb82449c
@ -476,6 +476,7 @@ void drm_vblank_off(struct drm_device *dev, int crtc)
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unsigned long irqflags;
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unsigned long irqflags;
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spin_lock_irqsave(&dev->vbl_lock, irqflags);
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spin_lock_irqsave(&dev->vbl_lock, irqflags);
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dev->driver->disable_vblank(dev, crtc);
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DRM_WAKEUP(&dev->vbl_queue[crtc]);
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DRM_WAKEUP(&dev->vbl_queue[crtc]);
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dev->vblank_enabled[crtc] = 0;
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dev->vblank_enabled[crtc] = 0;
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dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc);
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dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc);
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@ -324,13 +324,12 @@ void r300_gpu_init(struct radeon_device *rdev)
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uint32_t gb_tile_config, tmp;
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uint32_t gb_tile_config, tmp;
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r100_hdp_reset(rdev);
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r100_hdp_reset(rdev);
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/* FIXME: rv380 one pipes ? */
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if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
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if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
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(rdev->family == CHIP_R350)) {
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(rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
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/* r300,r350 */
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/* r300,r350 */
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rdev->num_gb_pipes = 2;
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rdev->num_gb_pipes = 2;
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} else {
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} else {
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/* rv350,rv370,rv380,r300 AD */
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/* rv350,rv370,rv380,r300 AD, r350 AH */
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rdev->num_gb_pipes = 1;
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rdev->num_gb_pipes = 1;
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}
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}
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rdev->num_z_pipes = 1;
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rdev->num_z_pipes = 1;
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@ -921,7 +921,7 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
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ptr_addr = drm_buffer_read_object(cmdbuf->buffer,
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ptr_addr = drm_buffer_read_object(cmdbuf->buffer,
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sizeof(stack_ptr_addr), &stack_ptr_addr);
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sizeof(stack_ptr_addr), &stack_ptr_addr);
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ref_age_base = (u32 *)(unsigned long)*ptr_addr;
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ref_age_base = (u32 *)(unsigned long)get_unaligned(ptr_addr);
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for (i=0; i < header.scratch.n_bufs; i++) {
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for (i=0; i < header.scratch.n_bufs; i++) {
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buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
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buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
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@ -59,6 +59,12 @@ void r420_pipes_init(struct radeon_device *rdev)
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/* get max number of pipes */
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/* get max number of pipes */
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gb_pipe_select = RREG32(0x402C);
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gb_pipe_select = RREG32(0x402C);
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num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
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num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
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/* SE chips have 1 pipe */
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if ((rdev->pdev->device == 0x5e4c) ||
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(rdev->pdev->device == 0x5e4f))
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num_pipes = 1;
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rdev->num_gb_pipes = num_pipes;
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rdev->num_gb_pipes = num_pipes;
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tmp = 0;
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tmp = 0;
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switch (num_pipes) {
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switch (num_pipes) {
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@ -435,14 +435,19 @@ static void radeon_init_pipes(struct drm_device *dev)
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
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gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
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gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
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dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
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dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
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/* SE cards have 1 pipe */
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if ((dev->pdev->device == 0x5e4c) ||
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(dev->pdev->device == 0x5e4f))
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dev_priv->num_gb_pipes = 1;
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} else {
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} else {
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/* R3xx */
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/* R3xx */
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
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dev->pdev->device != 0x4144) ||
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dev->pdev->device != 0x4144) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
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dev->pdev->device != 0x4148)) {
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dev_priv->num_gb_pipes = 2;
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dev_priv->num_gb_pipes = 2;
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} else {
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} else {
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/* RV3xx/R300 AD */
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/* RV3xx/R300 AD/R350 AH */
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dev_priv->num_gb_pipes = 1;
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dev_priv->num_gb_pipes = 1;
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}
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}
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}
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}
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@ -86,12 +86,12 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id);
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WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);
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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
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WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0);
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WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
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for (i = 0; i < 256; i++) {
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for (i = 0; i < 256; i++) {
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WREG32(EVERGREEN_DC_LUT_30_COLOR,
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WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
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(radeon_crtc->lut_r[i] << 20) |
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(radeon_crtc->lut_r[i] << 20) |
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(radeon_crtc->lut_g[i] << 10) |
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(radeon_crtc->lut_g[i] << 10) |
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(radeon_crtc->lut_b[i] << 0));
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(radeon_crtc->lut_b[i] << 0));
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@ -1326,7 +1326,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
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radeon_encoder->pixel_clock = adjusted_mode->clock;
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radeon_encoder->pixel_clock = adjusted_mode->clock;
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if (ASIC_IS_AVIVO(rdev)) {
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if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
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if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
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if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
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atombios_yuv_setup(encoder, true);
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atombios_yuv_setup(encoder, true);
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else
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else
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@ -165,7 +165,7 @@ u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
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{
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{
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc > 1) {
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if (crtc < 0 || crtc >= rdev->num_crtc) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -177,7 +177,7 @@ int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
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{
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{
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc > 1) {
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if (crtc < 0 || crtc >= rdev->num_crtc) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -191,7 +191,7 @@ void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
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{
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{
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc > 1) {
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if (crtc < 0 || crtc >= rdev->num_crtc) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return;
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return;
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}
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}
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