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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (52 commits)
  Blackfin: encode cpu-rev into uImage name
  Blackfin: bf54x: don't ack GPIO ints when unmasking them
  Blackfin: sram_free_with_lsl: do not ignore return value of sram_free
  Blackfin: boards: add missing "static" to peripheral lists
  Blackfin: DNP5370: new board port
  Blackfin: bf518f-ezbrd: fix dsa resources
  Blackfin: move "-m elf32bfin" to general LDFLAGS
  Blackfin: kgdb_test: make sure to initialize num2
  Blackfin: kgdb: disable preempt schedule when running single step in kgdb
  Blackfin: kgdb: disable interrupt when single stepping in ADEOS
  Blackfin: SMP: kgdb: apply anomaly 257 work around
  Blackfin: fix building IPIPE code when XIP is enabled
  Blackfin: SMP: kgdb: flush core internal write buffer before flushinv
  Blackfin: sport_uart resources: remove unused secondary RX/TX pins
  Blackfin: tll6527m: fix spelling in unused code (struct name)
  Blackfin: bf527-ezkit: add adau1373 chip address
  Blackfin: no-mpu: fix masking of small uncached dma region
  Blackfin: pm: drop irq save/restore in standby and suspend to mem callback
  MAINTAINERS: update Analog Devices support info
  Blackfin: dpmc.h: pull in new pll.h
  ...
This commit is contained in:
Linus Torvalds 2011-01-10 17:06:08 -08:00
commit 0be8c8bd1d
157 changed files with 9975 additions and 11027 deletions
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82
MAINTAINERS
View File

@ -285,6 +285,41 @@ L: linux-parisc@vger.kernel.org
S: Maintained
F: sound/pci/ad1889.*
AD525X ANALOG DEVICES DIGITAL POTENTIOMETERS DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/AD5254
S: Supported
F: drivers/misc/ad525x_dpot.c
AD5398 CURRENT REGULATOR DRIVER (AD5398/AD5821)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/AD5398
S: Supported
F: drivers/regulator/ad5398.c
AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/AD7142
S: Supported
F: drivers/input/misc/ad714x.c
AD7877 TOUCHSCREEN DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/AD7877
S: Supported
F: drivers/input/touchscreen/ad7877.c
AD7879 TOUCHSCREEN DRIVER (AD7879/AD7889)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/AD7879
S: Supported
F: drivers/input/touchscreen/ad7879.c
ADM1025 HARDWARE MONITOR DRIVER
M: Jean Delvare <khali@linux-fr.org>
L: lm-sensors@lm-sensors.org
@ -304,6 +339,32 @@ W: http://linuxwireless.org/
S: Orphan
F: drivers/net/wireless/adm8211.*
ADP5520 BACKLIGHT DRIVER WITH IO EXPANDER (ADP5520/ADP5501)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/ADP5520
S: Supported
F: drivers/mfd/adp5520.c
F: drivers/video/backlight/adp5520_bl.c
F: drivers/led/leds-adp5520.c
F: drivers/gpio/adp5520-gpio.c
F: drivers/input/keyboard/adp5520-keys.c
ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/ADP5588
S: Supported
F: drivers/input/keyboard/adp5588-keys.c
F: drivers/gpio/adp5588-gpio.c
ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/ADP8860
S: Supported
F: drivers/video/backlight/adp8860_bl.c
ADT746X FAN DRIVER
M: Colin Leroy <colin@colino.net>
S: Maintained
@ -316,6 +377,13 @@ S: Maintained
F: Documentation/hwmon/adt7475
F: drivers/hwmon/adt7475.c
ADXL34X THREE-AXIS DIGITAL ACCELEROMETER DRIVER (ADXL345/ADXL346)
M: Michael Hennerich <michael.hennerich@analog.com>
L: device-driver-devel@blackfin.uclinux.org
W: http://wiki-analog.com/ADXL345
S: Supported
F: drivers/input/misc/adxl34x.c
ADVANSYS SCSI DRIVER
M: Matthew Wilcox <matthew@wil.cx>
L: linux-scsi@vger.kernel.org
@ -440,16 +508,22 @@ L: linux-rdma@vger.kernel.org
S: Maintained
F: drivers/infiniband/hw/amso1100/
ANALOG DEVICES INC ASOC CODEC DRIVERS
L: device-driver-devel@blackfin.uclinux.org
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
W: http://wiki-analog.com/
S: Supported
F: sound/soc/codecs/ad1*
F: sound/soc/codecs/adau*
F: sound/soc/codecs/adav*
F: sound/soc/codecs/ssm*
ANALOG DEVICES INC ASOC DRIVERS
L: uclinux-dist-devel@blackfin.uclinux.org
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
W: http://blackfin.uclinux.org/
S: Supported
F: sound/soc/blackfin/*
F: sound/soc/codecs/ad1*
F: sound/soc/codecs/adau*
F: sound/soc/codecs/adav*
F: sound/soc/codecs/ssm*
AOA (Apple Onboard Audio) ALSA DRIVER
M: Johannes Berg <johannes@sipsolutions.net>

9
arch/blackfin/Makefile
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@ -19,7 +19,7 @@ KBUILD_CFLAGS += -mlong-calls
endif
KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
KBUILD_CFLAGS_MODULE += -mlong-calls
KBUILD_LDFLAGS_MODULE += -m elf32bfin
LDFLAGS += -m elf32bfin
KALLSYMS += --symbol-prefix=_
KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@ -97,8 +97,11 @@ rev-$(CONFIG_BF_REV_0_6) := 0.6
rev-$(CONFIG_BF_REV_NONE) := none
rev-$(CONFIG_BF_REV_ANY) := any
KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y)
KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
CPU_REV := $(cpu-y)-$(rev-y)
export CPU_REV
KBUILD_CFLAGS += -mcpu=$(CPU_REV)
KBUILD_AFLAGS += -mcpu=$(CPU_REV)
# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')

2
arch/blackfin/boot/Makefile
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@ -17,7 +17,7 @@ UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' \
-C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
-e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
$(UIMAGE_OPTS-y) -d $< $@

113
arch/blackfin/configs/BF561-EZKIT-SMP_defconfig Normal file
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@ -0,0 +1,113 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EMBEDDED=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
# CONFIG_FUTEX is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BF561=y
CONFIG_SMP=y
CONFIG_IRQ_TIMER0=10
CONFIG_CLKIN_HZ=30000000
CONFIG_HIGH_RES_TIMERS=y
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
CONFIG_BFIN_GPTIMERS=m
CONFIG_C_CDPRIO=y
CONFIG_BANK_3=0xAAC2
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_IRDA=m
CONFIG_IRLAN=m
CONFIG_IRCOMM=m
CONFIG_IRDA_CACHE_LAST_LSAP=y
CONFIG_IRTTY_SIR=m
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
CONFIG_MTD_PHYSMAP=m
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SMC91X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
CONFIG_INPUT=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
CONFIG_BFIN_JTAG_COMM=m
CONFIG_SERIAL_BFIN=y
CONFIG_SERIAL_BFIN_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_BFIN=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_BFIN_WDT=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_JFFS2_FS=m
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
CONFIG_SMB_FS=m
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_MMRS=y
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_CRYPTO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

121
arch/blackfin/configs/DNP5370_defconfig Normal file
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@ -0,0 +1,121 @@
CONFIG_EXPERIMENTAL=y
CONFIG_LOCALVERSION="DNP5370"
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLOB=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_BF537=y
CONFIG_BF_REV_0_3=y
CONFIG_DNP5370=y
CONFIG_IRQ_ERROR=7
# CONFIG_CYCLES_CLOCKSOURCE is not set
CONFIG_C_CDPRIO=y
CONFIG_C_AMBEN_B0_B1_B2=y
CONFIG_PM=y
# CONFIG_SUSPEND is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_RARP=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_LLC2=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_DEBUG_VERBOSE=1
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_NFTL=y
CONFIG_NFTL_RW=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y
CONFIG_MTD_ABSENT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_UCLINUX=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_DAVICOM_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_BFIN_MAC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_BFIN_DMA_INTERFACE is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
CONFIG_BFIN_JTAG_COMM=y
CONFIG_BFIN_JTAG_COMM_CONSOLE=y
CONFIG_SERIAL_BFIN=y
CONFIG_SERIAL_BFIN_CONSOLE=y
CONFIG_SERIAL_BFIN_UART0=y
CONFIG_LEGACY_PTY_COUNT=64
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_SPI=y
CONFIG_SPI_BFIN=y
CONFIG_SPI_SPIDEV=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_LM75=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_DMADEVICES=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=850
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BOTH=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_LIST=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_PAGE_POISONING=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_CPLB_INFO=y
CONFIG_CRC_CCITT=y

91
arch/blackfin/include/asm/bfin_dma.h Normal file
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@ -0,0 +1,91 @@
/*
* bfin_dma.h - Blackfin DMA defines/structures/etc...
*
* Copyright 2004-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __ASM_BFIN_DMA_H__
#define __ASM_BFIN_DMA_H__
#include <linux/types.h>
/* DMA_CONFIG Masks */
#define DMAEN 0x0001 /* DMA Channel Enable */
#define WNR 0x0002 /* Channel Direction (W/R*) */
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
#define RESTART 0x0020 /* DMA Buffer Clear */
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
#define DI_EN 0x0080 /* Data Interrupt Enable */
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
#define NDSIZE 0x0f00 /* Next Descriptor Size */
#define DMAFLOW 0x7000 /* Flow Control */
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
/* DMA_IRQ_STATUS Masks */
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
/*
* bfin dma registers layout
*/
struct bfin_dma_regs {
u32 next_desc_ptr;
u32 start_addr;
__BFP(config);
u32 __pad0;
__BFP(x_count);
__BFP(x_modify);
__BFP(y_count);
__BFP(y_modify);
u32 curr_desc_ptr;
u32 curr_addr;
__BFP(irq_status);
__BFP(peripheral_map);
__BFP(curr_x_count);
u32 __pad1;
__BFP(curr_y_count);
u32 __pad2;
};
/*
* bfin handshake mdma registers layout
*/
struct bfin_hmdma_regs {
__BFP(control);
__BFP(ecinit);
__BFP(bcinit);
__BFP(ecurgent);
__BFP(ecoverflow);
__BFP(ecount);
__BFP(bcount);
};
#undef __BFP
#endif

275
arch/blackfin/include/asm/bfin_serial.h Normal file
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@ -0,0 +1,275 @@
/*
* bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_ASM_SERIAL_H__
#define __BFIN_ASM_SERIAL_H__
#include <linux/serial_core.h>
#include <mach/anomaly.h>
#include <mach/bfin_serial.h>
#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
defined(CONFIG_BFIN_UART1_CTSRTS) || \
defined(CONFIG_BFIN_UART2_CTSRTS) || \
defined(CONFIG_BFIN_UART3_CTSRTS)
# ifdef BFIN_UART_BF54X_STYLE
# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
# else
# define CONFIG_SERIAL_BFIN_CTSRTS
# endif
#endif
struct circ_buf;
struct timer_list;
struct work_struct;
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
int status_irq;
#ifndef BFIN_UART_BF54X_STYLE
unsigned int lsr;
#endif
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#elif ANOMALY_05000363
unsigned int anomaly_threshold;
#endif
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
int scts;
#endif
#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
int cts_pin;
int rts_pin;
#endif
};
/* UART_LCR Masks */
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
#define STP 0x20 /* Stick Parity */
#define SB 0x40 /* Set Break */
#define DLAB 0x80 /* Divisor Latch Access */
/* UART_LSR Masks */
#define DR 0x01 /* Data Ready */
#define OE 0x02 /* Overrun Error */
#define PE 0x04 /* Parity Error */
#define FE 0x08 /* Framing Error */
#define BI 0x10 /* Break Interrupt */
#define THRE 0x20 /* THR Empty */
#define TEMT 0x40 /* TSR and UART_THR Empty */
#define TFI 0x80 /* Transmission Finished Indicator */
/* UART_IER Masks */
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
#define ELSI 0x04 /* Enable RX Status Interrupt */
#define EDSSI 0x08 /* Enable Modem Status Interrupt */
#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
/* UART_MCR Masks */
#define XOFF 0x01 /* Transmitter Off */
#define MRTS 0x02 /* Manual Request To Send */
#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
#define RFRT 0x08 /* Receive FIFO RTS Threshold */
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
#define FCPOL 0x20 /* Flow Control Pin Polarity */
#define ARTS 0x40 /* Automatic Request To Send */
#define ACTS 0x80 /* Automatic Clear To Send */
/* UART_MSR Masks */
#define SCTS 0x01 /* Sticky CTS */
#define CTS 0x10 /* Clear To Send */
#define RFCS 0x20 /* Receive FIFO Count Status */
/* UART_GCTL Masks */
#define UCEN 0x01 /* Enable UARTx Clocks */
#define IREN 0x02 /* Enable IrDA Mode */
#define TPOLC 0x04 /* IrDA TX Polarity Change */
#define RPOLC 0x08 /* IrDA RX Polarity Change */
#define FPE 0x10 /* Force Parity Error On Transmit */
#define FFE 0x20 /* Force Framing Error On Transmit */
#ifdef BFIN_UART_BF54X_STYLE
# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
# define OFFSET_GCTL 0x08 /* Global Control Register */
# define OFFSET_LCR 0x0C /* Line Control Register */
# define OFFSET_MCR 0x10 /* Modem Control Register */
# define OFFSET_LSR 0x14 /* Line Status Register */
# define OFFSET_MSR 0x18 /* Modem Status Register */
# define OFFSET_SCR 0x1C /* SCR Scratch Register */
# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
# define OFFSET_THR 0x28 /* Transmit Holding register */
# define OFFSET_RBR 0x2C /* Receive Buffer register */
#else /* BF533 style */
# define OFFSET_THR 0x00 /* Transmit Holding register */
# define OFFSET_RBR 0x00 /* Receive Buffer register */
# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
# define OFFSET_IER 0x04 /* Interrupt Enable Register */
# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
# define OFFSET_LCR 0x0C /* Line Control Register */
# define OFFSET_MCR 0x10 /* Modem Control Register */
# define OFFSET_LSR 0x14 /* Line Status Register */
# define OFFSET_MSR 0x18 /* Modem Status Register */
# define OFFSET_SCR 0x1C /* SCR Scratch Register */
# define OFFSET_GCTL 0x24 /* Global Control Register */
/* code should not need IIR, so force build error if they use it */
# undef OFFSET_IIR
#endif
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
struct bfin_uart_regs {
#ifdef BFIN_UART_BF54X_STYLE
__BFP(dll);
__BFP(dlh);
__BFP(gctl);
__BFP(lcr);
__BFP(mcr);
__BFP(lsr);
__BFP(msr);
__BFP(scr);
__BFP(ier_set);
__BFP(ier_clear);
__BFP(thr);
__BFP(rbr);
#else
union {
u16 dll;
u16 thr;
const u16 rbr;
};
const u16 __pad0;
union {
u16 dlh;
u16 ier;
};
const u16 __pad1;
const __BFP(iir);
__BFP(lcr);
__BFP(mcr);
__BFP(lsr);
__BFP(msr);
__BFP(scr);
const u32 __pad2;
__BFP(gctl);
#endif
};
#undef __BFP
#ifndef port_membase
# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
#endif
#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
#ifdef BFIN_UART_BF54X_STYLE
#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
/* This handles hard CTS/RTS */
#define BFIN_UART_CTSRTS_HARD
#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
#else /* BF533 style */
#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
#ifndef put_lsr_cache
# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
#endif
#ifndef get_lsr_cache
# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr)
#endif
/* The hardware clears the LSR bits upon read, so we need to cache
* some of the more fun bits in software so they don't get lost
* when checking the LSR in other code paths (TX).
*/
static inline void UART_CLEAR_LSR(void *p)
{
put_lsr_cache(p, 0);
bfin_write16(port_membase(p) + OFFSET_LSR, -1);
}
static inline unsigned int UART_GET_LSR(void *p)
{
unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
return lsr | get_lsr_cache(p);
}
static inline void UART_PUT_LSR(void *p, uint16_t val)
{
put_lsr_cache(p, get_lsr_cache(p) & ~val);
}
/* This handles soft CTS/RTS */
#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#endif
#ifndef BFIN_UART_TX_FIFO_SIZE
# define BFIN_UART_TX_FIFO_SIZE 2
#endif
#endif /* __BFIN_ASM_SERIAL_H__ */

2
arch/blackfin/include/asm/bitops.h
View File

@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
#define test_bit __skip_test_bit
#include <asm-generic/bitops/non-atomic.h>
#undef test_bit
#endif /* CONFIG_SMP */

2
arch/blackfin/include/asm/cache.h
View File

@ -7,6 +7,8 @@
#ifndef __ARCH_BLACKFIN_CACHE_H
#define __ARCH_BLACKFIN_CACHE_H
#include <linux/linkage.h> /* for asmlinkage */
/*
* Bytes per L1 cache line
* Blackfin loads 32 bytes for cache

3
arch/blackfin/include/asm/cacheflush.h
View File

@ -11,6 +11,9 @@
#include <asm/blackfin.h> /* for SSYNC() */
#include <asm/sections.h> /* for _ramend */
#ifdef CONFIG_SMP
#include <asm/smp.h>
#endif
extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);

37
arch/blackfin/include/asm/dma.h
View File

@ -14,40 +14,7 @@
#include <asm/blackfin.h>
#include <asm/page.h>
#include <asm-generic/dma.h>
/* DMA_CONFIG Masks */
#define DMAEN 0x0001 /* DMA Channel Enable */
#define WNR 0x0002 /* Channel Direction (W/R*) */
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
#define RESTART 0x0020 /* DMA Buffer Clear */
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
#define DI_EN 0x0080 /* Data Interrupt Enable */
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
#define NDSIZE 0x0f00 /* Next Descriptor Size */
#define DMAFLOW 0x7000 /* Flow Control */
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
/* DMA_IRQ_STATUS Masks */
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
#include <asm/bfin_dma.h>
/*-------------------------
* config reg bits value
@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
* DMA API's
*******************************************************************************/
extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
extern int channel2irq(unsigned int channel);
static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)

2
arch/blackfin/include/asm/dpmc.h
View File

@ -9,6 +9,8 @@
#ifndef _BLACKFIN_DPMC_H_
#define _BLACKFIN_DPMC_H_
#include <mach/pll.h>
/* PLL_CTL Masks */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* PLL Not Powered */

266
arch/blackfin/include/asm/io.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@ -7,148 +7,48 @@
#ifndef _BFIN_IO_H
#define _BFIN_IO_H
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#include <linux/types.h>
#endif
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/byteorder.h>
/*
* These are for ISA/PCI shared memory _only_ and should never be used
* on any other type of memory, including Zorro memory. They are meant to
* access the bus in the bus byte order which is little-endian!.
*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the bfin architecture, we just read/write the
* memory location directly.
*/
#ifndef __ASSEMBLY__
static inline unsigned char readb(const volatile void __iomem *addr)
{
unsigned int val;
int tmp;
__asm__ __volatile__ (
"cli %1;"
"NOP; NOP; SSYNC;"
"%0 = b [%2] (z);"
"sti %1;"
: "=d"(val), "=d"(tmp)
: "a"(addr)
);
return (unsigned char) val;
#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
static inline type __raw_read##size(const volatile void __iomem *addr) \
{ \
unsigned int val; \
int tmp; \
__asm__ __volatile__ ( \
"cli %1;" \
"NOP; NOP; SSYNC;" \
"%0 = "#asm" [%2] "#asm_sign";" \
"sti %1;" \
: "=d"(val), "=d"(tmp) \
: "a"(addr) \
); \
return (type) val; \
}
static inline unsigned short readw(const volatile void __iomem *addr)
{
unsigned int val;
int tmp;
__asm__ __volatile__ (
"cli %1;"
"NOP; NOP; SSYNC;"
"%0 = w [%2] (z);"
"sti %1;"
: "=d"(val), "=d"(tmp)
: "a"(addr)
);
return (unsigned short) val;
}
static inline unsigned int readl(const volatile void __iomem *addr)
{
unsigned int val;
int tmp;
__asm__ __volatile__ (
"cli %1;"
"NOP; NOP; SSYNC;"
"%0 = [%2];"
"sti %1;"
: "=d"(val), "=d"(tmp)
: "a"(addr)
);
return val;
}
#endif /* __ASSEMBLY__ */
#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
#define __io(port) ((void *)(unsigned long)(port))
#define inb(port) readb(__io(port))
#define inw(port) readw(__io(port))
#define inl(port) readl(__io(port))
#define outb(x, port) writeb(x, __io(port))
#define outw(x, port) writew(x, __io(port))
#define outl(x, port) writel(x, __io(port))
#define inb_p(port) inb(__io(port))
#define inw_p(port) inw(__io(port))
#define inl_p(port) inl(__io(port))
#define outb_p(x, port) outb(x, __io(port))
#define outw_p(x, port) outw(x, __io(port))
#define outl_p(x, port) outl(x, __io(port))
#define ioread8_rep(a, d, c) readsb(a, d, c)
#define ioread16_rep(a, d, c) readsw(a, d, c)
#define ioread32_rep(a, d, c) readsl(a, d, c)
#define iowrite8_rep(a, s, c) writesb(a, s, c)
#define iowrite16_rep(a, s, c) writesw(a, s, c)
#define iowrite32_rep(a, s, c) writesl(a, s, c)
#define ioread8(x) readb(x)
#define ioread16(x) readw(x)
#define ioread32(x) readl(x)
#define iowrite8(val, x) writeb(val, x)
#define iowrite16(val, x) writew(val, x)
#define iowrite32(val, x) writel(val, x)
/**
* I/O write barrier
*
* Ensure ordering of I/O space writes. This will make sure that writes
* following the barrier will arrive after all previous writes.
*/
#define mmiowb() do { SSYNC(); wmb(); } while (0)
#define IO_SPACE_LIMIT 0xffffffff
/* Values for nocacheflag and cmode */
#define IOMAP_NOCACHE_SER 1
#ifndef __ASSEMBLY__
DECLARE_BFIN_RAW_READX(b, u8, b, (z))
#define __raw_readb __raw_readb
DECLARE_BFIN_RAW_READX(w, u16, w, (z))
#define __raw_readw __raw_readw
DECLARE_BFIN_RAW_READX(l, u32, , )
#define __raw_readl __raw_readl
extern void outsb(unsigned long port, const void *addr, unsigned long count);
extern void outsw(unsigned long port, const void *addr, unsigned long count);
extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
extern void outsl(unsigned long port, const void *addr, unsigned long count);
#define outsb outsb
#define outsw outsw
#define outsl outsl
extern void insb(unsigned long port, void *addr, unsigned long count);
extern void insw(unsigned long port, void *addr, unsigned long count);
extern void insw_8(unsigned long port, void *addr, unsigned long count);
extern void insl(unsigned long port, void *addr, unsigned long count);
extern void insl_16(unsigned long port, void *addr, unsigned long count);
#define insb insb
#define insw insw
#define insl insl
extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
extern void dma_insw(unsigned long port, void *addr, unsigned short count);
extern void dma_insl(unsigned long port, void *addr, unsigned short count);
static inline void readsl(const void __iomem *addr, void *buf, int len)
{
insl((unsigned long)addr, buf, len);
}
static inline void readsw(const void __iomem *addr, void *buf, int len)
{
insw((unsigned long)addr, buf, len);
}
static inline void readsb(const void __iomem *addr, void *buf, int len)
{
insb((unsigned long)addr, buf, len);
}
static inline void writesl(const void __iomem *addr, const void *buf, int len)
{
outsl((unsigned long)addr, buf, len);
}
static inline void writesw(const void __iomem *addr, const void *buf, int len)
{
outsw((unsigned long)addr, buf, len);
}
static inline void writesb(const void __iomem *addr, const void *buf, int len)
{
outsb((unsigned long)addr, buf, len);
}
/*
* Map some physical address range into the kernel address space.
/**
* I/O write barrier
*
* Ensure ordering of I/O space writes. This will make sure that writes
* following the barrier will arrive after all previous writes.
*/
static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
int cacheflag)
{
return (void __iomem *)physaddr;
}
#define mmiowb() do { SSYNC(); wmb(); } while (0)
/*
* Unmap a ioremap()ed region again
*/
static inline void iounmap(void *addr)
{
}
/*
* __iounmap unmaps nearly everything, so be careful
* it doesn't free currently pointer/page tables anymore but it
* wans't used anyway and might be added later.
*/
static inline void __iounmap(void *addr, unsigned long size)
{
}
/*
* Set new cache mode for some kernel address space.
* The caller must push data for that range itself, if such data may already
* be in the cache.
*/
static inline void kernel_set_cachemode(void *addr, unsigned long size,
int cmode)
{
}
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_nocache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern void blkfin_inv_cache_all(void);
#include <asm-generic/io.h>
#endif
#define ioport_map(port, nr) ((void __iomem*)(port))
#define ioport_unmap(addr)
/* Pages to physical address... */
#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
#define phys_to_virt(vaddr) ((void *) (vaddr))
#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#endif /* __KERNEL__ */
#endif /* _BFIN_IO_H */

3
arch/blackfin/include/asm/irqflags.h
View File

@ -13,9 +13,6 @@
#ifdef CONFIG_SMP
# include <asm/pda.h>
# include <asm/processor.h>
/* Forward decl needed due to cdef inter dependencies */
static inline uint32_t __pure bfin_dspid(void);
# define blackfin_core_id() (bfin_dspid() & 0xff)
# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
#else
extern unsigned long bfin_irq_flags;

4
arch/blackfin/include/asm/processor.h
View File

@ -14,7 +14,7 @@
#define current_text_addr() ({ __label__ _l; _l: &&_l;})
#include <asm/ptrace.h>
#include <asm/blackfin.h>
#include <mach/blackfin.h>
static inline unsigned long rdusp(void)
{
@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
return bfin_read_DSPID();
}
#define blackfin_core_id() (bfin_dspid() & 0xff)
static inline uint32_t __pure bfin_compiled_revid(void)
{
#if defined(CONFIG_BF_REV_0_0)

28
arch/blackfin/include/asm/spinlock.h
View File

@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
asmlinkage void arch_read_lock_asm(volatile int *ptr);
asmlinkage int arch_read_trylock_asm(volatile int *ptr);
asmlinkage void arch_read_unlock_asm(volatile int *ptr);
asmlinkage void arch_write_lock_asm(volatile int *ptr);
asmlinkage int arch_write_trylock_asm(volatile int *ptr);
asmlinkage void arch_write_unlock_asm(volatile int *ptr);
asmlinkage void __raw_read_lock_asm(volatile int *ptr);
asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
asmlinkage void __raw_write_lock_asm(volatile int *ptr);
asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
static inline void arch_read_lock(arch_rwlock_t *rw)
{
arch_read_lock_asm(&rw->lock);
__raw_read_lock_asm(&rw->lock);
}
#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
static inline int arch_read_trylock(arch_rwlock_t *rw)
{
return arch_read_trylock_asm(&rw->lock);
return __raw_read_trylock_asm(&rw->lock);
}
static inline void arch_read_unlock(arch_rwlock_t *rw)
{
arch_read_unlock_asm(&rw->lock);
__raw_read_unlock_asm(&rw->lock);
}
static inline void arch_write_lock(arch_rwlock_t *rw)
{
arch_write_lock_asm(&rw->lock);
__raw_write_lock_asm(&rw->lock);
}
#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
static inline int arch_write_trylock(arch_rwlock_t *rw)
{
return arch_write_trylock_asm(&rw->lock);
return __raw_write_trylock_asm(&rw->lock);
}
static inline void arch_write_unlock(arch_rwlock_t *rw)
{
arch_write_unlock_asm(&rw->lock);
__raw_write_unlock_asm(&rw->lock);
}
#define arch_spin_relax(lock) cpu_relax()

86
arch/blackfin/include/mach-common/pll.h Normal file
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@ -0,0 +1,86 @@
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_COMMON_PLL_H
#define _MACH_COMMON_PLL_H
#ifndef __ASSEMBLY__
#include <asm/blackfin.h>
#include <asm/irqflags.h>
#ifndef bfin_iwr_restore
static inline void
bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
{
#ifdef SIC_IWR
bfin_write_SIC_IWR(iwr0);
#else
bfin_write_SIC_IWR0(iwr0);
# ifdef SIC_IWR1
bfin_write_SIC_IWR1(iwr1);
# endif
# ifdef SIC_IWR2
bfin_write_SIC_IWR2(iwr2);
# endif
#endif
}
#endif
#ifndef bfin_iwr_save
static inline void
bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
{
#ifdef SIC_IWR
*iwr0 = bfin_read_SIC_IWR();
#else
*iwr0 = bfin_read_SIC_IWR0();
# ifdef SIC_IWR1
*iwr1 = bfin_read_SIC_IWR1();
# endif
# ifdef SIC_IWR2
*iwr2 = bfin_read_SIC_IWR2();
# endif
#endif
bfin_iwr_restore(niwr0, niwr1, niwr2);
}
#endif
static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
bfin_write16(addr, val);
SSYNC();
asm("IDLE;");
bfin_iwr_restore(iwr0, iwr1, iwr2);
hard_local_irq_restore(flags);
}
/* Writing to PLL_CTL initiates a PLL relock sequence */
static inline void bfin_write_PLL_CTL(unsigned int val)
{
_bfin_write_pll_relock(PLL_CTL, val);
}
/* Writing to VR_CTL initiates a PLL relock sequence */
static inline void bfin_write_VR_CTL(unsigned int val)
{
_bfin_write_pll_relock(VR_CTL, val);
}
#endif
#endif

25
arch/blackfin/include/mach-common/ports-a.h Normal file
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@ -0,0 +1,25 @@
/*
* Port A Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_A__
#define __BFIN_PERIPHERAL_PORT_A__
#define PA0 (1 << 0)
#define PA1 (1 << 1)
#define PA2 (1 << 2)
#define PA3 (1 << 3)
#define PA4 (1 << 4)
#define PA5 (1 << 5)
#define PA6 (1 << 6)
#define PA7 (1 << 7)
#define PA8 (1 << 8)
#define PA9 (1 << 9)
#define PA10 (1 << 10)
#define PA11 (1 << 11)
#define PA12 (1 << 12)
#define PA13 (1 << 13)
#define PA14 (1 << 14)
#define PA15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-b.h Normal file
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@ -0,0 +1,25 @@
/*
* Port B Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_B__
#define __BFIN_PERIPHERAL_PORT_B__
#define PB0 (1 << 0)
#define PB1 (1 << 1)
#define PB2 (1 << 2)
#define PB3 (1 << 3)
#define PB4 (1 << 4)
#define PB5 (1 << 5)
#define PB6 (1 << 6)
#define PB7 (1 << 7)
#define PB8 (1 << 8)
#define PB9 (1 << 9)
#define PB10 (1 << 10)
#define PB11 (1 << 11)
#define PB12 (1 << 12)
#define PB13 (1 << 13)
#define PB14 (1 << 14)
#define PB15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-c.h Normal file
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@ -0,0 +1,25 @@
/*
* Port C Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_C__
#define __BFIN_PERIPHERAL_PORT_C__
#define PC0 (1 << 0)
#define PC1 (1 << 1)
#define PC2 (1 << 2)
#define PC3 (1 << 3)
#define PC4 (1 << 4)
#define PC5 (1 << 5)
#define PC6 (1 << 6)
#define PC7 (1 << 7)
#define PC8 (1 << 8)
#define PC9 (1 << 9)
#define PC10 (1 << 10)
#define PC11 (1 << 11)
#define PC12 (1 << 12)
#define PC13 (1 << 13)
#define PC14 (1 << 14)
#define PC15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-d.h Normal file
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@ -0,0 +1,25 @@
/*
* Port D Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_D__
#define __BFIN_PERIPHERAL_PORT_D__
#define PD0 (1 << 0)
#define PD1 (1 << 1)
#define PD2 (1 << 2)
#define PD3 (1 << 3)
#define PD4 (1 << 4)
#define PD5 (1 << 5)
#define PD6 (1 << 6)
#define PD7 (1 << 7)
#define PD8 (1 << 8)
#define PD9 (1 << 9)
#define PD10 (1 << 10)
#define PD11 (1 << 11)
#define PD12 (1 << 12)
#define PD13 (1 << 13)
#define PD14 (1 << 14)
#define PD15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-e.h Normal file
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@ -0,0 +1,25 @@
/*
* Port E Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_E__
#define __BFIN_PERIPHERAL_PORT_E__
#define PE0 (1 << 0)
#define PE1 (1 << 1)
#define PE2 (1 << 2)
#define PE3 (1 << 3)
#define PE4 (1 << 4)
#define PE5 (1 << 5)
#define PE6 (1 << 6)
#define PE7 (1 << 7)
#define PE8 (1 << 8)
#define PE9 (1 << 9)
#define PE10 (1 << 10)
#define PE11 (1 << 11)
#define PE12 (1 << 12)
#define PE13 (1 << 13)
#define PE14 (1 << 14)
#define PE15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-f.h Normal file
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@ -0,0 +1,25 @@
/*
* Port F Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_F__
#define __BFIN_PERIPHERAL_PORT_F__
#define PF0 (1 << 0)
#define PF1 (1 << 1)
#define PF2 (1 << 2)
#define PF3 (1 << 3)
#define PF4 (1 << 4)
#define PF5 (1 << 5)
#define PF6 (1 << 6)
#define PF7 (1 << 7)
#define PF8 (1 << 8)
#define PF9 (1 << 9)
#define PF10 (1 << 10)
#define PF11 (1 << 11)
#define PF12 (1 << 12)
#define PF13 (1 << 13)
#define PF14 (1 << 14)
#define PF15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-g.h Normal file
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@ -0,0 +1,25 @@
/*
* Port G Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_G__
#define __BFIN_PERIPHERAL_PORT_G__
#define PG0 (1 << 0)
#define PG1 (1 << 1)
#define PG2 (1 << 2)
#define PG3 (1 << 3)
#define PG4 (1 << 4)
#define PG5 (1 << 5)
#define PG6 (1 << 6)
#define PG7 (1 << 7)
#define PG8 (1 << 8)
#define PG9 (1 << 9)
#define PG10 (1 << 10)
#define PG11 (1 << 11)
#define PG12 (1 << 12)
#define PG13 (1 << 13)
#define PG14 (1 << 14)
#define PG15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-h.h Normal file
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@ -0,0 +1,25 @@
/*
* Port H Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_H__
#define __BFIN_PERIPHERAL_PORT_H__
#define PH0 (1 << 0)
#define PH1 (1 << 1)
#define PH2 (1 << 2)
#define PH3 (1 << 3)
#define PH4 (1 << 4)
#define PH5 (1 << 5)
#define PH6 (1 << 6)
#define PH7 (1 << 7)
#define PH8 (1 << 8)
#define PH9 (1 << 9)
#define PH10 (1 << 10)
#define PH11 (1 << 11)
#define PH12 (1 << 12)
#define PH13 (1 << 13)
#define PH14 (1 << 14)
#define PH15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-i.h Normal file
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@ -0,0 +1,25 @@
/*
* Port I Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_I__
#define __BFIN_PERIPHERAL_PORT_I__
#define PI0 (1 << 0)
#define PI1 (1 << 1)
#define PI2 (1 << 2)
#define PI3 (1 << 3)
#define PI4 (1 << 4)
#define PI5 (1 << 5)
#define PI6 (1 << 6)
#define PI7 (1 << 7)
#define PI8 (1 << 8)
#define PI9 (1 << 9)
#define PI10 (1 << 10)
#define PI11 (1 << 11)
#define PI12 (1 << 12)
#define PI13 (1 << 13)
#define PI14 (1 << 14)
#define PI15 (1 << 15)
#endif

25
arch/blackfin/include/mach-common/ports-j.h Normal file
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@ -0,0 +1,25 @@
/*
* Port J Masks
*/
#ifndef __BFIN_PERIPHERAL_PORT_J__
#define __BFIN_PERIPHERAL_PORT_J__
#define PJ0 (1 << 0)
#define PJ1 (1 << 1)
#define PJ2 (1 << 2)
#define PJ3 (1 << 3)
#define PJ4 (1 << 4)
#define PJ5 (1 << 5)
#define PJ6 (1 << 6)
#define PJ7 (1 << 7)
#define PJ8 (1 << 8)
#define PJ9 (1 << 9)
#define PJ10 (1 << 10)
#define PJ11 (1 << 11)
#define PJ12 (1 << 12)
#define PJ13 (1 << 13)
#define PJ14 (1 << 14)
#define PJ15 (1 << 15)
#endif

2
arch/blackfin/kernel/cplb-nompu/cplbinit.c
View File

@ -116,7 +116,7 @@ void __init generate_cplb_tables_all(void)
((_ramend - uncached_end) >= 1 * 1024 * 1024))
dcplb_bounds[i_d].eaddr = uncached_end;
else
dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
/* DMA uncached region. */
if (DMA_UNCACHED_REGION) {

26
arch/blackfin/kernel/kgdb.c
View File

@ -345,6 +345,23 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
}
#endif
#ifdef CONFIG_IPIPE
static unsigned long kgdb_arch_imask;
#endif
void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code)
{
if (kgdb_single_step)
preempt_enable();
#ifdef CONFIG_IPIPE
if (kgdb_arch_imask) {
cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask;
kgdb_arch_imask = 0;
}
#endif
}
int kgdb_arch_handle_exception(int vector, int signo,
int err_code, char *remcom_in_buffer,
char *remcom_out_buffer,
@ -388,6 +405,12 @@ int kgdb_arch_handle_exception(int vector, int signo,
* kgdb_single_step > 0 means in single step mode
*/
kgdb_single_step = i + 1;
preempt_disable();
#ifdef CONFIG_IPIPE
kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
cpu_pda[raw_smp_processor_id()].ex_imask = 0;
#endif
}
bfin_correct_hw_break();
@ -448,6 +471,9 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
int kgdb_arch_init(void)
{
kgdb_single_step = 0;
#ifdef CONFIG_IPIPE
kgdb_arch_imask = 0;
#endif
bfin_remove_all_hw_break();
return 0;

4
arch/blackfin/kernel/kgdb_test.c
View File

@ -95,6 +95,10 @@ static int __init kgdbtest_init(void)
{
struct proc_dir_entry *entry;
#if L2_LENGTH
num2 = 0;
#endif
entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
if (entry == NULL)
return -ENOMEM;

29
arch/blackfin/mach-bf518/boards/ezbrd.c
View File

@ -104,24 +104,23 @@ static const unsigned short bfin_mac_peripherals[] = {
static struct bfin_phydev_platform_data bfin_phydev_data[] = {
{
.addr = 1,
.irq = IRQ_MAC_PHYINT,
},
{
.addr = 2,
.irq = IRQ_MAC_PHYINT,
},
{
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
.addr = 3,
#else
.addr = 1,
#endif
.irq = IRQ_MAC_PHYINT,
},
};
static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
.phydev_number = 3,
.phydev_number = 1,
.phydev_data = bfin_phydev_data,
.phy_mode = PHY_INTERFACE_MODE_MII,
.mac_peripherals = bfin_mac_peripherals,
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
.phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
#endif
};
static struct platform_device bfin_mii_bus = {
@ -453,7 +452,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -496,7 +495,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -636,9 +635,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -670,9 +669,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

12
arch/blackfin/mach-bf518/boards/tcm-bf518.c
View File

@ -377,7 +377,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -420,7 +420,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -547,9 +547,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -581,9 +581,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

2
arch/blackfin/mach-bf518/dma.c
View File

@ -11,7 +11,7 @@
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,

14
arch/blackfin/mach-bf518/include/mach/bfin_serial.h Normal file
View File

@ -0,0 +1,14 @@
/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 2
#endif

73
arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
View File

@ -4,36 +4,9 @@
* Licensed under the GPL-2 or later
*/
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
@ -54,50 +27,6 @@
# endif
#endif
#define BFIN_UART_TX_FIFO_SIZE 2
/*
* The pin configuration is different from schematic
*/
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
int status_irq;
unsigned int lsr;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif
};
/* The hardware clears the LSR bits upon read, so we need to cache
* some of the more fun bits in software so they don't get lost
* when checking the LSR in other code paths (TX).
*/
static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
{
unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
uart->lsr |= (lsr & (BI|FE|PE|OE));
return lsr | uart->lsr;
}
static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
{
uart->lsr = 0;
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

74
arch/blackfin/mach-bf518/include/mach/blackfin.h
View File

@ -1,61 +1,43 @@
/*
* Copyright 2008-2009 Analog Devices Inc.
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#include "bf518.h"
#include "defBF512.h"
#include "anomaly.h"
#if defined(CONFIG_BF518)
#include "defBF518.h"
#include <asm/def_LPBlackfin.h>
#ifdef CONFIG_BF512
# include "defBF512.h"
#endif
#ifdef CONFIG_BF514
# include "defBF514.h"
#endif
#ifdef CONFIG_BF516
# include "defBF516.h"
#endif
#ifdef CONFIG_BF518
# include "defBF518.h"
#endif
#if defined(CONFIG_BF516)
#include "defBF516.h"
#ifndef __ASSEMBLY__
# include <asm/cdef_LPBlackfin.h>
# ifdef CONFIG_BF512
# include "cdefBF512.h"
# endif
# ifdef CONFIG_BF514
# include "cdefBF514.h"
# endif
# ifdef CONFIG_BF516
# include "cdefBF516.h"
# endif
# ifdef CONFIG_BF518
# include "cdefBF518.h"
# endif
#endif
#if defined(CONFIG_BF514)
#include "defBF514.h"
#endif
#if defined(CONFIG_BF512)
#include "defBF512.h"
#endif
#if !defined(__ASSEMBLY__)
#include "cdefBF512.h"
#if defined(CONFIG_BF518)
#include "cdefBF518.h"
#endif
#if defined(CONFIG_BF516)
#include "cdefBF516.h"
#endif
#if defined(CONFIG_BF514)
#include "cdefBF514.h"
#endif
#endif
#define BFIN_UART_NR_PORTS 2
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
#endif

1038
arch/blackfin/mach-bf518/include/mach/cdefBF512.h
View File

File diff suppressed because it is too large Load Diff

5
arch/blackfin/mach-bf518/include/mach/cdefBF514.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Analog Devices Inc.
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
@ -7,9 +7,6 @@
#ifndef _CDEF_BF514_H
#define _CDEF_BF514_H
/* include all Core registers and bit definitions */
#include "defBF514.h"
/* BF514 is BF512 + RSI */
#include "cdefBF512.h"

5
arch/blackfin/mach-bf518/include/mach/cdefBF516.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Analog Devices Inc.
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
@ -7,9 +7,6 @@
#ifndef _CDEF_BF516_H
#define _CDEF_BF516_H
/* include all Core registers and bit definitions */
#include "defBF516.h"
/* BF516 is BF514 + EMAC */
#include "cdefBF514.h"

5
arch/blackfin/mach-bf518/include/mach/cdefBF518.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Analog Devices Inc.
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
@ -7,9 +7,6 @@
#ifndef _CDEF_BF518_H
#define _CDEF_BF518_H
/* include all Core registers and bit definitions */
#include "defBF518.h"
/* BF518 is BF516 + IEEE-1588 */
#include "cdefBF516.h"

1061
arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
View File

File diff suppressed because it is too large Load Diff

1388
arch/blackfin/mach-bf518/include/mach/defBF512.h
View File

File diff suppressed because it is too large Load Diff

1495
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View File

File diff suppressed because it is too large Load Diff

4
arch/blackfin/mach-bf518/include/mach/gpio.h
View File

@ -55,4 +55,8 @@
#define PORT_G GPIO_PG0
#define PORT_H GPIO_PH0
#include <mach-common/ports-f.h>
#include <mach-common/ports-g.h>
#include <mach-common/ports-h.h>
#endif /* _MACH_GPIO_H_ */

64
arch/blackfin/mach-bf518/include/mach/pll.h
View File

@ -1,63 +1 @@
/*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
#include <mach-common/pll.h>

13
arch/blackfin/mach-bf527/boards/ad7160eval.c
View File

@ -67,6 +67,7 @@ static struct musb_hdrc_config musb_config = {
* if it is the case.
*/
.gpio_vrsel_active = 1,
.clkin = 24, /* musb CLKIN in MHZ */
};
static struct musb_hdrc_platform_data musb_plat = {
@ -419,7 +420,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -474,7 +475,7 @@ static struct resource bfin_uart1_resources[] = {
#endif
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -627,9 +628,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -661,9 +662,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

13
arch/blackfin/mach-bf527/boards/cm_bf527.c
View File

@ -104,6 +104,7 @@ static struct musb_hdrc_config musb_config = {
* if it is the case.
*/
.gpio_vrsel_active = 1,
.clkin = 24, /* musb CLKIN in MHZ */
};
static struct musb_hdrc_platform_data musb_plat = {
@ -614,7 +615,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -669,7 +670,7 @@ static struct resource bfin_uart1_resources[] = {
#endif
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -801,9 +802,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -835,9 +836,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

13
arch/blackfin/mach-bf527/boards/ezbrd.c
View File

@ -68,6 +68,7 @@ static struct musb_hdrc_config musb_config = {
* if it is the case.
*/
.gpio_vrsel_active = 1,
.clkin = 24, /* musb CLKIN in MHZ */
};
static struct musb_hdrc_platform_data musb_plat = {
@ -499,7 +500,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -554,7 +555,7 @@ static struct resource bfin_uart1_resources[] = {
#endif
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -681,9 +682,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -715,9 +716,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

18
arch/blackfin/mach-bf527/boards/ezkit.c
View File

@ -108,6 +108,7 @@ static struct musb_hdrc_config musb_config = {
* if it is the case.
*/
.gpio_vrsel_active = 1,
.clkin = 24, /* musb CLKIN in MHZ */
};
static struct musb_hdrc_platform_data musb_plat = {
@ -708,7 +709,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -763,7 +764,7 @@ static struct resource bfin_uart1_resources[] = {
#endif
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -962,6 +963,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
I2C_BOARD_INFO("ad5252", 0x2f),
},
#endif
#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
{
I2C_BOARD_INFO("adau1373", 0x1A),
},
#endif
};
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@ -984,9 +990,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -1018,9 +1024,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

14
arch/blackfin/mach-bf527/boards/tll6527m.c
View File

@ -193,7 +193,7 @@ static unsigned gpio_addr_inputs[] = {
GPIO_PG1, GPIO_PH9, GPIO_PH10
};
static struct gpio_decoder_platfrom_data spi_decoded_cs = {
static struct gpio_decoder_platform_data spi_decoded_cs = {
.base = EXP_GPIO_SPISEL_BASE,
.input_addrs = gpio_addr_inputs,
.nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
@ -586,7 +586,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -642,7 +642,7 @@ static struct resource bfin_uart1_resources[] = {
#endif
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -799,9 +799,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -834,9 +834,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

2
arch/blackfin/mach-bf527/dma.c
View File

@ -11,7 +11,7 @@
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,

14
arch/blackfin/mach-bf527/include/mach/bfin_serial.h Normal file
View File

@ -0,0 +1,14 @@
/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 2
#endif

73
arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
View File

@ -4,36 +4,9 @@
* Licensed under the GPL-2 or later
*/
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
@ -54,50 +27,6 @@
# endif
#endif
#define BFIN_UART_TX_FIFO_SIZE 2
/*
* The pin configuration is different from schematic
*/
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
int status_irq;
unsigned int lsr;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif
};
/* The hardware clears the LSR bits upon read, so we need to cache
* some of the more fun bits in software so they don't get lost
* when checking the LSR in other code paths (TX).
*/
static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
{
unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
uart->lsr |= (lsr & (BI|FE|PE|OE));
return lsr | uart->lsr;
}
static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
{
uart->lsr = 0;
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

50
arch/blackfin/mach-bf527/include/mach/blackfin.h
View File

@ -1,49 +1,37 @@
/*
* Copyright 2007-2009 Analog Devices Inc.
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#include "bf527.h"
#include "defBF522.h"
#include "anomaly.h"
#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
#include "defBF527.h"
#include <asm/def_LPBlackfin.h>
#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
# include "defBF522.h"
#endif
#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
#include "defBF525.h"
# include "defBF525.h"
#endif
#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
# include "defBF527.h"
#endif
#if !defined(__ASSEMBLY__)
#include "cdefBF522.h"
#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
#include "cdefBF527.h"
# include <asm/cdef_LPBlackfin.h>
# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
# include "cdefBF522.h"
# endif
# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
# include "cdefBF525.h"
# endif
# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
# include "cdefBF527.h"
# endif
#endif
#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
#include "cdefBF525.h"
#endif
#endif
#define BFIN_UART_NR_PORTS 2
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
#endif

1092
arch/blackfin/mach-bf527/include/mach/cdefBF522.h
View File

File diff suppressed because it is too large Load Diff

7
arch/blackfin/mach-bf527/include/mach/cdefBF525.h
View File

@ -1,15 +1,12 @@
/*
* Copyright 2007-2008 Analog Devices Inc.
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
* Licensed under the GPL-2 or later.
*/
#ifndef _CDEF_BF525_H
#define _CDEF_BF525_H
/* include all Core registers and bit definitions */
#include "defBF525.h"
/* BF525 is BF522 + USB */
#include "cdefBF522.h"

7
arch/blackfin/mach-bf527/include/mach/cdefBF527.h
View File

@ -1,15 +1,12 @@
/*
* Copyright 2007-2008 Analog Devices Inc.
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
* Licensed under the GPL-2 or later.
*/
#ifndef _CDEF_BF527_H
#define _CDEF_BF527_H
/* include all Core registers and bit definitions */
#include "defBF527.h"
/* BF527 is BF525 + EMAC */
#include "cdefBF525.h"

1113
arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
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File diff suppressed because it is too large Load Diff

1393
arch/blackfin/mach-bf527/include/mach/defBF522.h
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File diff suppressed because it is too large Load Diff

2
arch/blackfin/mach-bf527/include/mach/defBF525.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007-2008 Analog Devices Inc.
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/

2
arch/blackfin/mach-bf527/include/mach/defBF527.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007-2008 Analog Devices Inc.
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/

1506
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
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File diff suppressed because it is too large Load Diff

4
arch/blackfin/mach-bf527/include/mach/gpio.h
View File

@ -62,4 +62,8 @@
#define PORT_G GPIO_PG0
#define PORT_H GPIO_PH0
#include <mach-common/ports-f.h>
#include <mach-common/ports-g.h>
#include <mach-common/ports-h.h>
#endif /* _MACH_GPIO_H_ */

64
arch/blackfin/mach-bf527/include/mach/pll.h
View File

@ -1,63 +1 @@
/*
* Copyright 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
#include <mach-common/pll.h>

2
arch/blackfin/mach-bf533/boards/H8606.c
View File

@ -286,7 +286,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};

25
arch/blackfin/mach-bf533/boards/blackstamp.c
View File

@ -25,7 +25,6 @@
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <mach/fio_flag.h>
/*
* Name the Board for the /proc/cpuinfo
@ -225,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -290,9 +289,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -324,9 +323,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {
@ -476,10 +475,16 @@ static int __init blackstamp_init(void)
return ret;
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
/* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
bfin_write_FIO_FLAG_S(PF0);
SSYNC();
/*
* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
* the bfin-async-map driver takes care of flipping between
* flash and ethernet when necessary.
*/
ret = gpio_request(GPIO_PF0, "enet_cpld");
if (!ret) {
gpio_direction_output(GPIO_PF0, 1);
gpio_free(GPIO_PF0);
}
#endif
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));

10
arch/blackfin/mach-bf533/boards/cm_bf533.c
View File

@ -271,7 +271,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -336,9 +336,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -370,9 +370,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

2
arch/blackfin/mach-bf533/boards/ezkit.c
View File

@ -349,7 +349,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};

11
arch/blackfin/mach-bf533/boards/ip0x.c
View File

@ -22,7 +22,6 @@
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <mach/fio_flag.h>
/*
* Name the Board for the /proc/cpuinfo
@ -174,7 +173,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -295,15 +294,7 @@ static int __init ip0x_init(void)
printk(KERN_INFO "%s(): registering device resources\n", __func__);
platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
int j = 1 << bfin_spi_board_info[i].chip_select;
/* set spi cs to 1 */
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
bfin_write_FIO_FLAG_S(j);
}
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif
return 0;
}

30
arch/blackfin/mach-bf533/boards/stamp.c
View File

@ -24,7 +24,6 @@
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <mach/fio_flag.h>
/*
* Name the Board for the /proc/cpuinfo
@ -354,7 +353,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -419,9 +418,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -453,9 +452,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {
@ -674,10 +673,16 @@ static int __init stamp_init(void)
return ret;
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
/* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
bfin_write_FIO_FLAG_S(PF0);
SSYNC();
/*
* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
* the bfin-async-map driver takes care of flipping between
* flash and ethernet when necessary.
*/
ret = gpio_request(GPIO_PF0, "enet_cpld");
if (!ret) {
gpio_direction_output(GPIO_PF0, 1);
gpio_free(GPIO_PF0);
}
#endif
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
@ -713,7 +718,6 @@ void __init native_machine_early_platform_add_devices(void)
void native_machine_restart(char *cmd)
{
/* workaround pull up on cpld / flash pin not being strong enough */
bfin_write_FIO_INEN(~PF0);
bfin_write_FIO_DIR(PF0);
bfin_write_FIO_FLAG_C(PF0);
gpio_request(GPIO_PF0, "flash_cpld");
gpio_direction_output(GPIO_PF0, 0);
}

2
arch/blackfin/mach-bf533/dma.c
View File

@ -11,7 +11,7 @@
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,

14
arch/blackfin/mach-bf533/include/mach/bfin_serial.h Normal file
View File

@ -0,0 +1,14 @@
/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 1
#endif

74
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
View File

@ -4,36 +4,9 @@
* Licensed under the GPL-2 or later
*/
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
@ -44,51 +17,6 @@
# endif
#endif
#define BFIN_UART_TX_FIFO_SIZE 2
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
int status_irq;
unsigned int lsr;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#else
# if ANOMALY_05000363
unsigned int anomaly_threshold;
# endif
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif
};
/* The hardware clears the LSR bits upon read, so we need to cache
* some of the more fun bits in software so they don't get lost
* when checking the LSR in other code paths (TX).
*/
static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
{
unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
uart->lsr |= (lsr & (BI|FE|PE|OE));
return lsr | uart->lsr;
}
static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
{
uart->lsr = 0;
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

30
arch/blackfin/mach-bf533/include/mach/blackfin.h
View File

@ -1,7 +1,7 @@
/*
* Copyright 2005-2009 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
@ -10,26 +10,14 @@
#define BF533_FAMILY
#include "bf533.h"
#include "defBF532.h"
#include "anomaly.h"
#if !defined(__ASSEMBLY__)
#include "cdefBF532.h"
#include <asm/def_LPBlackfin.h>
#include "defBF532.h"
#ifndef __ASSEMBLY__
# include <asm/cdef_LPBlackfin.h>
# include "cdefBF532.h"
#endif
#define BFIN_UART_NR_PORTS 1
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
#endif /* _MACH_BLACKFIN_H_ */
#endif

63
arch/blackfin/mach-bf533/include/mach/cdefBF532.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
@ -7,9 +7,6 @@
#ifndef _CDEF_BF532_H
#define _CDEF_BF532_H
/*include core specific register pointer definitions*/
#include <asm/cdef_LPBlackfin.h>
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
@ -66,16 +63,10 @@
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
/* DMA Traffic controls */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
@ -105,6 +96,47 @@
#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
#if ANOMALY_05000311
/* Keep at the CPP expansion to avoid circular header dependency loops */
#define BFIN_WRITE_FIO_FLAG(name, val) \
do { \
unsigned long __flags; \
__flags = hard_local_irq_save(); \
bfin_write16(FIO_FLAG_##name, val); \
bfin_read_CHIPID(); \
hard_local_irq_restore(__flags); \
} while (0)
#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
#define BFIN_READ_FIO_FLAG(name) \
({ \
unsigned long __flags; \
u16 __ret; \
__flags = hard_local_irq_save(); \
__ret = bfin_read16(FIO_FLAG_##name); \
bfin_read_CHIPID(); \
hard_local_irq_restore(__flags); \
__ret; \
})
#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
#else
#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
#endif
/* DMA Controller */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
@ -647,7 +679,4 @@
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
#endif /* _CDEF_BF532_H */

128
arch/blackfin/mach-bf533/include/mach/defBF532.h
View File

@ -1,7 +1,7 @@
/*
* System & MMR bit and Address definitions for ADSP-BF532
*
* Copyright 2005-2008 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
@ -9,9 +9,6 @@
#ifndef _DEF_BF532_H
#define _DEF_BF532_H
/* include all Core registers and bit definitions */
#include <asm/def_LPBlackfin.h>
/*********************************************************************************** */
/* System MMR Register Map */
/*********************************************************************************** */
@ -182,12 +179,8 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic controls */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
@ -432,83 +425,6 @@
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
/* ***************************** UART CONTROLLER MASKS ********************** */
/* UART_LCR Register */
#define DLAB 0x80
#define SB 0x40
#define STP 0x20
#define EPS 0x10
#define PEN 0x08
#define STB 0x04
#define WLS(x) ((x-5) & 0x03)
#define DLAB_P 0x07
#define SB_P 0x06
#define STP_P 0x05
#define EPS_P 0x04
#define PEN_P 0x03
#define STB_P 0x02
#define WLS_P1 0x01
#define WLS_P0 0x00
/* UART_MCR Register */
#define LOOP_ENA 0x10
#define LOOP_ENA_P 0x04
/* UART_LSR Register */
#define TEMT 0x40
#define THRE 0x20
#define BI 0x10
#define FE 0x08
#define PE 0x04
#define OE 0x02
#define DR 0x01
#define TEMP_P 0x06
#define THRE_P 0x05
#define BI_P 0x04
#define FE_P 0x03
#define PE_P 0x02
#define OE_P 0x01
#define DR_P 0x00
/* UART_IER Register */
#define ELSI 0x04
#define ETBEI 0x02
#define ERBFI 0x01
#define ELSI_P 0x02
#define ETBEI_P 0x01
#define ERBFI_P 0x00
/* UART_IIR Register */
#define STATUS(x) ((x << 1) & 0x06)
#define NINT 0x01
#define STATUS_P1 0x02
#define STATUS_P0 0x01
#define NINT_P 0x00
#define IIR_TX_READY 0x02 /* UART_THR empty */
#define IIR_RX_READY 0x04 /* Receive data ready */
#define IIR_LINE_CHANGE 0x06 /* Receive line status */
#define IIR_STATUS 0x06
/* UART_GCTL Register */
#define FFE 0x20
#define FPE 0x10
#define RPOLC 0x08
#define TPOLC 0x04
#define IREN 0x02
#define UCEN 0x01
#define FFE_P 0x05
#define FPE_P 0x04
#define RPOLC_P 0x03
#define TPOLC_P 0x02
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */
@ -643,44 +559,6 @@
#define ERR_TYP_P0 0x0E
#define ERR_TYP_P1 0x0F
/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
#define PF0 0x0001
#define PF1 0x0002
#define PF2 0x0004
#define PF3 0x0008
#define PF4 0x0010
#define PF5 0x0020
#define PF6 0x0040
#define PF7 0x0080
#define PF8 0x0100
#define PF9 0x0200
#define PF10 0x0400
#define PF11 0x0800
#define PF12 0x1000
#define PF13 0x2000
#define PF14 0x4000
#define PF15 0x8000
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
#define PF0_P 0
#define PF1_P 1
#define PF2_P 2
#define PF3_P 3
#define PF4_P 4
#define PF5_P 5
#define PF6_P 6
#define PF7_P 7
#define PF8_P 8
#define PF9_P 9
#define PF10_P 10
#define PF11_P 11
#define PF12_P 12
#define PF13_P 13
#define PF14_P 14
#define PF15_P 15
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
/* AMGCTL Masks */

55
arch/blackfin/mach-bf533/include/mach/fio_flag.h
View File

@ -1,55 +0,0 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_FIO_FLAG_H
#define _MACH_FIO_FLAG_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
#if ANOMALY_05000311
#define BFIN_WRITE_FIO_FLAG(name) \
static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
{ \
unsigned long flags; \
flags = hard_local_irq_save(); \
bfin_write16(FIO_FLAG_##name, val); \
bfin_read_CHIPID(); \
hard_local_irq_restore(flags); \
}
BFIN_WRITE_FIO_FLAG(D)
BFIN_WRITE_FIO_FLAG(C)
BFIN_WRITE_FIO_FLAG(S)
BFIN_WRITE_FIO_FLAG(T)
#define BFIN_READ_FIO_FLAG(name) \
static inline u16 bfin_read_FIO_FLAG_##name(void) \
{ \
unsigned long flags; \
u16 ret; \
flags = hard_local_irq_save(); \
ret = bfin_read16(FIO_FLAG_##name); \
bfin_read_CHIPID(); \
hard_local_irq_restore(flags); \
return ret; \
}
BFIN_READ_FIO_FLAG(D)
BFIN_READ_FIO_FLAG(C)
BFIN_READ_FIO_FLAG(S)
BFIN_READ_FIO_FLAG(T)
#else
#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
#endif
#endif /* _MACH_FIO_FLAG_H */

2
arch/blackfin/mach-bf533/include/mach/gpio.h
View File

@ -28,4 +28,6 @@
#define PORT_F GPIO_PF0
#include <mach-common/ports-f.h>
#endif /* _MACH_GPIO_H_ */

58
arch/blackfin/mach-bf533/include/mach/pll.h
View File

@ -1,57 +1 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
#include <mach-common/pll.h>

6
arch/blackfin/mach-bf537/boards/Kconfig
View File

@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
help
Board supply package for CSP Minotaur
config DNP5370
bool "SSV Dil/NetPC DNP/5370"
depends on (BF537)
help
Board supply package for DNP/5370 DIL64 module
endchoice

1
arch/blackfin/mach-bf537/boards/Makefile
View File

@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
obj-$(CONFIG_PNAV10) += pnav10.o
obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
obj-$(CONFIG_DNP5370) += dnp5370.o

12
arch/blackfin/mach-bf537/boards/cm_bf537e.c
View File

@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = {
#endif
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = {
#endif
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

12
arch/blackfin/mach-bf537/boards/cm_bf537u.c
View File

@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

418
arch/blackfin/mach-bf537/boards/dnp5370.c Normal file
View File

@ -0,0 +1,418 @@
/*
* This is the configuration for SSV Dil/NetPC DNP/5370 board.
*
* DIL module: http://www.dilnetpc.com/dnp0086.htm
* SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
*
* Copyright 2010 3ality Digital Systems
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2006 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/plat-ram.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/spi/mmc_spi.h>
#include <linux/phy.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
/*
* Name the Board for the /proc/cpuinfo
*/
const char bfin_board_name[] = "DNP/5370";
#define FLASH_MAC 0x202f0000
#define CONFIG_MTD_PHYSMAP_LEN 0x300000
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
#include <linux/bfin_mac.h>
static const unsigned short bfin_mac_peripherals[] = P_RMII0;
static struct bfin_phydev_platform_data bfin_phydev_data[] = {
{
.addr = 1,
.irq = PHY_POLL, /* IRQ_MAC_PHYINT */
},
};
static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
.phydev_number = 1,
.phydev_data = bfin_phydev_data,
.phy_mode = PHY_INTERFACE_MODE_RMII,
.mac_peripherals = bfin_mac_peripherals,
};
static struct platform_device bfin_mii_bus = {
.name = "bfin_mii_bus",
.dev = {
.platform_data = &bfin_mii_bus_data,
}
};
static struct platform_device bfin_mac_device = {
.name = "bfin_mac",
.dev = {
.platform_data = &bfin_mii_bus,
}
};
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition asmb_flash_partitions[] = {
{
.name = "bootloader(nor)",
.size = 0x30000,
.offset = 0,
}, {
.name = "linux kernel and rootfs(nor)",
.size = 0x300000 - 0x30000 - 0x10000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "MAC address(nor)",
.size = 0x10000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE,
}
};
static struct physmap_flash_data asmb_flash_data = {
.width = 1,
.parts = asmb_flash_partitions,
.nr_parts = ARRAY_SIZE(asmb_flash_partitions),
};
static struct resource asmb_flash_resource = {
.start = 0x20000000,
.end = 0x202fffff,
.flags = IORESOURCE_MEM,
};
/* 4 MB NOR flash attached to async memory banks 0-2,
* therefore only 3 MB visible.
*/
static struct platform_device asmb_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &asmb_flash_data,
},
.num_resources = 1,
.resource = &asmb_flash_resource,
};
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
static int bfin_mmc_spi_init(struct device *dev,
irqreturn_t (*detect_int)(int, void *), void *data)
{
return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
}
static void bfin_mmc_spi_exit(struct device *dev, void *data)
{
free_irq(MMC_SPI_CARD_DETECT_INT, data);
}
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
.enable_dma = 0, /* use no dma transfer with this chip*/
.bits_per_word = 8,
};
static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
.init = bfin_mmc_spi_init,
.exit = bfin_mmc_spi_exit,
.detect_delay = 100, /* msecs */
};
#endif
#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
/* This mapping is for at45db642 it has 1056 page size,
* partition size and offset should be page aligned
*/
static struct mtd_partition bfin_spi_dataflash_partitions[] = {
{
.name = "JFFS2 dataflash(nor)",
#ifdef CONFIG_MTD_PAGESIZE_1024
.offset = 0x40000,
.size = 0x7C0000,
#else
.offset = 0x0,
.size = 0x840000,
#endif
}
};
static struct flash_platform_data bfin_spi_dataflash_data = {
.name = "mtd_dataflash",
.parts = bfin_spi_dataflash_partitions,
.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
.type = "mtd_dataflash",
};
static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
.enable_dma = 0, /* use no dma transfer with this chip*/
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
/* SD/MMC card reader at SPI bus */
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
{
.modalias = "mmc_spi",
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 1,
.platform_data = &bfin_mmc_spi_pdata,
.controller_data = &mmc_spi_chip_info,
.mode = SPI_MODE_3,
},
#endif
/* 8 Megabyte Atmel NOR flash chip at SPI bus */
#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
{
.modalias = "mtd_dataflash",
.max_speed_hz = 16700000,
.bus_num = 0,
.chip_select = 2,
.platform_data = &bfin_spi_dataflash_data,
.controller_data = &spi_dataflash_chip_info,
.mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
},
#endif
};
/* SPI controller data */
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
[0] = {
.start = SPI0_REGBASE,
.end = SPI0_REGBASE + 0xFF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CH_SPI,
.end = CH_SPI,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = IRQ_SPI,
.end = IRQ_SPI,
.flags = IORESOURCE_IRQ,
},
};
static struct bfin5xx_spi_master spi_bfin_master_info = {
.num_chipselect = 8,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
static struct platform_device spi_bfin_master_device = {
.name = "bfin-spi",
.id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource,
.dev = {
.platform_data = &spi_bfin_master_info, /* Passed to driver */
},
};
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
static struct resource bfin_uart0_resources[] = {
{
.start = UART0_THR,
.end = UART0_GCTL+2,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART0_RX,
.end = IRQ_UART0_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_UART0_ERROR,
.end = IRQ_UART0_ERROR,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_UART0_TX,
.end = CH_UART0_TX,
.flags = IORESOURCE_DMA,
},
{
.start = CH_UART0_RX,
.end = CH_UART0_RX,
.flags = IORESOURCE_DMA,
},
};
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
static struct platform_device bfin_uart0_device = {
.name = "bfin-uart",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
.resource = bfin_uart0_resources,
.dev = {
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
},
};
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
static struct resource bfin_uart1_resources[] = {
{
.start = UART1_THR,
.end = UART1_GCTL+2,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART1_RX,
.end = IRQ_UART1_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_UART1_ERROR,
.end = IRQ_UART1_ERROR,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_UART1_TX,
.end = CH_UART1_TX,
.flags = IORESOURCE_DMA,
},
{
.start = CH_UART1_RX,
.end = CH_UART1_RX,
.flags = IORESOURCE_DMA,
},
};
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
static struct platform_device bfin_uart1_device = {
.name = "bfin-uart",
.id = 1,
.num_resources = ARRAY_SIZE(bfin_uart1_resources),
.resource = bfin_uart1_resources,
.dev = {
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
},
};
#endif
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
.end = TWI0_REGBASE + 0xff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_TWI,
.end = IRQ_TWI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c_bfin_twi_device = {
.name = "i2c-bfin-twi",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
};
#endif
static struct platform_device *dnp5370_devices[] __initdata = {
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
&bfin_uart0_device,
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
&bfin_uart1_device,
#endif
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&asmb_flash_device,
#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
&bfin_mii_bus,
&bfin_mac_device,
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&spi_bfin_master_device,
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
};
static int __init dnp5370_init(void)
{
printk(KERN_INFO "DNP/5370: registering device resources\n");
platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
ARRAY_SIZE(bfin_spi_board_info));
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
return 0;
}
arch_initcall(dnp5370_init);
/*
* Currently the MAC address is saved in Flash by U-Boot
*/
void bfin_get_ether_addr(char *addr)
{
*(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
*(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
}
EXPORT_SYMBOL(bfin_get_ether_addr);

12
arch/blackfin/mach-bf537/boards/minotaur.c
View File

@ -263,7 +263,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -306,7 +306,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -419,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -453,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

4
arch/blackfin/mach-bf537/boards/pnav10.c
View File

@ -367,7 +367,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -410,7 +410,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};

18
arch/blackfin/mach-bf537/boards/stamp.c
View File

@ -289,7 +289,7 @@ static struct platform_device isp1362_hcd_device = {
#endif
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
unsigned short bfin_can_peripherals[] = {
static unsigned short bfin_can_peripherals[] = {
P_CAN0_RX, P_CAN0_TX, 0
};
@ -693,7 +693,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
#endif
#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
unsigned short ad2s120x_platform_data[] = {
static unsigned short ad2s120x_platform_data[] = {
/* used as SAMPLE and RDVEL */
GPIO_PF5, GPIO_PF6, 0
};
@ -705,7 +705,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
#endif
#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
unsigned short ad2s1210_platform_data[] = {
static unsigned short ad2s1210_platform_data[] = {
/* use as SAMPLE, A0, A1 */
GPIO_PF7, GPIO_PF8, GPIO_PF9,
# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
@ -1717,7 +1717,7 @@ static struct resource bfin_uart0_resources[] = {
#endif
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -1760,7 +1760,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -2447,9 +2447,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -2481,9 +2481,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

12
arch/blackfin/mach-bf537/boards/tcm_bf537.c
View File

@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
},
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {

2
arch/blackfin/mach-bf537/dma.c
View File

@ -11,7 +11,7 @@
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,

14
arch/blackfin/mach-bf537/include/mach/bfin_serial.h Normal file
View File

@ -0,0 +1,14 @@
/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 2
#endif

72
arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
View File

@ -4,36 +4,9 @@
* Licensed under the GPL-2 or later
*/
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
@ -54,49 +27,6 @@
# endif
#endif
#define BFIN_UART_TX_FIFO_SIZE 2
/*
* The pin configuration is different from schematic
*/
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
int status_irq;
unsigned int lsr;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int cts_pin;
int rts_pin;
#endif
};
/* The hardware clears the LSR bits upon read, so we need to cache
* some of the more fun bits in software so they don't get lost
* when checking the LSR in other code paths (TX).
*/
static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
{
unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
uart->lsr |= (lsr & (BI|FE|PE|OE));
return lsr | uart->lsr;
}
static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
{
uart->lsr = 0;
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

38
arch/blackfin/mach-bf537/include/mach/blackfin.h
View File

@ -1,7 +1,7 @@
/*
* Copyright 2005-2009 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
@ -10,34 +10,24 @@
#define BF537_FAMILY
#include "bf537.h"
#include "defBF534.h"
#include "anomaly.h"
#include <asm/def_LPBlackfin.h>
#ifdef CONFIG_BF534
# include "defBF534.h"
#endif
#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
#include "defBF537.h"
# include "defBF537.h"
#endif
#if !defined(__ASSEMBLY__)
#include "cdefBF534.h"
#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
#include "cdefBF537.h"
#endif
# include <asm/cdef_LPBlackfin.h>
# ifdef CONFIG_BF534
# include "cdefBF534.h"
# endif
# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
# include "cdefBF537.h"
# endif
#endif
#define BFIN_UART_NR_PORTS 2
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
#endif

27
arch/blackfin/mach-bf537/include/mach/cdefBF534.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
@ -7,14 +7,6 @@
#ifndef _CDEF_BF534_H
#define _CDEF_BF534_H
#include <asm/blackfin.h>
/* Include all Core registers and bit definitions */
#include "defBF534.h"
/* Include core specific register pointer definitions */
#include <asm/cdef_LPBlackfin.h>
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
@ -355,16 +347,10 @@
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
/* DMA Traffic Control Registers */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
/* DMA Controller */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
@ -1747,7 +1733,4 @@
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
#endif /* _CDEF_BF534_H */

5
arch/blackfin/mach-bf537/include/mach/cdefBF537.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
@ -10,9 +10,6 @@
/* Include MMRs Common to BF534 */
#include "cdefBF534.h"
/* Include all Core registers and bit definitions */
#include "defBF537.h"
/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)

111
arch/blackfin/mach-bf537/include/mach/defBF534.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
@ -7,9 +7,6 @@
#ifndef _DEF_BF534_H
#define _DEF_BF534_H
/* Include all Core registers and bit definitions */
#include <asm/def_LPBlackfin.h>
/************************************************************************************
** System MMR Register Map
*************************************************************************************/
@ -193,12 +190,8 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic Control Registers */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@ -1029,48 +1022,6 @@
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
/* ************** UART CONTROLLER MASKS *************************/
/* UARTx_LCR Masks */
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
#define STP 0x20 /* Stick Parity */
#define SB 0x40 /* Set Break */
#define DLAB 0x80 /* Divisor Latch Access */
/* UARTx_MCR Mask */
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
#define LOOP_ENA_P 0x04
/* UARTx_LSR Masks */
#define DR 0x01 /* Data Ready */
#define OE 0x02 /* Overrun Error */
#define PE 0x04 /* Parity Error */
#define FE 0x08 /* Framing Error */
#define BI 0x10 /* Break Interrupt */
#define THRE 0x20 /* THR Empty */
#define TEMT 0x40 /* TSR and UART_THR Empty */
/* UARTx_IER Masks */
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
#define ELSI 0x04 /* Enable RX Status Interrupt */
/* UARTx_IIR Masks */
#define NINT 0x01 /* Pending Interrupt */
#define IIR_TX_READY 0x02 /* UART_THR empty */
#define IIR_RX_READY 0x04 /* Receive data ready */
#define IIR_LINE_CHANGE 0x06 /* Receive line status */
#define IIR_STATUS 0x06
/* UARTx_GCTL Masks */
#define UCEN 0x01 /* Enable UARTx Clocks */
#define IREN 0x02 /* Enable IrDA Mode */
#define TPOLC 0x04 /* IrDA TX Polarity Change */
#define RPOLC 0x08 /* IrDA RX Polarity Change */
#define FPE 0x10 /* Force Parity Error On Transmit */
#define FFE 0x20 /* Force Framing Error On Transmit */
/* **************** GENERAL PURPOSE TIMER MASKS **********************/
/* TIMER_ENABLE Masks */
#define TIMEN0 0x0001 /* Enable Timer 0 */
@ -1141,62 +1092,6 @@
#define EMU_RUN 0x0200 /* Emulation Behavior Select */
#define ERR_TYP 0xC000 /* Error Type */
/* ****************** GPIO PORTS F, G, H MASKS ***********************/
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
/* Port F Masks */
#define PF0 0x0001
#define PF1 0x0002
#define PF2 0x0004
#define PF3 0x0008
#define PF4 0x0010
#define PF5 0x0020
#define PF6 0x0040
#define PF7 0x0080
#define PF8 0x0100
#define PF9 0x0200
#define PF10 0x0400
#define PF11 0x0800
#define PF12 0x1000
#define PF13 0x2000
#define PF14 0x4000
#define PF15 0x8000
/* Port G Masks */
#define PG0 0x0001
#define PG1 0x0002
#define PG2 0x0004
#define PG3 0x0008
#define PG4 0x0010
#define PG5 0x0020
#define PG6 0x0040
#define PG7 0x0080
#define PG8 0x0100
#define PG9 0x0200
#define PG10 0x0400
#define PG11 0x0800
#define PG12 0x1000
#define PG13 0x2000
#define PG14 0x4000
#define PG15 0x8000
/* Port H Masks */
#define PH0 0x0001
#define PH1 0x0002
#define PH2 0x0004
#define PH3 0x0008
#define PH4 0x0010
#define PH5 0x0020
#define PH6 0x0040
#define PH7 0x0080
#define PH8 0x0100
#define PH9 0x0200
#define PH10 0x0400
#define PH11 0x0800
#define PH12 0x1000
#define PH13 0x2000
#define PH14 0x4000
#define PH15 0x8000
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

5
arch/blackfin/mach-bf537/include/mach/defBF537.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
@ -7,9 +7,6 @@
#ifndef _DEF_BF537_H
#define _DEF_BF537_H
/* Include all Core registers and bit definitions*/
#include <asm/cdef_LPBlackfin.h>
/* Include all MMR and bit defines common to BF534 */
#include "defBF534.h"

4
arch/blackfin/mach-bf537/include/mach/gpio.h
View File

@ -62,4 +62,8 @@
#define PORT_G GPIO_PG0
#define PORT_H GPIO_PH0
#include <mach-common/ports-f.h>
#include <mach-common/ports-g.h>
#include <mach-common/ports-h.h>
#endif /* _MACH_GPIO_H_ */

58
arch/blackfin/mach-bf537/include/mach/pll.h
View File

@ -1,57 +1 @@
/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
#include <mach-common/pll.h>

20
arch/blackfin/mach-bf538/boards/ezkit.c
View File

@ -82,7 +82,7 @@ static struct resource bfin_uart0_resources[] = {
#endif
};
unsigned short bfin_uart0_peripherals[] = {
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
@ -125,7 +125,7 @@ static struct resource bfin_uart1_resources[] = {
},
};
unsigned short bfin_uart1_peripherals[] = {
static unsigned short bfin_uart1_peripherals[] = {
P_UART1_TX, P_UART1_RX, 0
};
@ -168,7 +168,7 @@ static struct resource bfin_uart2_resources[] = {
},
};
unsigned short bfin_uart2_peripherals[] = {
static unsigned short bfin_uart2_peripherals[] = {
P_UART2_TX, P_UART2_RX, 0
};
@ -282,9 +282,9 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
unsigned short bfin_sport0_peripherals[] = {
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
@ -316,9 +316,9 @@ static struct resource bfin_sport1_uart_resources[] = {
},
};
unsigned short bfin_sport1_peripherals[] = {
static unsigned short bfin_sport1_peripherals[] = {
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
};
static struct platform_device bfin_sport1_uart_device = {
@ -350,7 +350,7 @@ static struct resource bfin_sport2_uart_resources[] = {
},
};
unsigned short bfin_sport2_peripherals[] = {
static unsigned short bfin_sport2_peripherals[] = {
P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
};
@ -384,7 +384,7 @@ static struct resource bfin_sport3_uart_resources[] = {
},
};
unsigned short bfin_sport3_peripherals[] = {
static unsigned short bfin_sport3_peripherals[] = {
P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
};
@ -402,7 +402,7 @@ static struct platform_device bfin_sport3_uart_device = {
#endif
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
unsigned short bfin_can_peripherals[] = {
static unsigned short bfin_can_peripherals[] = {
P_CAN0_RX, P_CAN0_TX, 0
};

18
arch/blackfin/mach-bf538/dma.c
View File

@ -11,7 +11,7 @@
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA17_NEXT_DESC_PTR,
(struct dma_register *) DMA18_NEXT_DESC_PTR,
(struct dma_register *) DMA19_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
};
EXPORT_SYMBOL(dma_io_base_addr);

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