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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel

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This commit is contained in:
Russell King 2008-12-18 22:15:48 +00:00 committed by Russell King
commit 0bd5292f58
22 changed files with 78 additions and 81 deletions
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8
arch/arm/mach-mx1/devices.c
View File

@ -232,25 +232,25 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
.chip.label = "gpio-0",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
.irq = GPIO_INT_PORTA,
.virtual_irq_start = MXC_MAX_INT_LINES
.virtual_irq_start = MXC_GPIO_IRQ_START
},
[1] = {
.chip.label = "gpio-1",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.irq = GPIO_INT_PORTB,
.virtual_irq_start = MXC_MAX_INT_LINES + 32
.virtual_irq_start = MXC_GPIO_IRQ_START + 32
},
[2] = {
.chip.label = "gpio-2",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
.irq = GPIO_INT_PORTC,
.virtual_irq_start = MXC_MAX_INT_LINES + 64
.virtual_irq_start = MXC_GPIO_IRQ_START + 64
},
[3] = {
.chip.label = "gpio-3",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.irq = GPIO_INT_PORTD,
.virtual_irq_start = MXC_MAX_INT_LINES + 96
.virtual_irq_start = MXC_GPIO_IRQ_START + 96
}
};

12
arch/arm/mach-mx2/devices.c
View File

@ -230,32 +230,32 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
.chip.label = "gpio-0",
.irq = MXC_INT_GPIO,
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
.virtual_irq_start = MXC_MAX_INT_LINES,
.virtual_irq_start = MXC_GPIO_IRQ_START,
},
[1] = {
.chip.label = "gpio-1",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
.virtual_irq_start = MXC_MAX_INT_LINES + 32,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
},
[2] = {
.chip.label = "gpio-2",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
.virtual_irq_start = MXC_MAX_INT_LINES + 64,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
},
[3] = {
.chip.label = "gpio-3",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
.virtual_irq_start = MXC_MAX_INT_LINES + 96,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
},
[4] = {
.chip.label = "gpio-4",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
.virtual_irq_start = MXC_MAX_INT_LINES + 128,
.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
},
[5] = {
.chip.label = "gpio-5",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
.virtual_irq_start = MXC_MAX_INT_LINES + 160,
.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
}
};

2
arch/arm/mach-mx2/mx27ads.c
View File

@ -93,7 +93,7 @@ static int uart_mxc_port1_init(struct platform_device *pdev)
static int uart_mxc_port1_exit(struct platform_device *pdev)
{
mxc_gpio_setup_release_pins(mxc_uart1_pins,
mxc_gpio_release_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins));
return 0;
}

1
arch/arm/mach-mx3/clock.c
View File

@ -24,6 +24,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#include <asm/div64.h>
#include "crm_regs.h"

6
arch/arm/mach-mx3/devices.c
View File

@ -125,19 +125,19 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_INT_BASE
.virtual_irq_start = MXC_GPIO_IRQ_START,
},
[1] = {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
},
[2] = {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}
};

1
arch/arm/plat-mxc/Kconfig
View File

@ -8,6 +8,7 @@ choice
config ARCH_MX1
bool "MX1-based"
select CPU_ARM920T
help
This enables support for systems based on the Freescale i.MX1 family

7
arch/arm/plat-mxc/dma-mx1-mx2.c
View File

@ -511,6 +511,7 @@ void imx_dma_disable(int channel)
}
EXPORT_SYMBOL(imx_dma_disable);
#ifdef CONFIG_ARCH_MX2
static void imx_dma_watchdog(unsigned long chno)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
@ -522,6 +523,7 @@ static void imx_dma_watchdog(unsigned long chno)
if (imxdma->err_handler)
imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
}
#endif
static irqreturn_t dma_err_handler(int irq, void *dev_id)
{
@ -674,7 +676,7 @@ int imx_dma_request(int channel, const char *name)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
unsigned long flags;
int ret;
int ret = 0;
/* basic sanity checks */
if (!name)
@ -696,6 +698,7 @@ int imx_dma_request(int channel, const char *name)
ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
NULL);
if (ret) {
local_irq_restore(flags);
printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
MXC_INT_DMACH0 + channel, channel);
return ret;
@ -712,7 +715,7 @@ int imx_dma_request(int channel, const char *name)
imxdma->sg = NULL;
local_irq_restore(flags);
return 0;
return ret;
}
EXPORT_SYMBOL(imx_dma_request);

2
arch/arm/plat-mxc/include/mach/board-mx27ads.h
View File

@ -15,7 +15,7 @@
#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
/* external interrupt multiplexer */
#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE

2
arch/arm/plat-mxc/include/mach/board-mx31ads.h
View File

@ -90,7 +90,7 @@
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)

2
arch/arm/plat-mxc/include/mach/entry-macro.S
View File

@ -9,6 +9,8 @@
* published by the Free Software Foundation.
*/
#include <mach/hardware.h>
#define AVIC_NIMASK 0x04
@ this macro disables fast irq (not implemented)

4
arch/arm/plat-mxc/include/mach/gpio.h
View File

@ -27,8 +27,8 @@
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio))
#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES)
#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
struct mxc_gpio_port {
void __iomem *base;

4
arch/arm/plat-mxc/include/mach/io.h
View File

@ -25,8 +25,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
/* Access all peripherals below 0x80000000 as nonshared device
* but leave l2cc alone.
*/
if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) ||
(phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE)))
if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) ||
(phys_addr >= 0x30000000 + SZ_1M)))
mtype = MT_DEVICE_NONSHARED;
}

4
arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
View File

@ -405,9 +405,9 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
#endif
/* decode irq number to use with IMR(x), ISR(x) and friends */
#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x)
#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)

2
arch/arm/plat-mxc/include/mach/iomux-mx3.h
View File

@ -141,7 +141,7 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
#define IOMUX_TO_IRQ(iomux_pin) \
(((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
MXC_GPIO_INT_BASE)
MXC_GPIO_IRQ_START)
/*
* This enumeration is constructed based on the Section

27
arch/arm/plat-mxc/include/mach/irqs.h
View File

@ -11,7 +11,32 @@
#ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__
#include <mach/hardware.h>
/*
* So far all i.MX SoCs have 64 internal interrupts
*/
#define MXC_INTERNAL_IRQS 64
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
#if defined CONFIG_ARCH_MX1
#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX2
#define MXC_GPIO_IRQS (32 * 6)
#elif defined CONFIG_ARCH_MX3
#define MXC_GPIO_IRQS (32 * 3)
#endif
/*
* The next 16 interrupts are for board specific purposes. Since
* the kernel can only run on one machine at a time, we can re-use
* these. If you need more, increase MXC_BOARD_IRQS, but keep it
* within sensible limits.
*/
#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
#define MXC_BOARD_IRQS 16
#define NR_IRQS (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */

8
arch/arm/plat-mxc/include/mach/memory.h
View File

@ -11,6 +11,12 @@
#ifndef __ASM_ARCH_MXC_MEMORY_H__
#define __ASM_ARCH_MXC_MEMORY_H__
#include <mach/hardware.h>
#if defined CONFIG_ARCH_MX1
#define PHYS_OFFSET UL(0x08000000)
#elif defined CONFIG_ARCH_MX2
#define PHYS_OFFSET UL(0xA0000000)
#elif defined CONFIG_ARCH_MX3
#define PHYS_OFFSET UL(0x80000000)
#endif
#endif /* __ASM_ARCH_MXC_MEMORY_H__ */

11
arch/arm/plat-mxc/include/mach/mx1.h
View File

@ -18,13 +18,6 @@
#include <mach/vmalloc.h>
/*
* defines the hardware clock tick rate
*/
#define CLOCK_TICK_RATE 16000000
#define PHYS_OFFSET UL(0x08000000)
/*
* Memory map
*/
@ -145,10 +138,6 @@
#define GPIO_INT_PORTD 62
#define WDT_INT 63
#define MXC_MAX_INT_LINES 64
#define NR_IRQS 256
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x1C
#define GPIO_GDIR 0x00

12
arch/arm/plat-mxc/include/mach/mx27.h
View File

@ -289,16 +289,4 @@ extern int mx27_revision(void);
/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
#define ARCH_NR_GPIOS (192 + 16)
/* OS clock tick rate */
#define CLOCK_TICK_RATE 13300000
/* Start of RAM */
#define PHYS_OFFSET SDRAM_BASE_ADDR
/* max interrupt lines count */
#define NR_IRQS 256
/* count of internal interrupt sources */
#define MXC_MAX_INT_LINES 64
#endif /* __ASM_ARCH_MXC_MX27_H__ */

25
arch/arm/plat-mxc/include/mach/mx31.h
View File

@ -15,11 +15,6 @@
#error "Do not include directly."
#endif
/*!
* defines the hardware clock tick rate
*/
#define CLOCK_TICK_RATE 16625000
/*
* MX31 memory map:
*
@ -244,9 +239,6 @@
#define PCMCIA_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
#define PHYS_OFFSET CSD0_BASE_ADDR
/*
* Interrupt numbers
*/
@ -315,23 +307,6 @@
#define MXC_INT_EXT_WDOG 62
#define MXC_INT_EXT_TV 63
#define MXC_MAX_INT_LINES 64
#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
#define MXC_MAX_VIRTUAL_INTS 16
#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
/*!
* Number of GPIO port as defined in the IC Spec
*/
#define GPIO_PORT_NUM 3
/*!
* Number of GPIO pins per port
*/
#define GPIO_NUM_PIN 32
#define PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */

8
arch/arm/plat-mxc/include/mach/timex.h
View File

@ -20,6 +20,12 @@
#ifndef __ASM_ARCH_MXC_TIMEX_H__
#define __ASM_ARCH_MXC_TIMEX_H__
#include <mach/hardware.h> /* for CLOCK_TICK_RATE */
#if defined CONFIG_ARCH_MX1
#define CLOCK_TICK_RATE 16000000
#elif defined CONFIG_ARCH_MX2
#define CLOCK_TICK_RATE 13300000
#elif defined CONFIG_ARCH_MX3
#define CLOCK_TICK_RATE 16625000
#endif
#endif /* __ASM_ARCH_MXC_TIMEX_H__ */

9
arch/arm/plat-mxc/irq.c
View File

@ -22,6 +22,7 @@
#include <linux/io.h>
#include <mach/common.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
@ -72,14 +73,14 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{
unsigned int irqt;
if (irq >= MXC_MAX_INT_LINES)
if (irq >= MXC_INTERNAL_IRQS)
return -EINVAL;
if (irq < MXC_MAX_INT_LINES / 2) {
if (irq < MXC_INTERNAL_IRQS / 2) {
irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
} else {
irq -= MXC_MAX_INT_LINES / 2;
irq -= MXC_INTERNAL_IRQS / 2;
irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
}
@ -129,7 +130,7 @@ void __init mxc_init_irq(void)
/* all IRQ no FIQ */
__raw_writel(0, AVIC_INTTYPEH);
__raw_writel(0, AVIC_INTTYPEL);
for (i = 0; i < MXC_MAX_INT_LINES; i++) {
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_avic_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);

2
drivers/serial/imx.c
View File

@ -191,7 +191,7 @@
#define SERIAL_IMX_MAJOR 207
#define MINOR_START 16
#define DEV_NAME "ttymxc"
#define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES
#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
#endif
/*