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net/mlx5e: Mutually exclude RX-FCS and RX-port-timestamp

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Due to current HW arch limitations, RX-FCS (scattering FCS frame field
to software) and RX-port-timestamp (improved timestamp accuracy on the
receive side) can't work together.
RX-port-timestamp is not controlled by the user and it is enabled by
default when supported by the HW/FW.
This patch sets RX-port-timestamp opposite to RX-FCS configuration.

Fixes: 102722fc68 ("net/mlx5e: Add support for RXFCS feature flag")
Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Aya Levin 2021-09-26 17:55:41 +03:00 committed by Saeed Mahameed
parent b2107cdc43
commit 0bc73ad46a
2 changed files with 60 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
View File

@ -3325,20 +3325,67 @@ static int set_feature_rx_all(struct net_device *netdev, bool enable)
return mlx5_set_port_fcs(mdev, !enable); return mlx5_set_port_fcs(mdev, !enable);
} }
static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
{
u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
bool supported, curr_state;
int err;
if (!MLX5_CAP_GEN(mdev, ports_check))
return 0;
err = mlx5_query_ports_check(mdev, in, sizeof(in));
if (err)
return err;
supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
if (!supported || enable == curr_state)
return 0;
MLX5_SET(pcmr_reg, in, local_port, 1);
MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
return mlx5_set_ports_check(mdev, in, sizeof(in));
}
static int set_feature_rx_fcs(struct net_device *netdev, bool enable) static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
{ {
struct mlx5e_priv *priv = netdev_priv(netdev); struct mlx5e_priv *priv = netdev_priv(netdev);
struct mlx5e_channels *chs = &priv->channels;
struct mlx5_core_dev *mdev = priv->mdev;
int err; int err;
mutex_lock(&priv->state_lock); mutex_lock(&priv->state_lock);
priv->channels.params.scatter_fcs_en = enable; if (enable) {
err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); err = mlx5e_set_rx_port_ts(mdev, false);
if (err) if (err)
priv->channels.params.scatter_fcs_en = !enable; goto out;
chs->params.scatter_fcs_en = true;
err = mlx5e_modify_channels_scatter_fcs(chs, true);
if (err) {
chs->params.scatter_fcs_en = false;
mlx5e_set_rx_port_ts(mdev, true);
}
} else {
chs->params.scatter_fcs_en = false;
err = mlx5e_modify_channels_scatter_fcs(chs, false);
if (err) {
chs->params.scatter_fcs_en = true;
goto out;
}
err = mlx5e_set_rx_port_ts(mdev, true);
if (err) {
mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
err = 0;
}
}
out:
mutex_unlock(&priv->state_lock); mutex_unlock(&priv->state_lock);
return err; return err;
} }

10
include/linux/mlx5/mlx5_ifc.h
View File

@ -9475,16 +9475,22 @@ struct mlx5_ifc_pcmr_reg_bits {
u8 reserved_at_0[0x8]; u8 reserved_at_0[0x8];
u8 local_port[0x8]; u8 local_port[0x8];
u8 reserved_at_10[0x10]; u8 reserved_at_10[0x10];
u8 entropy_force_cap[0x1]; u8 entropy_force_cap[0x1];
u8 entropy_calc_cap[0x1]; u8 entropy_calc_cap[0x1];
u8 entropy_gre_calc_cap[0x1]; u8 entropy_gre_calc_cap[0x1];
u8 reserved_at_23[0x1b]; u8 reserved_at_23[0xf];
u8 rx_ts_over_crc_cap[0x1];
u8 reserved_at_33[0xb];
u8 fcs_cap[0x1]; u8 fcs_cap[0x1];
u8 reserved_at_3f[0x1]; u8 reserved_at_3f[0x1];
u8 entropy_force[0x1]; u8 entropy_force[0x1];
u8 entropy_calc[0x1]; u8 entropy_calc[0x1];
u8 entropy_gre_calc[0x1]; u8 entropy_gre_calc[0x1];
u8 reserved_at_43[0x1b]; u8 reserved_at_43[0xf];
u8 rx_ts_over_crc[0x1];
u8 reserved_at_53[0xb];
u8 fcs_chk[0x1]; u8 fcs_chk[0x1];
u8 reserved_at_5f[0x1]; u8 reserved_at_5f[0x1];
}; };