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bpf/tests: Add tests to check source register zero-extension
This patch adds tests to check that the source register is preserved when zero-extending a 32-bit value. In particular, it checks that the source operand is not zero-extended in-place. Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20211001130348.3670534-5-johan.almbladh@anyfinetworks.com
This commit is contained in:
Johan Almbladh
Daniel Borkmann
parent
f68e8efd7f
commit
0bbaa02b48
143
lib/test_bpf.c
143
lib/test_bpf.c
@ -10586,6 +10586,149 @@ static struct bpf_test tests[] = {
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{},
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{ { 0, 2 } },
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},
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/* Checking that ALU32 src is not zero extended in place */
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#define BPF_ALU32_SRC_ZEXT(op) \
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{ \
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"ALU32_" #op "_X: src preserved in zext", \
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.u.insns_int = { \
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BPF_LD_IMM64(R1, 0x0123456789acbdefULL),\
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BPF_LD_IMM64(R2, 0xfedcba9876543210ULL),\
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BPF_ALU64_REG(BPF_MOV, R0, R1), \
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BPF_ALU32_REG(BPF_##op, R2, R1), \
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BPF_ALU64_REG(BPF_SUB, R0, R1), \
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BPF_ALU64_REG(BPF_MOV, R1, R0), \
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BPF_ALU64_IMM(BPF_RSH, R1, 32), \
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BPF_ALU64_REG(BPF_OR, R0, R1), \
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BPF_EXIT_INSN(), \
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}, \
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INTERNAL, \
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{ }, \
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{ { 0, 0 } }, \
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}
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BPF_ALU32_SRC_ZEXT(MOV),
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BPF_ALU32_SRC_ZEXT(AND),
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BPF_ALU32_SRC_ZEXT(OR),
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BPF_ALU32_SRC_ZEXT(XOR),
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BPF_ALU32_SRC_ZEXT(ADD),
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BPF_ALU32_SRC_ZEXT(SUB),
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BPF_ALU32_SRC_ZEXT(MUL),
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BPF_ALU32_SRC_ZEXT(DIV),
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BPF_ALU32_SRC_ZEXT(MOD),
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#undef BPF_ALU32_SRC_ZEXT
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/* Checking that ATOMIC32 src is not zero extended in place */
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#define BPF_ATOMIC32_SRC_ZEXT(op) \
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{ \
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"ATOMIC_W_" #op ": src preserved in zext", \
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.u.insns_int = { \
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BPF_LD_IMM64(R0, 0x0123456789acbdefULL), \
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BPF_ALU64_REG(BPF_MOV, R1, R0), \
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BPF_ST_MEM(BPF_W, R10, -4, 0), \
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BPF_ATOMIC_OP(BPF_W, BPF_##op, R10, R1, -4), \
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BPF_ALU64_REG(BPF_SUB, R0, R1), \
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BPF_ALU64_REG(BPF_MOV, R1, R0), \
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BPF_ALU64_IMM(BPF_RSH, R1, 32), \
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BPF_ALU64_REG(BPF_OR, R0, R1), \
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BPF_EXIT_INSN(), \
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}, \
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INTERNAL, \
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{ }, \
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{ { 0, 0 } }, \
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.stack_depth = 8, \
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}
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BPF_ATOMIC32_SRC_ZEXT(ADD),
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BPF_ATOMIC32_SRC_ZEXT(AND),
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BPF_ATOMIC32_SRC_ZEXT(OR),
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BPF_ATOMIC32_SRC_ZEXT(XOR),
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#undef BPF_ATOMIC32_SRC_ZEXT
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/* Checking that CMPXCHG32 src is not zero extended in place */
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{
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"ATOMIC_W_CMPXCHG: src preserved in zext",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0x0123456789acbdefULL),
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BPF_ALU64_REG(BPF_MOV, R2, R1),
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BPF_ALU64_REG(BPF_MOV, R0, 0),
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BPF_ST_MEM(BPF_W, R10, -4, 0),
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BPF_ATOMIC_OP(BPF_W, BPF_CMPXCHG, R10, R1, -4),
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BPF_ALU64_REG(BPF_SUB, R1, R2),
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BPF_ALU64_REG(BPF_MOV, R2, R1),
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BPF_ALU64_IMM(BPF_RSH, R2, 32),
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BPF_ALU64_REG(BPF_OR, R1, R2),
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BPF_ALU64_REG(BPF_MOV, R0, R1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0 } },
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.stack_depth = 8,
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},
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/* Checking that JMP32 immediate src is not zero extended in place */
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#define BPF_JMP32_IMM_ZEXT(op) \
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{ \
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"JMP32_" #op "_K: operand preserved in zext", \
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.u.insns_int = { \
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BPF_LD_IMM64(R0, 0x0123456789acbdefULL),\
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BPF_ALU64_REG(BPF_MOV, R1, R0), \
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BPF_JMP32_IMM(BPF_##op, R0, 1234, 1), \
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BPF_JMP_A(0), /* Nop */ \
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BPF_ALU64_REG(BPF_SUB, R0, R1), \
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BPF_ALU64_REG(BPF_MOV, R1, R0), \
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BPF_ALU64_IMM(BPF_RSH, R1, 32), \
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BPF_ALU64_REG(BPF_OR, R0, R1), \
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BPF_EXIT_INSN(), \
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}, \
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INTERNAL, \
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{ }, \
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{ { 0, 0 } }, \
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}
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BPF_JMP32_IMM_ZEXT(JEQ),
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BPF_JMP32_IMM_ZEXT(JNE),
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BPF_JMP32_IMM_ZEXT(JSET),
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BPF_JMP32_IMM_ZEXT(JGT),
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BPF_JMP32_IMM_ZEXT(JGE),
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BPF_JMP32_IMM_ZEXT(JLT),
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BPF_JMP32_IMM_ZEXT(JLE),
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BPF_JMP32_IMM_ZEXT(JSGT),
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BPF_JMP32_IMM_ZEXT(JSGE),
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BPF_JMP32_IMM_ZEXT(JSGT),
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BPF_JMP32_IMM_ZEXT(JSLT),
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BPF_JMP32_IMM_ZEXT(JSLE),
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#undef BPF_JMP2_IMM_ZEXT
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/* Checking that JMP32 dst & src are not zero extended in place */
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#define BPF_JMP32_REG_ZEXT(op) \
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{ \
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"JMP32_" #op "_X: operands preserved in zext", \
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.u.insns_int = { \
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BPF_LD_IMM64(R0, 0x0123456789acbdefULL),\
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BPF_LD_IMM64(R1, 0xfedcba9876543210ULL),\
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BPF_ALU64_REG(BPF_MOV, R2, R0), \
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BPF_ALU64_REG(BPF_MOV, R3, R1), \
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BPF_JMP32_IMM(BPF_##op, R0, R1, 1), \
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BPF_JMP_A(0), /* Nop */ \
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BPF_ALU64_REG(BPF_SUB, R0, R2), \
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BPF_ALU64_REG(BPF_SUB, R1, R3), \
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BPF_ALU64_REG(BPF_OR, R0, R1), \
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BPF_ALU64_REG(BPF_MOV, R1, R0), \
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BPF_ALU64_IMM(BPF_RSH, R1, 32), \
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BPF_ALU64_REG(BPF_OR, R0, R1), \
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BPF_EXIT_INSN(), \
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}, \
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INTERNAL, \
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{ }, \
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{ { 0, 0 } }, \
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}
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BPF_JMP32_REG_ZEXT(JEQ),
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BPF_JMP32_REG_ZEXT(JNE),
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BPF_JMP32_REG_ZEXT(JSET),
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BPF_JMP32_REG_ZEXT(JGT),
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BPF_JMP32_REG_ZEXT(JGE),
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BPF_JMP32_REG_ZEXT(JLT),
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BPF_JMP32_REG_ZEXT(JLE),
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BPF_JMP32_REG_ZEXT(JSGT),
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BPF_JMP32_REG_ZEXT(JSGE),
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BPF_JMP32_REG_ZEXT(JSGT),
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BPF_JMP32_REG_ZEXT(JSLT),
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BPF_JMP32_REG_ZEXT(JSLE),
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#undef BPF_JMP2_REG_ZEXT
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/* Exhaustive test of ALU64 shift operations */
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{
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"ALU64_LSH_K: all shift values",
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