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arm64/sysreg: Convert ID_AA64MMFR0_EL1 to automatic generation

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Automatically generate most of the defines for ID_AA64MMFR0_EL1 mostly as
per DDI0487H.a. Due to the large amount of MixedCase in this register which
isn't really consistent with either the kernel style or the majority of the
architecture the use of upper case is preserved. We also leave in place a
number of min/max/default value definitions which don't flow from the
architecture definitions.

No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-22-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Mark Brown 2022-09-05 23:54:18 +01:00 committed by Catalin Marinas
parent cfaa32108a
commit 0b7ed4d8f5
2 changed files with 73 additions and 30 deletions
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30
arch/arm64/include/asm/sysreg.h
View File

@ -199,7 +199,6 @@
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
@ -731,42 +730,13 @@
#define ID_AA64PFR1_EL1_MTE_MTE3 0x3
/* id_aa64mmfr0 */
#define ID_AA64MMFR0_EL1_ECV_SHIFT 60
#define ID_AA64MMFR0_EL1_FGT_SHIFT 56
#define ID_AA64MMFR0_EL1_EXS_SHIFT 44
#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
#define ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
#define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
#define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
#define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
#define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
#define ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
#define ID_AA64MMFR0_EL1_ASIDBITS_8 0x0
#define ID_AA64MMFR0_EL1_ASIDBITS_16 0x2
#define ID_AA64MMFR0_EL1_TGRAN4_NI 0xf
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
#define ID_AA64MMFR0_EL1_TGRAN64_NI 0xf
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
#define ID_AA64MMFR0_EL1_TGRAN16_NI 0x0
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
#define ID_AA64MMFR0_EL1_PARANGE_32 0x0
#define ID_AA64MMFR0_EL1_PARANGE_36 0x1
#define ID_AA64MMFR0_EL1_PARANGE_40 0x2
#define ID_AA64MMFR0_EL1_PARANGE_42 0x3
#define ID_AA64MMFR0_EL1_PARANGE_44 0x4
#define ID_AA64MMFR0_EL1_PARANGE_48 0x5
#define ID_AA64MMFR0_EL1_PARANGE_52 0x6
#define ARM64_MIN_PARANGE_BITS 32
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0

73
arch/arm64/tools/sysreg
View File

@ -315,6 +315,79 @@ Enum 3:0 WFxT
EndEnum
EndSysreg
Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0
Enum 63:60 ECV
0b0000 NI
0b0001 IMP
0b0010 CNTPOFF
EndEnum
Enum 59:56 FGT
0b0000 NI
0b0001 IMP
EndEnum
Res0 55:48
Enum 47:44 EXS
0b0000 NI
0b0001 IMP
EndEnum
Enum 43:40 TGRAN4_2
0b0000 TGRAN4
0b0001 NI
0b0010 IMP
0b0011 52_BIT
EndEnum
Enum 39:36 TGRAN64_2
0b0000 TGRAN64
0b0001 NI
0b0010 IMP
EndEnum
Enum 35:32 TGRAN16_2
0b0000 TGRAN16
0b0001 NI
0b0010 IMP
0b0011 52_BIT
EndEnum
Enum 31:28 TGRAN4
0b0000 IMP
0b0001 52_BIT
0b1111 NI
EndEnum
Enum 27:24 TGRAN64
0b0000 IMP
0b1111 NI
EndEnum
Enum 23:20 TGRAN16
0b0000 NI
0b0001 IMP
0b0010 52_BIT
EndEnum
Enum 19:16 BIGENDEL0
0b0000 NI
0b0001 IMP
EndEnum
Enum 15:12 SNSMEM
0b0000 NI
0b0001 IMP
EndEnum
Enum 11:8 BIGEND
0b0000 NI
0b0001 IMP
EndEnum
Enum 7:4 ASIDBITS
0b0000 8
0b0010 16
EndEnum
Enum 3:0 PARANGE
0b0000 32
0b0001 36
0b0010 40
0b0011 42
0b0100 44
0b0101 48
0b0110 52
EndEnum
EndSysreg
Sysreg SCTLR_EL1 3 0 1 0 0
Field 63 TIDCP
Field 62 SPINMASK