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powerpc: Enforce usage of R0-R31 where possible
Enforce the use of R0-R31 in macros where possible now we have all the fixes in. R0-R31 macros are removed here so that can't be used anymore. They should not be defined anywhere. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Michael Neuling
Benjamin Herrenschmidt
parent
0972def44f
commit
0b7673c35e
@ -15,39 +15,6 @@
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#include <linux/stringify.h>
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#include <asm/asm-compat.h>
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#define R0 0
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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#define R16 16
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#define R17 17
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#define R18 18
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#define R19 19
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#define R20 20
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#define R21 21
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#define R22 22
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#define R23 23
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#define R24 24
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#define R25 25
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#define R26 26
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#define R27 27
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#define R28 28
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#define R29 29
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#define R30 30
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#define R31 31
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#define __REG_R0 0
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#define __REG_R1 1
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#define __REG_R2 2
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@ -181,10 +148,10 @@
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#define ___PPC_RB(b) (((b) & 0x1f) << 11)
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#define ___PPC_RS(s) (((s) & 0x1f) << 21)
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#define ___PPC_RT(t) ___PPC_RS(t)
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#define __PPC_RA(a) (((a) & 0x1f) << 16)
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#define __PPC_RB(b) (((b) & 0x1f) << 11)
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#define __PPC_RS(s) (((s) & 0x1f) << 21)
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#define __PPC_RT(s) __PPC_RS(s)
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#define __PPC_RA(a) ___PPC_RA(__REG_##a)
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#define __PPC_RB(b) ___PPC_RB(__REG_##b)
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#define __PPC_RS(s) ___PPC_RS(__REG_##s)
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#define __PPC_RT(t) ___PPC_RT(__REG_##t)
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#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
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#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
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#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
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@ -126,26 +126,26 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
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/* Save the lower 32 VSRs in the thread VSR region */
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#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b)
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#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b)
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#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
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#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
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#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
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#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
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#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
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#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
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#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b)
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#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
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#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
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#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
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#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
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#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
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/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
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#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b)
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#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b)
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#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
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#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
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#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
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#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
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#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
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#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
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#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
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#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
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#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
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#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
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@ -183,15 +183,18 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
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#else
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#define ULONG_SIZE 4
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#endif
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#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
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#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
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#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC64
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#define STACKFRAMESIZE 256
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#define STK_REG(i) (112 + ((i)-14)*8)
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#define __STK_REG(i) (112 + ((i)-14)*8)
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#define STK_REG(i) __STK_REG(__REG_##i)
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#define STK_PARAM(i) (48 + ((i)-3)*8)
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#define __STK_PARAM(i) (48 + ((i)-3)*8)
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#define STK_PARAM(i) __STK_PARAM(__REG_##i)
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#define XGLUE(a,b) a##b
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#define GLUE(a,b) XGLUE(a,b)
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@ -26,7 +26,7 @@
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#include <asm/ptrace.h>
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#ifdef CONFIG_VSX
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#define REST_32FPVSRS(n,c,base) \
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#define __REST_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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@ -35,7 +35,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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2: REST_32VSRS(n,c,base); \
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3:
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#define SAVE_32FPVSRS(n,c,base) \
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#define __SAVE_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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@ -44,9 +44,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#endif
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#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
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#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
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/*
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* This task wants to use the FPU now.
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@ -79,7 +81,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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beq 1f
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toreal(r4)
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addi r4,r4,THREAD /* want last_task_used_math->thread */
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SAVE_32FPVSRS(0, r5, r4)
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SAVE_32FPVSRS(0, R5, R4)
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mffs fr0
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stfd fr0,THREAD_FPSCR(r4)
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PPC_LL r5,PT_REGS(r4)
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@ -34,7 +34,8 @@
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#define HOST_R2 12
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#define HOST_CR 16
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#define HOST_NV_GPRS 20
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#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4))
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#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4))
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#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n)
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#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + 4)
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#define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */
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#define HOST_STACK_LR (HOST_STACK_SIZE + 4) /* In caller stack frame. */
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