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Renesas ARM DT updates for v5.10 (take two)

Browse Source 
- PCIe endpoint support for the RZ/G2H SoC,
   - SATA support for the HopeRun HiHope RZ/G2H board,
   - Increase support (CAN, LED, SPI NOR, VIN, VSP) for the RZ/G1H SoC on
     the iWave Qseven board (G21D), and its camera add-on board,
   - Initial support for the R-Car V3U SoC on the Falcon CPU and BreakOut
     boards,
   - HDMI display and sound support for the R-Car M3-W+ SoC on the
     Salvator-XS board,
   - Digital Radio Interface (DRIF) support for the R-Car E3 SoC,
   - Minor fixes and cleanups.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCX2SkmQAKCRCKwlD9ZEnx
 cIXNAP0XqvKJP7xGjQ1ORyePB1nWZtebVqGoQFxpvqwznMNZlAD7BIRlATo4LYpu
 LNMya5sk85WAhZNbpkHwR++3/8m+mgE=
 =Va2A
 -----END PGP SIGNATURE-----

Merge tag 'renesas-arm-dt-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.10 (take two)

  - PCIe endpoint support for the RZ/G2H SoC,
  - SATA support for the HopeRun HiHope RZ/G2H board,
  - Increase support (CAN, LED, SPI NOR, VIN, VSP) for the RZ/G1H SoC on
    the iWave Qseven board (G21D), and its camera add-on board,
  - Initial support for the R-Car V3U SoC on the Falcon CPU and BreakOut
    boards,
  - HDMI display and sound support for the R-Car M3-W+ SoC on the
    Salvator-XS board,
  - Digital Radio Interface (DRIF) support for the R-Car E3 SoC,
  - Minor fixes and cleanups.

* tag 'renesas-arm-dt-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (24 commits)
  arm64: dts: renesas: r8a774c0: Fix MSIOF1 DMA channels
  arm64: dts: renesas: r8a77990: Fix MSIOF1 DMA channels
  arm64: dts: renesas: r8a77990: Add DRIF support
  ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add can0 support to camera DB
  ARM: dts: r8a7742: Add VSP support
  arm64: dts: renesas: Drop superfluous pin configuration containers
  arm64: dts: renesas: r8a77961: salvator-xs: Add HDMI Sound support
  arm64: dts: renesas: r8a77961: salvator-xs: Add HDMI Display support
  arm64: dts: renesas: r8a77961: Add HDMI device nodes
  arm64: dts: renesas: r8a77961: Add DU device nodes
  arm64: dts: renesas: r8a77961: Add VSP device nodes
  arm64: dts: renesas: r8a77961: Add FCP device nodes
  arm64: dts: renesas: Fix pin controller node names
  ARM: dts: renesas: Fix pin controller node names
  arm64: dts: renesas: Add Renesas Falcon boards support
  arm64: dts: renesas: Add Renesas R8A779A0 SoC support
  ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication
  ARM: dts: r8a7742-iwg21d-q7: Add can1 support to carrier board
  ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support
  ARM: dts: r8a7742: Add VIN DT nodes
  ...

Link: https://lore.kernel.org/r/20200918124800.15555-2-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-09-26 09:59:24 -07:00
commit 0b69d912b3
43 changed files with 859 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/emev2.dtsi
View File

@ -195,7 +195,7 @@
clock-names = "sclk";
};
pfc: pin-controller@e0140200 {
pfc: pinctrl@e0140200 {
compatible = "renesas,pfc-emev2";
reg = <0xe0140200 0x100>;
};

2
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -499,7 +499,7 @@
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
pinctrl: pin-controller@fcfe3000 {
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;

2
arch/arm/boot/dts/r7s9210.dtsi
View File

@ -489,7 +489,7 @@
interrupt-map-mask = <7 0>;
};
pinctrl: pin-controller@fcffe000 {
pinctrl: pinctrl@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;

2
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -221,7 +221,7 @@
power-domains = <&pd_c4>;
};
pfc: pin-controller@e6050000 {
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a73a4";
reg = <0 0xe6050000 0 0x9000>;
gpio-controller;

2
arch/arm/boot/dts/r8a7740.dtsi
View File

@ -311,7 +311,7 @@
status = "disabled";
};
pfc: pin-controller@e6050000 {
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;

11
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
View File

@ -27,6 +27,12 @@
status = "disabled";
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&ether {
pinctrl-0 = <&ether_pins>;
pinctrl-names = "default";
@ -49,6 +55,11 @@
};
&pfc {
can0_pins: can0 {
groups = "can0_data_d";
function = "can0";
};
ether_pins: ether {
groups = "eth_mdio", "eth_rmii";
function = "eth";

62
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
View File

@ -52,6 +52,16 @@
clock-frequency = <26000000>;
};
leds {
compatible = "gpio-leds";
sdhi2_led {
label = "sdio-led";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
};
};
reg_1p5v: 1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
@ -131,16 +141,58 @@
};
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cmt0 {
status = "okay";
};
&gpio1 {
can-trx-en-gpio{
gpio-hog;
gpios = <28 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can-trx-en-gpio";
};
};
&hsusb {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
status = "okay";
};
&msiof0 {
pinctrl-0 = <&msiof0_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
flash1: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "user";
reg = <0x00000000 0x00200000>;
};
};
};
};
&pci0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
@ -177,11 +229,21 @@
function = "avb";
};
can1_pins: can1 {
groups = "can1_data_b";
function = "can1";
};
i2c2_pins: i2c2 {
groups = "i2c2_b";
function = "i2c2";
};
msiof0_pins: msiof0 {
groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx";
function = "msiof0";
};
scifa2_pins: scifa2 {
groups = "scifa2_data_c";
function = "scifa2";

82
arch/arm/boot/dts/r8a7742.dtsi
View File

@ -338,7 +338,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7742";
reg = <0 0xe6060000 0 0x250>;
};
@ -1103,6 +1103,50 @@
status = "disabled";
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7742",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 811>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7742",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 810>;
status = "disabled";
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7742",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 809>;
status = "disabled";
};
vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a7742",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 808>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 808>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
@ -1642,6 +1686,42 @@
status = "disabled";
};
vsp@fe920000 {
compatible = "renesas,vsp1";
reg = <0 0xfe920000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 130>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 130>;
};
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 131>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 131>;
};
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 128>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 128>;
};
vsp@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 127>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 127>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a7742";
reg = <0 0xfeb00000 0 0x70000>;

2
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -265,7 +265,7 @@
resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7743";
reg = <0 0xe6060000 0 0x250>;
};

2
arch/arm/boot/dts/r8a7744.dtsi
View File

@ -265,7 +265,7 @@
resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7744";
reg = <0 0xe6060000 0 0x250>;
};

2
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -230,7 +230,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7745";
reg = <0 0xe6060000 0 0x11c>;
};

2
arch/arm/boot/dts/r8a77470.dtsi
View File

@ -187,7 +187,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77470";
reg = <0 0xe6060000 0 0x118>;
};

2
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -142,7 +142,7 @@
interrupt-controller;
};
pfc: pin-controller@fffc0000 {
pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7778";
reg = <0xfffc0000 0x118>;
};

2
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -321,7 +321,7 @@
status = "disabled";
};
pfc: pin-controller@fffc0000 {
pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;
};

2
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -363,7 +363,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7790";
reg = <0 0xe6060000 0 0x250>;
};

2
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -286,7 +286,7 @@
resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7791";
reg = <0 0xe6060000 0 0x250>;
};

2
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -296,7 +296,7 @@
resets = <&cpg 913>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7792";
reg = <0 0xe6060000 0 0x144>;
};

2
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -271,7 +271,7 @@
resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7793";
reg = <0 0xe6060000 0 0x250>;
};

2
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -238,7 +238,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7794";
reg = <0 0xe6060000 0 0x11c>;
};

2
arch/arm/boot/dts/r9a06g032.dtsi
View File

@ -165,7 +165,7 @@
status = "disabled";
};
pinctrl: pin-controller@40067000 {
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;

2
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -448,7 +448,7 @@
status = "disabled";
};
pfc: pin-controller@e6050000 {
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;

2
arch/arm64/boot/dts/renesas/Makefile
View File

@ -54,3 +54,5 @@ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb

2
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -408,7 +408,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774a1";
reg = <0 0xe6060000 0 0x50c>;
};

2
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -282,7 +282,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774b1";
reg = <0 0xe6060000 0 0x50c>;
};

7
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -256,7 +256,7 @@
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774c0";
reg = <0 0xe6060000 0 0x508>;
};
@ -1214,9 +1214,8 @@
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
dmas = <&dmac0 0x43>, <&dmac0 0x42>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;

5
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
View File

@ -13,3 +13,8 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
&sata {
status = "okay";
};

40
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -457,7 +457,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774e1";
reg = <0 0xe6060000 0 0x50c>;
};
@ -2468,6 +2468,44 @@
status = "disabled";
};
pciec0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a774e1-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xfe000000 0 0x80000>,
<0x0 0xfe100000 0 0x100000>,
<0x0 0xfe200000 0 0x200000>,
<0x0 0x30000000 0 0x8000000>,
<0x0 0x38000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
resets = <&cpg 319>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
status = "disabled";
};
pciec1_ep: pcie-ep@ee800000 {
compatible = "renesas,r8a774e1-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xee800000 0 0x80000>,
<0x0 0xee900000 0 0x100000>,
<0x0 0xeea00000 0 0x200000>,
<0x0 0xc0000000 0 0x8000000>,
<0x0 0xc8000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>;
clock-names = "pcie";
resets = <&cpg 318>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
status = "disabled";
};
vspbc: vsp@fe920000 {
compatible = "renesas,vsp2";
reg = <0 0xfe920000 0 0x8000>;

2
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -490,7 +490,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0 0xe6060000 0 0x50c>;
};

2
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -459,7 +459,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7796";
reg = <0 0xe6060000 0 0x50c>;
};

57
arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
View File

@ -29,3 +29,60 @@
reg = <0x6 0x00000000 0x1 0x00000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

134
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -448,7 +448,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77961";
reg = <0 0xe6060000 0 0x50c>;
};
@ -1932,6 +1932,113 @@
status = "disabled";
};
fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 615>;
};
fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 607>;
};
fcpvi0: fcp@fe9af000 {
compatible = "renesas,fcpv";
reg = <0 0xfe9af000 0 0x200>;
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 611>;
iommus = <&ipmmu_vc0 19>;
};
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
fcpvd2: fcp@fea37000 {
compatible = "renesas,fcpv";
reg = <0 0xfea37000 0 0x200>;
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 601>;
iommus = <&ipmmu_vi0 10>;
};
vspb: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x5000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 623>;
renesas,fcp = <&fcpvd0>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x5000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 622>;
renesas,fcp = <&fcpvd1>;
};
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x5000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 621>;
renesas,fcp = <&fcpvd2>;
};
vspi0: vsp@fe9a0000 {
compatible = "renesas,vsp2";
reg = <0 0xfe9a0000 0 0x8000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>;
power-domains = <&sysc R8A77961_PD_A3VC>;
resets = <&cpg 631>;
renesas,fcp = <&fcpvi0>;
};
csi20: csi2@fea80000 {
reg = <0 0xfea80000 0 0x10000>;
/* placeholder */
@ -1966,14 +2073,23 @@
};
hdmi0: hdmi@fead0000 {
compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
/* placeholder */
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 729>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
@ -1986,8 +2102,19 @@
};
du: display@feb00000 {
compatible = "renesas,du-r8a77961";
reg = <0 0xfeb00000 0 0x70000>;
/* placeholder */
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.2";
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
status = "disabled";
ports {
#address-cells = <1>;
@ -2001,6 +2128,7 @@
port@1 {
reg = <1>;
du_out_hdmi0: endpoint {
remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {

2
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -329,7 +329,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77965";
reg = <0 0xe6060000 0 0x50c>;
};

2
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -204,7 +204,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77970";
reg = <0 0xe6060000 0 0x504>;
};

2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -234,7 +234,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77980";
reg = <0 0xe6060000 0 0x50c>;
};

6
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View File

@ -520,10 +520,8 @@
&pfc {
avb_pins: avb {
mux {
groups = "avb_link", "avb_mii";
function = "avb";
};
groups = "avb_link", "avb_mii";
function = "avb";
};
canfd0_pins: canfd0 {

127
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -282,7 +282,7 @@
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;
};
@ -1192,9 +1192,8 @@
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
dmas = <&dmac0 0x43>, <&dmac0 0x42>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
@ -1288,6 +1287,126 @@
};
};
drif00: rif@e6f40000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x84>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 515>;
renesas,bonding = <&drif01>;
status = "disabled";
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x84>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled";
};
drif10: rif@e6f60000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x84>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x84>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
status = "disabled";
};
drif20: rif@e6f80000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f80000 0 0x84>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac0 0x28>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled";
};
drif21: rif@e6f90000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f90000 0 0x84>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac0 0x2a>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled";
};
drif30: rif@e6fa0000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fa0000 0 0x84>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac0 0x2c>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled";
};
drif31: rif@e6fb0000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fb0000 0 0x84>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac0 0x2e>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required

6
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
View File

@ -393,10 +393,8 @@
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
};
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
};
can0_pins: can0 {

2
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -188,7 +188,7 @@
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77995";
reg = <0 0xe6060000 0 0x508>;
};

46
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi Normal file
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@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a779a0.dtsi"
/ {
model = "Renesas Falcon CPU board";
compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x80000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&scif0 {
status = "okay";
};

22
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU and BreakOut boards
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779a0-falcon-cpu.dtsi"
/ {
model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

133
arch/arm64/boot/dts/renesas/r8a779a0.dtsi Normal file
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@ -0,0 +1,133 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car V3U (R8A779A0) SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779a0-sysc.h>
/ {
compatible = "renesas,r8a779a0";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76_0>;
};
L3_CA76_0: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A779A0_PD_A2E0D0>;
cache-unified;
cache-level = <3>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779a0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779a0-rst";
reg = <0 0xe6160000 0 0x4000>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a779a0-sysc";
reg = <0 0xe6180000 0 0x4000>;
#power-domain-cells = <1>;
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

55
include/dt-bindings/clock/r8a779a0-cpg-mssr.h Normal file
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@ -0,0 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779A0 CPG Core Clocks */
#define R8A779A0_CLK_Z0 0
#define R8A779A0_CLK_ZX 1
#define R8A779A0_CLK_Z1 2
#define R8A779A0_CLK_ZR 3
#define R8A779A0_CLK_ZS 4
#define R8A779A0_CLK_ZT 5
#define R8A779A0_CLK_ZTR 6
#define R8A779A0_CLK_S1D1 7
#define R8A779A0_CLK_S1D2 8
#define R8A779A0_CLK_S1D4 9
#define R8A779A0_CLK_S1D8 10
#define R8A779A0_CLK_S1D12 11
#define R8A779A0_CLK_S3D1 12
#define R8A779A0_CLK_S3D2 13
#define R8A779A0_CLK_S3D4 14
#define R8A779A0_CLK_LB 15
#define R8A779A0_CLK_CP 16
#define R8A779A0_CLK_CL 17
#define R8A779A0_CLK_CL16MCK 18
#define R8A779A0_CLK_ZB30 19
#define R8A779A0_CLK_ZB30D2 20
#define R8A779A0_CLK_ZB30D4 21
#define R8A779A0_CLK_ZB31 22
#define R8A779A0_CLK_ZB31D2 23
#define R8A779A0_CLK_ZB31D4 24
#define R8A779A0_CLK_SD0H 25
#define R8A779A0_CLK_SD0 26
#define R8A779A0_CLK_RPC 27
#define R8A779A0_CLK_RPCD2 28
#define R8A779A0_CLK_MSO 29
#define R8A779A0_CLK_CANFD 30
#define R8A779A0_CLK_CSI0 31
#define R8A779A0_CLK_FRAY 32
#define R8A779A0_CLK_DSI 33
#define R8A779A0_CLK_VIP 34
#define R8A779A0_CLK_ADGH 35
#define R8A779A0_CLK_CNNDSP 36
#define R8A779A0_CLK_ICU 37
#define R8A779A0_CLK_ICUD2 38
#define R8A779A0_CLK_VCBUS 39
#define R8A779A0_CLK_CBFUSA 40
#define R8A779A0_CLK_R 41
#define R8A779A0_CLK_OSC 42
#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */

59
include/dt-bindings/power/r8a779a0-sysc.h Normal file
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@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779A0_PD_A1E0D0C0 0
#define R8A779A0_PD_A1E0D0C1 1
#define R8A779A0_PD_A1E0D1C0 2
#define R8A779A0_PD_A1E0D1C1 3
#define R8A779A0_PD_A1E1D0C0 4
#define R8A779A0_PD_A1E1D0C1 5
#define R8A779A0_PD_A1E1D1C0 6
#define R8A779A0_PD_A1E1D1C1 7
#define R8A779A0_PD_A2E0D0 16
#define R8A779A0_PD_A2E0D1 17
#define R8A779A0_PD_A2E1D0 18
#define R8A779A0_PD_A2E1D1 19
#define R8A779A0_PD_A3E0 20
#define R8A779A0_PD_A3E1 21
#define R8A779A0_PD_3DG_A 24
#define R8A779A0_PD_3DG_B 25
#define R8A779A0_PD_A1CNN2 32
#define R8A779A0_PD_A1DSP0 33
#define R8A779A0_PD_A2IMP01 34
#define R8A779A0_PD_A2DP0 35
#define R8A779A0_PD_A2CV0 36
#define R8A779A0_PD_A2CV1 37
#define R8A779A0_PD_A2CV4 38
#define R8A779A0_PD_A2CV6 39
#define R8A779A0_PD_A2CN2 40
#define R8A779A0_PD_A1CNN0 41
#define R8A779A0_PD_A2CN0 42
#define R8A779A0_PD_A3IR 43
#define R8A779A0_PD_A1CNN1 44
#define R8A779A0_PD_A1DSP1 45
#define R8A779A0_PD_A2IMP23 46
#define R8A779A0_PD_A2DP1 47
#define R8A779A0_PD_A2CV2 48
#define R8A779A0_PD_A2CV3 49
#define R8A779A0_PD_A2CV5 50
#define R8A779A0_PD_A2CV7 51
#define R8A779A0_PD_A2CN1 52
#define R8A779A0_PD_A3VIP0 56
#define R8A779A0_PD_A3VIP1 57
#define R8A779A0_PD_A3VIP2 58
#define R8A779A0_PD_A3VIP3 59
#define R8A779A0_PD_A3ISP01 60
#define R8A779A0_PD_A3ISP23 61
/* Always-on power area */
#define R8A779A0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */