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dt-bindings: memory: convert Samsung Exynos DMC to dtschema
Convert Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory Controller to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Lukasz Luba <lukasz.luba@arm.com> Link: https://lore.kernel.org/r/20210820150353.161161-3-krzysztof.kozlowski@canonical.com Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Rob Herring
parent
c507f15231
commit
0b3813014c
@ -1,84 +0,0 @@
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* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
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The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
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memory chips are connected. The driver is to monitor the controller in runtime
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and switch frequency and voltage. To monitor the usage of the controller in
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runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
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is able to measure the current load of the memory.
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When 'userspace' governor is used for the driver, an application is able to
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switch the DMC and memory frequency.
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Required properties for DMC device for Exynos5422:
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- compatible: Should be "samsung,exynos5422-dmc".
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- clocks : list of clock specifiers, must contain an entry for each
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required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
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CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
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CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
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- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
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"fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
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"mout_mclk_cdrex" entries
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- devfreq-events : phandles for PPMU devices connected to this DMC.
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- vdd-supply : phandle for voltage regulator which is connected.
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- reg : registers of two CDREX controllers.
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- operating-points-v2 : phandle for OPPs described in v2 definition.
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- device-handle : phandle of the connected DRAM memory device. For more
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information please refer to documentation file:
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Documentation/devicetree/bindings/ddr/lpddr3.txt
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- devfreq-events : phandles of the PPMU events used by the controller.
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- samsung,syscon-clk : phandle of the clock register set used by the controller,
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these registers are used for enabling a 'pause' feature and are not
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exposed by clock framework but they must be used in a safe way.
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The register offsets are in the driver code and specyfic for this SoC
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type.
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Optional properties for DMC device for Exynos5422:
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- interrupt-parent : The parent interrupt controller.
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- interrupts : Contains the IRQ line numbers for the DMC internal performance
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event counters in DREX0 and DREX1 channels. Align with specification of the
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interrupt line(s) in the interrupt-parent controller.
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- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
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same as in the 'interrupts' list above.
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Example:
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ppmu_dmc0_0: ppmu@10d00000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x10d00000 0x2000>;
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clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
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clock-names = "ppmu";
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events {
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ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
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event-name = "ppmu-event3-dmc0_0";
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};
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};
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};
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dmc: memory-controller@10c20000 {
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compatible = "samsung,exynos5422-dmc";
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reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
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clocks = <&clock CLK_FOUT_SPLL>,
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<&clock CLK_MOUT_SCLK_SPLL>,
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<&clock CLK_FF_DOUT_SPLL2>,
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<&clock CLK_FOUT_BPLL>,
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<&clock CLK_MOUT_BPLL>,
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<&clock CLK_SCLK_BPLL>,
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<&clock CLK_MOUT_MX_MSPLL_CCORE>,
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<&clock CLK_MOUT_MCLK_CDREX>;
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clock-names = "fout_spll",
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"mout_sclk_spll",
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"ff_dout_spll2",
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"fout_bpll",
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"mout_bpll",
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"sclk_bpll",
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"mout_mx_mspll_ccore",
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"mout_mclk_cdrex";
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operating-points-v2 = <&dmc_opp_table>;
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devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
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<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
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device-handle = <&samsung_K3QF2F20DB>;
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vdd-supply = <&buck1_reg>;
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samsung,syscon-clk = <&clock>;
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interrupt-parent = <&combiner>;
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interrupts = <16 0>, <16 1>;
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interrupt-names = "drex_0", "drex_1";
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};
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@ -0,0 +1,137 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: |
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Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
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Controller device
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maintainers:
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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- Lukasz Luba <lukasz.luba@arm.com>
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description: |
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The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
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DRAM memory chips are connected. The driver is to monitor the controller in
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runtime and switch frequency and voltage. To monitor the usage of the
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controller in runtime, the driver uses the PPMU (Platform Performance
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Monitoring Unit), which is able to measure the current load of the memory.
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When 'userspace' governor is used for the driver, an application is able to
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switch the DMC and memory frequency.
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properties:
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compatible:
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items:
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- const: samsung,exynos5422-dmc
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clock-names:
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items:
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- const: fout_spll
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- const: mout_sclk_spll
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- const: ff_dout_spll2
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- const: fout_bpll
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- const: mout_bpll
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- const: sclk_bpll
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- const: mout_mx_mspll_ccore
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- const: mout_mclk_cdrex
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clocks:
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minItems: 8
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maxItems: 8
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devfreq-events:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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minItems: 1
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maxItems: 16
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description: phandles of the PPMU events used by the controller.
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device-handle:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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phandle of the connected DRAM memory device. For more information please
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refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
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operating-points-v2: true
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interrupts:
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items:
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- description: DMC internal performance event counters in DREX0
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- description: DMC internal performance event counters in DREX1
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interrupt-names:
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items:
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- const: drex_0
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- const: drex_1
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reg:
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items:
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- description: registers of DREX0
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- description: registers of DREX1
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samsung,syscon-clk:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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Phandle of the clock register set used by the controller, these registers
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are used for enabling a 'pause' feature and are not exposed by clock
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framework but they must be used in a safe way. The register offsets are
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in the driver code and specyfic for this SoC type.
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vdd-supply: true
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required:
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- compatible
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- clock-names
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- clocks
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- devfreq-events
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- device-handle
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- reg
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- samsung,syscon-clk
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5420.h>
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ppmu_dmc0_0: ppmu@10d00000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x10d00000 0x2000>;
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clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
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clock-names = "ppmu";
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events {
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ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
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event-name = "ppmu-event3-dmc0_0";
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};
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};
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};
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memory-controller@10c20000 {
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compatible = "samsung,exynos5422-dmc";
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reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
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clocks = <&clock CLK_FOUT_SPLL>,
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<&clock CLK_MOUT_SCLK_SPLL>,
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<&clock CLK_FF_DOUT_SPLL2>,
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<&clock CLK_FOUT_BPLL>,
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<&clock CLK_MOUT_BPLL>,
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<&clock CLK_SCLK_BPLL>,
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<&clock CLK_MOUT_MX_MSPLL_CCORE>,
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<&clock CLK_MOUT_MCLK_CDREX>;
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clock-names = "fout_spll",
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"mout_sclk_spll",
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"ff_dout_spll2",
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"fout_bpll",
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"mout_bpll",
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"sclk_bpll",
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"mout_mx_mspll_ccore",
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"mout_mclk_cdrex";
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operating-points-v2 = <&dmc_opp_table>;
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devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
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<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
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device-handle = <&samsung_K3QF2F20DB>;
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vdd-supply = <&buck1_reg>;
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samsung,syscon-clk = <&clock>;
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interrupt-parent = <&combiner>;
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interrupts = <16 0>, <16 1>;
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interrupt-names = "drex_0", "drex_1";
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};
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@ -5569,7 +5569,7 @@ M: Lukasz Luba <lukasz.luba@arm.com>
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L: linux-pm@vger.kernel.org
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L: linux-samsung-soc@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
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F: Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
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F: drivers/memory/samsung/exynos5422-dmc.c
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DME1737 HARDWARE MONITOR DRIVER
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