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ptp_ocp: implement DPLL ops
Implement basic DPLL operations in ptp_ocp driver as the simplest example of using new subsystem. Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vadim Fedorenko
David S. Miller
parent
d7999f5ea6
commit
09eeb3aecc
@ -188,6 +188,7 @@ config PTP_1588_CLOCK_OCP
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depends on COMMON_CLK
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select NET_DEVLINK
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select CRC16
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select DPLL
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help
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This driver adds support for an OpenCompute time card.
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@ -23,6 +23,7 @@
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#include <linux/mtd/mtd.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/crc16.h>
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#include <linux/dpll.h>
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#define PCI_VENDOR_ID_FACEBOOK 0x1d9b
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#define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
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@ -260,12 +261,21 @@ enum ptp_ocp_sma_mode {
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SMA_MODE_OUT,
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};
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static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
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DPLL_PIN_FREQUENCY_1PPS,
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DPLL_PIN_FREQUENCY_10MHZ,
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DPLL_PIN_FREQUENCY_IRIG_B,
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DPLL_PIN_FREQUENCY_DCF77,
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};
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struct ptp_ocp_sma_connector {
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enum ptp_ocp_sma_mode mode;
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bool fixed_fcn;
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bool fixed_dir;
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bool disabled;
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u8 default_fcn;
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struct dpll_pin *dpll_pin;
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struct dpll_pin_properties dpll_prop;
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};
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struct ocp_attr_group {
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@ -294,6 +304,7 @@ struct ptp_ocp_serial_port {
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#define OCP_BOARD_ID_LEN 13
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#define OCP_SERIAL_LEN 6
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#define OCP_SMA_NUM 4
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struct ptp_ocp {
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struct pci_dev *pdev;
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@ -331,7 +342,9 @@ struct ptp_ocp {
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const struct attribute_group **attr_group;
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const struct ptp_ocp_eeprom_map *eeprom_map;
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struct dentry *debug_root;
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bool sync;
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time64_t gnss_lost;
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struct delayed_work sync_work;
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int id;
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int n_irqs;
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struct ptp_ocp_serial_port gnss_port;
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@ -350,8 +363,9 @@ struct ptp_ocp {
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u32 ts_window_adjust;
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u64 fw_cap;
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struct ptp_ocp_signal signal[4];
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struct ptp_ocp_sma_connector sma[4];
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struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
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const struct ocp_sma_op *sma_op;
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struct dpll_device *dpll;
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};
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#define OCP_REQ_TIMESTAMP BIT(0)
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@ -835,6 +849,7 @@ static DEFINE_IDR(ptp_ocp_idr);
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struct ocp_selector {
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const char *name;
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int value;
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u64 frequency;
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};
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static const struct ocp_selector ptp_ocp_clock[] = {
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@ -855,31 +870,31 @@ static const struct ocp_selector ptp_ocp_clock[] = {
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#define SMA_SELECT_MASK GENMASK(14, 0)
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static const struct ocp_selector ptp_ocp_sma_in[] = {
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{ .name = "10Mhz", .value = 0x0000 },
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{ .name = "PPS1", .value = 0x0001 },
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{ .name = "PPS2", .value = 0x0002 },
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{ .name = "TS1", .value = 0x0004 },
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{ .name = "TS2", .value = 0x0008 },
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{ .name = "IRIG", .value = 0x0010 },
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{ .name = "DCF", .value = 0x0020 },
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{ .name = "TS3", .value = 0x0040 },
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{ .name = "TS4", .value = 0x0080 },
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{ .name = "FREQ1", .value = 0x0100 },
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{ .name = "FREQ2", .value = 0x0200 },
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{ .name = "FREQ3", .value = 0x0400 },
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{ .name = "FREQ4", .value = 0x0800 },
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{ .name = "None", .value = SMA_DISABLE },
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{ .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
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{ .name = "PPS1", .value = 0x0001, .frequency = 1 },
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{ .name = "PPS2", .value = 0x0002, .frequency = 1 },
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{ .name = "TS1", .value = 0x0004, .frequency = 0 },
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{ .name = "TS2", .value = 0x0008, .frequency = 0 },
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{ .name = "IRIG", .value = 0x0010, .frequency = 10000 },
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{ .name = "DCF", .value = 0x0020, .frequency = 77500 },
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{ .name = "TS3", .value = 0x0040, .frequency = 0 },
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{ .name = "TS4", .value = 0x0080, .frequency = 0 },
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{ .name = "FREQ1", .value = 0x0100, .frequency = 0 },
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{ .name = "FREQ2", .value = 0x0200, .frequency = 0 },
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{ .name = "FREQ3", .value = 0x0400, .frequency = 0 },
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{ .name = "FREQ4", .value = 0x0800, .frequency = 0 },
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{ .name = "None", .value = SMA_DISABLE, .frequency = 0 },
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{ }
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};
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static const struct ocp_selector ptp_ocp_sma_out[] = {
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{ .name = "10Mhz", .value = 0x0000 },
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{ .name = "PHC", .value = 0x0001 },
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{ .name = "MAC", .value = 0x0002 },
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{ .name = "GNSS1", .value = 0x0004 },
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{ .name = "GNSS2", .value = 0x0008 },
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{ .name = "IRIG", .value = 0x0010 },
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{ .name = "DCF", .value = 0x0020 },
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{ .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
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{ .name = "PHC", .value = 0x0001, .frequency = 1 },
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{ .name = "MAC", .value = 0x0002, .frequency = 1 },
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{ .name = "GNSS1", .value = 0x0004, .frequency = 1 },
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{ .name = "GNSS2", .value = 0x0008, .frequency = 1 },
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{ .name = "IRIG", .value = 0x0010, .frequency = 10000 },
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{ .name = "DCF", .value = 0x0020, .frequency = 77000 },
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{ .name = "GEN1", .value = 0x0040 },
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{ .name = "GEN2", .value = 0x0080 },
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{ .name = "GEN3", .value = 0x0100 },
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@ -890,15 +905,15 @@ static const struct ocp_selector ptp_ocp_sma_out[] = {
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};
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static const struct ocp_selector ptp_ocp_art_sma_in[] = {
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{ .name = "PPS1", .value = 0x0001 },
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{ .name = "10Mhz", .value = 0x0008 },
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{ .name = "PPS1", .value = 0x0001, .frequency = 1 },
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{ .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
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{ }
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};
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static const struct ocp_selector ptp_ocp_art_sma_out[] = {
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{ .name = "PHC", .value = 0x0002 },
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{ .name = "GNSS", .value = 0x0004 },
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{ .name = "10Mhz", .value = 0x0010 },
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{ .name = "PHC", .value = 0x0002, .frequency = 1 },
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{ .name = "GNSS", .value = 0x0004, .frequency = 1 },
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{ .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
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{ }
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};
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@ -1351,7 +1366,6 @@ static int
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ptp_ocp_init_clock(struct ptp_ocp *bp)
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{
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struct timespec64 ts;
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bool sync;
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u32 ctrl;
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ctrl = OCP_CTRL_ENABLE;
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@ -1375,8 +1389,8 @@ ptp_ocp_init_clock(struct ptp_ocp *bp)
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ptp_ocp_estimate_pci_timing(bp);
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sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
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if (!sync) {
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bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
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if (!bp->sync) {
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ktime_get_clocktai_ts64(&ts);
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ptp_ocp_settime(&bp->ptp_info, &ts);
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}
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@ -2289,22 +2303,35 @@ ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
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static void
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ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
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{
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struct dpll_pin_properties prop = {
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.board_label = NULL,
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.type = DPLL_PIN_TYPE_EXT,
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.capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
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.freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
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.freq_supported = ptp_ocp_sma_freq,
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};
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u32 reg;
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int i;
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/* defaults */
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for (i = 0; i < OCP_SMA_NUM; i++) {
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bp->sma[i].default_fcn = i & 1;
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bp->sma[i].dpll_prop = prop;
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bp->sma[i].dpll_prop.board_label =
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bp->ptp_info.pin_config[i].name;
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}
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bp->sma[0].mode = SMA_MODE_IN;
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bp->sma[1].mode = SMA_MODE_IN;
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bp->sma[2].mode = SMA_MODE_OUT;
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bp->sma[3].mode = SMA_MODE_OUT;
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for (i = 0; i < 4; i++)
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bp->sma[i].default_fcn = i & 1;
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/* If no SMA1 map, the pin functions and directions are fixed. */
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if (!bp->sma_map1) {
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for (i = 0; i < 4; i++) {
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for (i = 0; i < OCP_SMA_NUM; i++) {
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bp->sma[i].fixed_fcn = true;
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bp->sma[i].fixed_dir = true;
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bp->sma[1].dpll_prop.capabilities &=
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~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
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}
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return;
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}
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@ -2314,7 +2341,7 @@ ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
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*/
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reg = ioread32(&bp->sma_map2->gpio2);
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if (reg == 0xffffffff) {
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for (i = 0; i < 4; i++)
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for (i = 0; i < OCP_SMA_NUM; i++)
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bp->sma[i].fixed_dir = true;
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} else {
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reg = ioread32(&bp->sma_map1->gpio1);
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@ -2336,7 +2363,7 @@ static const struct ocp_sma_op ocp_fb_sma_op = {
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};
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static int
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ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
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ptp_ocp_set_pins(struct ptp_ocp *bp)
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{
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struct ptp_pin_desc *config;
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int i;
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@ -2403,16 +2430,16 @@ ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
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ptp_ocp_tod_init(bp);
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ptp_ocp_nmea_out_init(bp);
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ptp_ocp_sma_init(bp);
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ptp_ocp_signal_init(bp);
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err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
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if (err)
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return err;
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err = ptp_ocp_fb_set_pins(bp);
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err = ptp_ocp_set_pins(bp);
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if (err)
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return err;
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ptp_ocp_sma_init(bp);
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return ptp_ocp_init_clock(bp);
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}
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@ -2452,6 +2479,14 @@ ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
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static void
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ptp_ocp_art_sma_init(struct ptp_ocp *bp)
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{
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struct dpll_pin_properties prop = {
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.board_label = NULL,
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.type = DPLL_PIN_TYPE_EXT,
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.capabilities = 0,
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.freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
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.freq_supported = ptp_ocp_sma_freq,
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};
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u32 reg;
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int i;
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@ -2466,16 +2501,16 @@ ptp_ocp_art_sma_init(struct ptp_ocp *bp)
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bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
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bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
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/* If no SMA map, the pin functions and directions are fixed. */
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if (!bp->art_sma) {
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for (i = 0; i < 4; i++) {
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for (i = 0; i < OCP_SMA_NUM; i++) {
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/* If no SMA map, the pin functions and directions are fixed. */
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bp->sma[i].dpll_prop = prop;
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bp->sma[i].dpll_prop.board_label =
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bp->ptp_info.pin_config[i].name;
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if (!bp->art_sma) {
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bp->sma[i].fixed_fcn = true;
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bp->sma[i].fixed_dir = true;
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continue;
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}
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return;
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}
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for (i = 0; i < 4; i++) {
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reg = ioread32(&bp->art_sma->map[i].gpio);
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switch (reg & 0xff) {
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@ -2486,9 +2521,13 @@ ptp_ocp_art_sma_init(struct ptp_ocp *bp)
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case 1:
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case 8:
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bp->sma[i].mode = SMA_MODE_IN;
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bp->sma[i].dpll_prop.capabilities =
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DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
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break;
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default:
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bp->sma[i].mode = SMA_MODE_OUT;
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bp->sma[i].dpll_prop.capabilities =
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DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
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break;
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}
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}
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@ -2555,6 +2594,9 @@ ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
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/* Enable MAC serial port during initialisation */
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iowrite32(1, &bp->board_config->mro50_serial_activate);
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err = ptp_ocp_set_pins(bp);
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if (err)
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return err;
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ptp_ocp_sma_init(bp);
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err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
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@ -2696,16 +2738,9 @@ sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
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}
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static int
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ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
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ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
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{
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struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
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enum ptp_ocp_sma_mode mode;
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int val;
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mode = sma->mode;
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val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
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if (val < 0)
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return val;
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if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
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return -EOPNOTSUPP;
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@ -2740,6 +2775,20 @@ ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
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return val;
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}
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static int
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ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
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{
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struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
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enum ptp_ocp_sma_mode mode;
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int val;
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mode = sma->mode;
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val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
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if (val < 0)
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return val;
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return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
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}
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static ssize_t
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sma1_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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@ -3834,9 +3883,8 @@ ptp_ocp_summary_show(struct seq_file *s, void *data)
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strcpy(buf, "unknown");
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break;
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}
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val = ioread32(&bp->reg->status);
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seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
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val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
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bp->sync ? "sync" : "unsynced");
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if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
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struct timespec64 sys_ts;
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@ -4068,7 +4116,6 @@ ptp_ocp_phc_info(struct ptp_ocp *bp)
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{
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struct timespec64 ts;
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u32 version, select;
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bool sync;
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version = ioread32(&bp->reg->version);
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select = ioread32(&bp->reg->select);
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@ -4077,11 +4124,10 @@ ptp_ocp_phc_info(struct ptp_ocp *bp)
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ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
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ptp_clock_index(bp->ptp));
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sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
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if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
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dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
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ts.tv_sec, ts.tv_nsec,
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sync ? "in-sync" : "UNSYNCED");
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bp->sync ? "in-sync" : "UNSYNCED");
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}
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static void
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@ -4178,12 +4224,168 @@ ptp_ocp_detach(struct ptp_ocp *bp)
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device_unregister(&bp->dev);
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}
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static int ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll,
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void *priv,
|
||||
enum dpll_lock_status *status,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ptp_ocp *bp = priv;
|
||||
|
||||
*status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
|
||||
const struct dpll_device *dpll, void *priv,
|
||||
enum dpll_pin_state *state,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ptp_ocp *bp = priv;
|
||||
int idx;
|
||||
|
||||
if (bp->pps_select) {
|
||||
idx = ioread32(&bp->pps_select->gpio1);
|
||||
*state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
|
||||
DPLL_PIN_STATE_SELECTABLE;
|
||||
return 0;
|
||||
}
|
||||
NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
|
||||
u32 *mode, struct netlink_ext_ack *extack)
|
||||
{
|
||||
*mode = DPLL_MODE_AUTOMATIC;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool ptp_ocp_dpll_mode_supported(const struct dpll_device *dpll,
|
||||
void *priv, const enum dpll_mode mode,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
return mode == DPLL_MODE_AUTOMATIC;
|
||||
}
|
||||
|
||||
static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
|
||||
void *pin_priv,
|
||||
const struct dpll_device *dpll,
|
||||
void *priv,
|
||||
enum dpll_pin_direction *direction,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ptp_ocp_sma_connector *sma = pin_priv;
|
||||
|
||||
*direction = sma->mode == SMA_MODE_IN ?
|
||||
DPLL_PIN_DIRECTION_INPUT :
|
||||
DPLL_PIN_DIRECTION_OUTPUT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
|
||||
void *pin_priv,
|
||||
const struct dpll_device *dpll,
|
||||
void *dpll_priv,
|
||||
enum dpll_pin_direction direction,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ptp_ocp_sma_connector *sma = pin_priv;
|
||||
struct ptp_ocp *bp = dpll_priv;
|
||||
enum ptp_ocp_sma_mode mode;
|
||||
int sma_nr = (sma - bp->sma);
|
||||
|
||||
if (sma->fixed_dir)
|
||||
return -EOPNOTSUPP;
|
||||
mode = direction == DPLL_PIN_DIRECTION_INPUT ?
|
||||
SMA_MODE_IN : SMA_MODE_OUT;
|
||||
return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr);
|
||||
}
|
||||
|
||||
static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
|
||||
void *pin_priv,
|
||||
const struct dpll_device *dpll,
|
||||
void *dpll_priv, u64 frequency,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ptp_ocp_sma_connector *sma = pin_priv;
|
||||
struct ptp_ocp *bp = dpll_priv;
|
||||
const struct ocp_selector *tbl;
|
||||
int sma_nr = (sma - bp->sma);
|
||||
int i;
|
||||
|
||||
if (sma->fixed_fcn)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
tbl = bp->sma_op->tbl[sma->mode];
|
||||
for (i = 0; tbl[i].name; i++)
|
||||
if (tbl[i].frequency == frequency)
|
||||
return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
|
||||
void *pin_priv,
|
||||
const struct dpll_device *dpll,
|
||||
void *dpll_priv, u64 *frequency,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct ptp_ocp_sma_connector *sma = pin_priv;
|
||||
struct ptp_ocp *bp = dpll_priv;
|
||||
const struct ocp_selector *tbl;
|
||||
int sma_nr = (sma - bp->sma);
|
||||
u32 val;
|
||||
int i;
|
||||
|
||||
val = bp->sma_op->get(bp, sma_nr);
|
||||
tbl = bp->sma_op->tbl[sma->mode];
|
||||
for (i = 0; tbl[i].name; i++)
|
||||
if (val == tbl[i].value) {
|
||||
*frequency = tbl[i].frequency;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct dpll_device_ops dpll_ops = {
|
||||
.lock_status_get = ptp_ocp_dpll_lock_status_get,
|
||||
.mode_get = ptp_ocp_dpll_mode_get,
|
||||
.mode_supported = ptp_ocp_dpll_mode_supported,
|
||||
};
|
||||
|
||||
static const struct dpll_pin_ops dpll_pins_ops = {
|
||||
.frequency_get = ptp_ocp_dpll_frequency_get,
|
||||
.frequency_set = ptp_ocp_dpll_frequency_set,
|
||||
.direction_get = ptp_ocp_dpll_direction_get,
|
||||
.direction_set = ptp_ocp_dpll_direction_set,
|
||||
.state_on_dpll_get = ptp_ocp_dpll_state_get,
|
||||
};
|
||||
|
||||
static void
|
||||
ptp_ocp_sync_work(struct work_struct *work)
|
||||
{
|
||||
struct ptp_ocp *bp;
|
||||
bool sync;
|
||||
|
||||
bp = container_of(work, struct ptp_ocp, sync_work.work);
|
||||
sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
|
||||
|
||||
if (bp->sync != sync)
|
||||
dpll_device_change_ntf(bp->dpll);
|
||||
|
||||
bp->sync = sync;
|
||||
|
||||
queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
|
||||
}
|
||||
|
||||
static int
|
||||
ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
struct devlink *devlink;
|
||||
struct ptp_ocp *bp;
|
||||
int err;
|
||||
int err, i;
|
||||
u64 clkid;
|
||||
|
||||
devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
|
||||
if (!devlink) {
|
||||
@ -4202,6 +4404,8 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
if (err)
|
||||
goto out_disable;
|
||||
|
||||
INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
|
||||
|
||||
/* compat mode.
|
||||
* Older FPGA firmware only returns 2 irq's.
|
||||
* allow this - if not all of the IRQ's are returned, skip the
|
||||
@ -4233,8 +4437,43 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
|
||||
ptp_ocp_info(bp);
|
||||
devlink_register(devlink);
|
||||
return 0;
|
||||
|
||||
clkid = pci_get_dsn(pdev);
|
||||
bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
|
||||
if (IS_ERR(bp->dpll)) {
|
||||
err = PTR_ERR(bp->dpll);
|
||||
dev_err(&pdev->dev, "dpll_device_alloc failed\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
for (i = 0; i < OCP_SMA_NUM; i++) {
|
||||
bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
|
||||
if (IS_ERR(bp->sma[i].dpll_pin)) {
|
||||
err = PTR_ERR(bp->dpll);
|
||||
goto out_dpll;
|
||||
}
|
||||
|
||||
err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
|
||||
&bp->sma[i]);
|
||||
if (err) {
|
||||
dpll_pin_put(bp->sma[i].dpll_pin);
|
||||
goto out_dpll;
|
||||
}
|
||||
}
|
||||
queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
|
||||
|
||||
return 0;
|
||||
out_dpll:
|
||||
while (i) {
|
||||
--i;
|
||||
dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
|
||||
dpll_pin_put(bp->sma[i].dpll_pin);
|
||||
}
|
||||
dpll_device_put(bp->dpll);
|
||||
out:
|
||||
ptp_ocp_detach(bp);
|
||||
out_disable:
|
||||
@ -4249,7 +4488,17 @@ ptp_ocp_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct ptp_ocp *bp = pci_get_drvdata(pdev);
|
||||
struct devlink *devlink = priv_to_devlink(bp);
|
||||
int i;
|
||||
|
||||
cancel_delayed_work_sync(&bp->sync_work);
|
||||
for (i = 0; i < OCP_SMA_NUM; i++) {
|
||||
if (bp->sma[i].dpll_pin) {
|
||||
dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, bp);
|
||||
dpll_pin_put(bp->sma[i].dpll_pin);
|
||||
}
|
||||
}
|
||||
dpll_device_unregister(bp->dpll, &dpll_ops, bp);
|
||||
dpll_device_put(bp->dpll);
|
||||
devlink_unregister(devlink);
|
||||
ptp_ocp_detach(bp);
|
||||
pci_disable_device(pdev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user