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https://mirrors.bfsu.edu.cn/git/linux.git
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ARM: SoC changes, part 2
This is the second part of the general SoC updates, containing
everything that did not make it in the initial pull request,
or that came in as a bugfix later.
- Devicetree updates for SoCFPGA, ASPEED, AT91 and Rockchip, including
a new machine using an ASPEED BMC.
- More DT fixes from Krzysztof Kozlowski across platforms
- A new SoC platform for the GXP baseboard management controller,
used in current server products from HPE.
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Merge tag 'arm-late-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM SoC updates from Arnd Bergmann:
"This is the second part of the general SoC updates, containing
everything that did not make it in the initial pull request, or that
came in as a bugfix later.
- Devicetree updates for SoCFPGA, ASPEED, AT91 and Rockchip,
including a new machine using an ASPEED BMC.
- More DT fixes from Krzysztof Kozlowski across platforms
- A new SoC platform for the GXP baseboard management controller,
used in current server products from HPE"
* tag 'arm-late-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (56 commits)
ARM: configs: Enable more audio support for i.MX
tee: optee: Pass a pointer to virt_addr_valid()
arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
arm64: dts: rockchip: add clocks property to cru node rk3368
arm64: dts: rockchip: add clocks property to cru node rk3308
arm64: dts: rockchip: add clocks to rk356x cru
ARM: dts: rockchip: add clocks property to cru node rk3228
ARM: dts: rockchip: add clocks property to cru node rk3036
ARM: dts: rockchip: add clocks property to cru node rk3066a/rk3188
ARM: dts: rockchip: add clocks property to cru node rk3288
ARM: dts: rockchip: Remove "amba" bus nodes from rv1108
ARM: dts: rockchip: add clocks property to cru node rv1108
arm64: dts: sprd: use new 'dma-channels' property
ARM: dts: da850: use new 'dma-channels' property
ARM: dts: pxa: use new 'dma-channels/requests' properties
soc: ixp4xx/qmgr: Fix unused match warning
ARM: ep93xx: Make ts72xx_register_flash() static
ARM: configs: enable support for Kontron KSwitch D10
ep93xx: clock: Do not return the address of the freed memory
arm64: dts: intel: add device tree for n6000
...
This commit is contained in:
Linus Torvalds
commit
09a018176b
27
Documentation/devicetree/bindings/arm/hpe,gxp.yaml
Normal file
27
Documentation/devicetree/bindings/arm/hpe,gxp.yaml
Normal file
@ -0,0 +1,27 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: HPE BMC GXP platforms
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maintainers:
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- Nick Hawkins <nick.hawkins@hpe.com>
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- Jean-Marie Verdun <verdun@hpe.com>
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properties:
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compatible:
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oneOf:
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- description: GXP Based Boards
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items:
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- enum:
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- hpe,gxp-dl360gen10
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- const: hpe,gxp
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required:
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- compatible
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additionalProperties: true
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...
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@ -18,6 +18,7 @@ properties:
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items:
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- enum:
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- intel,n5x-socdk
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- intel,socfpga-agilex-n6000
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- intel,socfpga-agilex-socdk
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- const: intel,socfpga-agilex
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@ -9,8 +9,9 @@ Required properties:
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- The second cell is reserved and is currently unused.
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- gpio-controller : Marks the device node as a GPIO controller.
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- interrupt-controller: Mark the device node as an interrupt controller
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- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware.
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- #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
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- The first cell is the GPIO offset number within the GPIO controller.
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- The second cell is the interrupt trigger type and level flags.
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- interrupts: Specify the interrupt.
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- altr,interrupt-type: Specifies the interrupt trigger type the GPIO
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hardware is synthesized. This field is required if the Altera GPIO controller
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@ -38,6 +39,6 @@ gpio_altr: gpio@ff200000 {
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altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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@ -0,0 +1,51 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2022, Intel Corporation
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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|
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title: Intel HPS Copy Engine
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|
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maintainers:
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- Matthew Gerlach <matthew.gerlach@linux.intel.com>
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|
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description: |
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The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
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a bootable image from host memory to HPS DDR. Additionally, there is a
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register the HPS can use to indicate the state of booting the copied image as
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well as a keep-a-live indication to the host.
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properties:
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compatible:
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const: intel,hps-copy-engine
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'#dma-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
|
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additionalProperties: false
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|
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examples:
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- |
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bus@80000000 {
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compatible = "simple-bus";
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reg = <0x80000000 0x60000000>,
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<0xf9000000 0x00100000>;
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reg-names = "axi_h2f", "axi_h2f_lw";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
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dma-controller@0 {
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compatible = "intel,hps-copy-engine";
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reg = <0x00000000 0x00000000 0x00001000>;
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#dma-cells = <1>;
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};
|
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};
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47
Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
Normal file
47
Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/timer/hpe,gxp-timer.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: HPE GXP Timer
|
||||
|
||||
maintainers:
|
||||
- Nick Hawkins <nick.hawkins@hpe.com>
|
||||
- Jean-Marie Verdun <verdun@hpe.com>
|
||||
|
||||
properties:
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||||
compatible:
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const: hpe,gxp-timer
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|
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reg:
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maxItems: 1
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||||
|
||||
interrupts:
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maxItems: 1
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||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: iop
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
timer@c0000000 {
|
||||
compatible = "hpe,gxp-timer";
|
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reg = <0x80 0x16>;
|
||||
interrupts = <0>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clocks = <&iopclk>;
|
||||
clock-names = "iop";
|
||||
};
|
||||
12
MAINTAINERS
12
MAINTAINERS
@ -2125,6 +2125,18 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git
|
||||
F: arch/arm/mach-sa1100/include/mach/jornada720.h
|
||||
F: arch/arm/mach-sa1100/jornada720.c
|
||||
|
||||
ARM/HPE GXP ARCHITECTURE
|
||||
M: Jean-Marie Verdun <verdun@hpe.com>
|
||||
M: Nick Hawkins <nick.hawkins@hpe.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml
|
||||
F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
|
||||
F: arch/arm/boot/dts/hpe-bmc*
|
||||
F: arch/arm/boot/dts/hpe-gxp*
|
||||
F: arch/arm/mach-hpe/
|
||||
F: drivers/clocksource/timer-gxp.c
|
||||
F: drivers/watchdog/gxp-wdt.c
|
||||
|
||||
ARM/IGEP MACHINE SUPPORT
|
||||
M: Enric Balletbo i Serra <eballetbo@gmail.com>
|
||||
M: Javier Martinez Canillas <javier@dowhile0.org>
|
||||
|
||||
@ -531,6 +531,8 @@ source "arch/arm/mach-highbank/Kconfig"
|
||||
|
||||
source "arch/arm/mach-hisi/Kconfig"
|
||||
|
||||
source "arch/arm/mach-hpe/Kconfig"
|
||||
|
||||
source "arch/arm/mach-imx/Kconfig"
|
||||
|
||||
source "arch/arm/mach-iop32x/Kconfig"
|
||||
|
||||
@ -179,6 +179,7 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
|
||||
machine-$(CONFIG_ARCH_GEMINI) += gemini
|
||||
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
|
||||
machine-$(CONFIG_ARCH_HISI) += hisi
|
||||
machine-$(CONFIG_ARCH_HPE) += hpe
|
||||
machine-$(CONFIG_ARCH_IOP32X) += iop32x
|
||||
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
|
||||
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
|
||||
|
||||
@ -259,6 +259,8 @@ dtb-$(CONFIG_ARCH_HISI) += \
|
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hi3519-demb.dtb
|
||||
dtb-$(CONFIG_ARCH_HIX5HD2) += \
|
||||
hisi-x5hd2-dkb.dtb
|
||||
dtb-$(CONFIG_ARCH_HPE_GXP) += \
|
||||
hpe-bmc-dl360gen10.dtb
|
||||
dtb-$(CONFIG_ARCH_INTEGRATOR) += \
|
||||
integratorap.dtb \
|
||||
integratorap-im-pd1.dtb \
|
||||
@ -1584,6 +1586,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-bmc-lenovo-hr630.dtb \
|
||||
aspeed-bmc-lenovo-hr855xg2.dtb \
|
||||
aspeed-bmc-microsoft-olympus.dtb \
|
||||
aspeed-bmc-nuvia-dc-scm.dtb \
|
||||
aspeed-bmc-opp-lanyang.dtb \
|
||||
aspeed-bmc-opp-mihawk.dtb \
|
||||
aspeed-bmc-opp-mowgli.dtb \
|
||||
|
||||
@ -23,6 +23,26 @@
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
video_engine_memory: video {
|
||||
size = <0x04000000>;
|
||||
alignment = <0x01000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
};
|
||||
|
||||
gfx_memory: framebuffer {
|
||||
size = <0x01000000>;
|
||||
alignment = <0x01000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhci0: regulator-vcc-sdhci0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SDHCI0 Vcc";
|
||||
@ -103,7 +123,7 @@
|
||||
&mac0 {
|
||||
status = "okay";
|
||||
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <ðphy0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
@ -114,7 +134,7 @@
|
||||
&mac1 {
|
||||
status = "okay";
|
||||
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <ðphy1>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
@ -300,3 +320,18 @@
|
||||
vqmmc-supply = <&vccq_sdhci1>;
|
||||
clk-phase-sd-hs = <7>, <200>;
|
||||
};
|
||||
|
||||
&vhub {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&video {
|
||||
status = "okay";
|
||||
memory-region = <&video_engine_memory>;
|
||||
};
|
||||
|
||||
&gfx {
|
||||
status = "okay";
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
@ -51,26 +51,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
spi2_gpio: spi2-gpio {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
|
||||
gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
|
||||
gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
m25p,fast-read;
|
||||
label = "pnor";
|
||||
spi-max-frequency = <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
switchphy: ethernet-phy@0 {
|
||||
// Fixed link
|
||||
};
|
||||
@ -242,6 +222,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi2_default>;
|
||||
|
||||
flash@0 {
|
||||
status = "okay";
|
||||
m25p,fast-read;
|
||||
label = "pnor";
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
ina230@45 {
|
||||
@ -260,6 +253,17 @@
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
sled1_ioexp41: pca9536@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"SLED1_SWD_MUX", "SLED1_XRES_SWD_N",
|
||||
"SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN";
|
||||
};
|
||||
|
||||
sled1_ioexp: pca9539@76 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x76>;
|
||||
@ -310,6 +314,11 @@
|
||||
op-sink-microwatt = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
@ -330,6 +339,17 @@
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
sled2_ioexp41: pca9536@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"SLED2_SWD_MUX", "SLED2_XRES_SWD_N",
|
||||
"SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN";
|
||||
};
|
||||
|
||||
sled2_ioexp: pca9539@76 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x76>;
|
||||
@ -380,6 +400,11 @@
|
||||
op-sink-microwatt = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
@ -400,6 +425,17 @@
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
sled3_ioexp41: pca9536@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"SLED3_SWD_MUX", "SLED3_XRES_SWD_N",
|
||||
"SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN";
|
||||
};
|
||||
|
||||
sled3_ioexp: pca9539@76 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x76>;
|
||||
@ -450,6 +486,11 @@
|
||||
op-sink-microwatt = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
@ -470,6 +511,17 @@
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
sled4_ioexp41: pca9536@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"SLED4_SWD_MUX", "SLED4_XRES_SWD_N",
|
||||
"SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN";
|
||||
};
|
||||
|
||||
sled4_ioexp: pca9539@76 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x76>;
|
||||
@ -520,6 +572,11 @@
|
||||
op-sink-microwatt = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
@ -540,6 +597,17 @@
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
sled5_ioexp41: pca9536@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"SLED5_SWD_MUX", "SLED5_XRES_SWD_N",
|
||||
"SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN";
|
||||
};
|
||||
|
||||
sled5_ioexp: pca9539@76 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x76>;
|
||||
@ -590,6 +658,11 @@
|
||||
op-sink-microwatt = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
@ -610,6 +683,17 @@
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
sled6_ioexp41: pca9536@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"SLED6_SWD_MUX", "SLED6_XRES_SWD_N",
|
||||
"SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN";
|
||||
};
|
||||
|
||||
sled6_ioexp: pca9539@76 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x76>;
|
||||
@ -660,6 +744,11 @@
|
||||
op-sink-microwatt = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
@ -732,6 +821,8 @@
|
||||
compatible = "adi,adm1278";
|
||||
reg = <0x11>;
|
||||
shunt-resistor-micro-ohms = <300>;
|
||||
adi,volt-curr-sample-average = <128>;
|
||||
adi,power-sample-average = <128>;
|
||||
};
|
||||
|
||||
tmp421@4c {
|
||||
@ -771,43 +862,55 @@
|
||||
&gpio0 {
|
||||
gpio-line-names =
|
||||
/*A0-A7*/ "","","","","","","","",
|
||||
/*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1",
|
||||
"SPI2_MUX2","SPI2_MUX3","","",
|
||||
/*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N",
|
||||
"SEL_SPI2_MUX","SPI2_MUX1",
|
||||
"SPI2_MUX2","SPI2_MUX3",
|
||||
"","FUSB302_SLED3_INT_N",
|
||||
/*C0-C7*/ "","","","","","","","",
|
||||
/*D0-D7*/ "","","","","","","","",
|
||||
/*E0-E7*/ "","","","","","","","",
|
||||
/*F0-F7*/ "","","","","","","","",
|
||||
/*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","",
|
||||
/*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK",
|
||||
"BMC_SLED3_STCK","BMC_SLED4_STCK",
|
||||
"BMC_SLED5_STCK","BMC_SLED6_STCK",
|
||||
"","",
|
||||
/*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL",
|
||||
"PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","",
|
||||
/*H0-H7*/ "presence-riser1","presence-riser2",
|
||||
"presence-sled1","presence-sled2",
|
||||
"presence-sled3","presence-sled4",
|
||||
"presence-sled5","presence-sled6",
|
||||
/*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2",
|
||||
"","BSM_FLASH_WP_STATUS","BMC_TPM_PRES","",
|
||||
/*I0-I7*/ "REV_ID0","",
|
||||
"REV_ID1","REV_ID2",
|
||||
"","BSM_FLASH_WP_STATUS",
|
||||
"BMC_TPM_PRES_N","FUSB302_SLED6_INT_N",
|
||||
/*J0-J7*/ "","","","","","","","",
|
||||
/*K0-K7*/ "","","","","","","","",
|
||||
/*L0-L7*/ "","","","","","BMC_RTC_INT","","",
|
||||
/*M0-M7*/ "ALERT_SLED1","ALERT_SLED2",
|
||||
"ALERT_SLED3","ALERT_SLED4",
|
||||
"ALERT_SLED5","ALERT_SLED6",
|
||||
"P12V_AUX_ALERT1","",
|
||||
/*N0-N7*/ "","","","","","","","",
|
||||
/*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N",
|
||||
"ALERT_SLED3_N","ALERT_SLED4_N",
|
||||
"ALERT_SLED5_N","ALERT_SLED6_N",
|
||||
"","",
|
||||
/*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1",
|
||||
"LED_POSTCODE_2","LED_POSTCODE_3",
|
||||
"LED_POSTCODE_4","LED_POSTCODE_5",
|
||||
"LED_POSTCODE_5","LED_POSTCODE_7",
|
||||
/*O0-O7*/ "","","","",
|
||||
"","BOARD_ID0","BOARD_ID1","BOARD_ID2",
|
||||
/*P0-P7*/ "","","","","","","","BMC_HEARTBEAT",
|
||||
/*Q0-Q7*/ "","","","","","","","",
|
||||
/*R0-R7*/ "","","","","","","","",
|
||||
/*S0-S7*/ "","","","BAT_DETECT",
|
||||
"BMC_BT_WP0","BMC_BT_WP1","","",
|
||||
"BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N",
|
||||
/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","","",
|
||||
/*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL","","PSU_PRSNT",
|
||||
/*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N",
|
||||
"P12V_AUX_ALERT1_N","PSU_PRSNT",
|
||||
"USB2_SEL0_A","USB2_SEL1_A",
|
||||
"USB2_SEL0_B","USB2_SEL1_B",
|
||||
/*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","",
|
||||
/*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","",
|
||||
/*X0-X7*/ "","","","","","","","",
|
||||
/*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT","BSM_FLASH_LATCH","",
|
||||
/*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N",
|
||||
"BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N",
|
||||
"","","","",
|
||||
/*Z0-Z7*/ "","","","","","","","";
|
||||
};
|
||||
@ -834,7 +937,16 @@
|
||||
&pinctrl_adc14_default &pinctrl_adc15_default>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
/* TODO: Add Marvell 88E6191X */
|
||||
};
|
||||
|
||||
&mdio3 {
|
||||
status = "okay";
|
||||
/* TODO: Add Marvell 88X3310 */
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -283,7 +283,7 @@
|
||||
/*P0-P7*/ "","","","","led-pcieslot-power","","","",
|
||||
/*Q0-Q7*/ "","","regulator-standby-faulted","","","","","",
|
||||
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","",
|
||||
/*S0-S7*/ "","","","","","","","",
|
||||
/*S0-S7*/ "","","","","power-ffs-sync-history","","","",
|
||||
/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","","",
|
||||
/*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","",
|
||||
|
||||
@ -265,7 +265,7 @@
|
||||
/*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","",
|
||||
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
|
||||
/*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3",
|
||||
"","","","",
|
||||
"power-ffs-sync-history","","","",
|
||||
/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","","",
|
||||
/*V0-V7*/ "","","","","","","","",
|
||||
|
||||
190
arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
Normal file
190
arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
Normal file
@ -0,0 +1,190 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "aspeed-g6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Nuvia DC-SCM BMC";
|
||||
compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600";
|
||||
|
||||
aliases {
|
||||
serial4 = &uart5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart5;
|
||||
bootargs = "console=ttyS4,115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio3 {
|
||||
status = "okay";
|
||||
|
||||
ethphy3: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mac2 {
|
||||
status = "okay";
|
||||
|
||||
/* Bootloader sets up the MAC to insert delay */
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy3>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rgmii3_default>;
|
||||
};
|
||||
|
||||
&mac3 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rmii4_default>;
|
||||
|
||||
use-ncsi;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fmc {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
status = "okay";
|
||||
m25p,fast-read;
|
||||
label = "bmc";
|
||||
spi-max-frequency = <133000000>;
|
||||
#include "openbmc-flash-layout-64.dtsi"
|
||||
};
|
||||
|
||||
flash@1 {
|
||||
status = "okay";
|
||||
m25p,fast-read;
|
||||
label = "alt-bmc";
|
||||
spi-max-frequency = <133000000>;
|
||||
#include "openbmc-flash-layout-64-alt.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1_default>;
|
||||
|
||||
flash@0 {
|
||||
status = "okay";
|
||||
m25p,fast-read;
|
||||
label = "bios";
|
||||
spi-max-frequency = <133000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
gpio-line-names =
|
||||
/*A0-A7*/ "","","","","","","","",
|
||||
/*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","",
|
||||
/*C0-C7*/ "","","","","","","","",
|
||||
/*D0-D7*/ "","","","","","","","",
|
||||
/*E0-E7*/ "","","","","","","","",
|
||||
/*F0-F7*/ "","","","","","","","",
|
||||
/*G0-G7*/ "","","","","","","","",
|
||||
/*H0-H7*/ "","","","","","","","",
|
||||
/*I0-I7*/ "","","","","","","","",
|
||||
/*J0-J7*/ "","","","","","","","",
|
||||
/*K0-K7*/ "","","","","","","","",
|
||||
/*L0-L7*/ "","","","","","","","",
|
||||
/*M0-M7*/ "","","","","","","","",
|
||||
/*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
|
||||
/*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","",
|
||||
/*P0-P7*/ "","","","","","","","",
|
||||
/*Q0-Q7*/ "","","","","","","","",
|
||||
/*R0-R7*/ "","","","","","","","",
|
||||
/*S0-S7*/ "","","","","","","","",
|
||||
/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","","",
|
||||
/*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
|
||||
"SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
|
||||
"SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
|
||||
/*W0-W7*/ "","","","","","","","",
|
||||
/*X0-X7*/ "","","","","","","","",
|
||||
/*Y0-Y7*/ "","","","","","","","",
|
||||
/*Z0-Z7*/ "","","","","","","","",
|
||||
/*AA0-AA7*/ "","","","","","","","",
|
||||
/*AB0-AB7*/ "","","","","","","","",
|
||||
/*AC0-AC7*/ "","","","","","","","";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
/*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
|
||||
"SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
|
||||
/*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
|
||||
"SCMFPGA_SPARE_GPIO5_1V8","","","","","",
|
||||
/*C0-C7*/ "","","","","","","","",
|
||||
/*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
|
||||
"","TPM2_PIRQ_N","TPM2_RST_N","",
|
||||
/*E0-E7*/ "","","","","","","","";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c12 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c13 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c14 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c15 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vhub {
|
||||
status = "okay";
|
||||
};
|
||||
@ -54,8 +54,7 @@
|
||||
ranges;
|
||||
|
||||
fmc: spi@1e620000 {
|
||||
reg = < 0x1e620000 0x94
|
||||
0x20000000 0x10000000 >;
|
||||
reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2400-fmc";
|
||||
@ -65,34 +64,42 @@
|
||||
flash@0 {
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@2 {
|
||||
reg = < 2 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@3 {
|
||||
reg = < 3 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@4 {
|
||||
reg = < 4 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi: spi@1e630000 {
|
||||
reg = < 0x1e630000 0x18
|
||||
0x30000000 0x10000000 >;
|
||||
reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2400-spi";
|
||||
@ -102,6 +109,7 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -55,8 +55,7 @@
|
||||
ranges;
|
||||
|
||||
fmc: spi@1e620000 {
|
||||
reg = < 0x1e620000 0xc4
|
||||
0x20000000 0x10000000 >;
|
||||
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2500-fmc";
|
||||
@ -67,25 +66,27 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@2 {
|
||||
reg = < 2 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@1e630000 {
|
||||
reg = < 0x1e630000 0xc4
|
||||
0x30000000 0x08000000 >;
|
||||
reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2500-spi";
|
||||
@ -95,19 +96,20 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@1e631000 {
|
||||
reg = < 0x1e631000 0xc4
|
||||
0x38000000 0x08000000 >;
|
||||
reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2500-spi";
|
||||
@ -117,12 +119,14 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -95,8 +95,7 @@
|
||||
};
|
||||
|
||||
fmc: spi@1e620000 {
|
||||
reg = < 0x1e620000 0xc4
|
||||
0x20000000 0x10000000 >;
|
||||
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2600-fmc";
|
||||
@ -107,25 +106,27 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@2 {
|
||||
reg = < 2 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@1e630000 {
|
||||
reg = < 0x1e630000 0xc4
|
||||
0x30000000 0x10000000 >;
|
||||
reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2600-spi";
|
||||
@ -135,19 +136,20 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@1e631000 {
|
||||
reg = < 0x1e631000 0xc4
|
||||
0x50000000 0x10000000 >;
|
||||
reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "aspeed,ast2600-spi";
|
||||
@ -157,18 +159,21 @@
|
||||
reg = < 0 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@1 {
|
||||
reg = < 1 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
flash@2 {
|
||||
reg = < 2 >;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -302,6 +307,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
udc: usb@1e6a2000 {
|
||||
compatible = "aspeed,ast2600-udc";
|
||||
reg = <0x1e6a2000 0x300>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2bd_default>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -355,6 +370,17 @@
|
||||
quality = <100>;
|
||||
};
|
||||
|
||||
gfx: display@1e6e6000 {
|
||||
compatible = "aspeed,ast2600-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
|
||||
resets = <&syscon ASPEED_RESET_GRAPHICS>;
|
||||
syscon = <&syscon>;
|
||||
status = "disabled";
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
xdma: xdma@1e6e7000 {
|
||||
compatible = "aspeed,ast2600-xdma";
|
||||
reg = <0x1e6e7000 0x100>;
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include <dt-bindings/mfd/atmel-flexcom.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/sound/microchip,pdmc.h>
|
||||
|
||||
/ {
|
||||
model = "Microchip SAMA7G5-EK";
|
||||
@ -456,7 +457,7 @@
|
||||
&pinctrl_gmac1_mdio_default
|
||||
&pinctrl_gmac1_phy_irq>;
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
status = "okay"; /* Conflict with pdmc0. */
|
||||
|
||||
ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
@ -470,6 +471,17 @@
|
||||
pinctrl-0 = <&pinctrl_i2s0_default>;
|
||||
};
|
||||
|
||||
&pdmc0 {
|
||||
#sound-dai-cells = <0>;
|
||||
microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */
|
||||
<MCHP_PDMC_DS1 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 2 */
|
||||
<MCHP_PDMC_DS0 MCHP_PDMC_CLK_POSITIVE>, /* MIC 3 */
|
||||
<MCHP_PDMC_DS1 MCHP_PDMC_CLK_POSITIVE>; /* MIC 4 */
|
||||
status = "disabled"; /* Conflict with gmac1. */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pdmc0_default>;
|
||||
};
|
||||
|
||||
&pioA {
|
||||
|
||||
pinctrl_can0_default: can0_default {
|
||||
@ -639,6 +651,13 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_pdmc0_default: pdmc0_default {
|
||||
pinmux = <PIN_PD23__PDMC0_DS0>,
|
||||
<PIN_PD24__PDMC0_DS1>,
|
||||
<PIN_PD22__PDMC0_CLK>;
|
||||
bias_disable;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspi {
|
||||
pinmux = <PIN_PB12__QSPI0_IO0>,
|
||||
<PIN_PB11__QSPI0_IO1>,
|
||||
|
||||
@ -178,6 +178,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -102,6 +102,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -212,6 +212,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
|
||||
};
|
||||
|
||||
rtc@fffffe00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -679,7 +679,9 @@
|
||||
"scheduler", "queuemgr";
|
||||
interrupts = <58>;
|
||||
#dma-cells = <2>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <4>;
|
||||
dma-channels = <4>;
|
||||
power-domains = <&psc1 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
26
arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
Normal file
26
arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
Normal file
@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree file for HPE DL360Gen10
|
||||
*/
|
||||
|
||||
/include/ "hpe-gxp.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
|
||||
model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
|
||||
|
||||
aliases {
|
||||
serial0 = &uartc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
};
|
||||
};
|
||||
127
arch/arm/boot/dts/hpe-gxp.dtsi
Normal file
127
arch/arm/boot/dts/hpe-gxp.dtsi
Normal file
@ -0,0 +1,127 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree file for HPE GXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Hewlett Packard Enterprise GXP BMC";
|
||||
compatible = "hpe,gxp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
pll: clock-0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1600000000>;
|
||||
};
|
||||
|
||||
iopclk: clock-1 {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&pll>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
L2: cache-controller@b0040000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xb0040000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
ahb@c0000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xc0000000 0x30000000>;
|
||||
dma-ranges;
|
||||
|
||||
vic0: interrupt-controller@eff0000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
reg = <0xeff0000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
vic1: interrupt-controller@80f00000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
reg = <0x80f00000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
uarta: serial@e0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xe0 0x8>;
|
||||
interrupts = <17>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clock-frequency = <1846153>;
|
||||
reg-shift = <0>;
|
||||
};
|
||||
|
||||
uartb: serial@e8 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xe8 0x8>;
|
||||
interrupts = <18>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clock-frequency = <1846153>;
|
||||
reg-shift = <0>;
|
||||
};
|
||||
|
||||
uartc: serial@f0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xf0 0x8>;
|
||||
interrupts = <19>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clock-frequency = <1846153>;
|
||||
reg-shift = <0>;
|
||||
};
|
||||
|
||||
usb0: usb@efe0000 {
|
||||
compatible = "hpe,gxp-ehci", "generic-ehci";
|
||||
reg = <0xefe0000 0x100>;
|
||||
interrupts = <7>;
|
||||
interrupt-parent = <&vic0>;
|
||||
};
|
||||
|
||||
st: timer@80 {
|
||||
compatible = "hpe,gxp-timer";
|
||||
reg = <0x80 0x16>;
|
||||
interrupts = <0>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clocks = <&iopclk>;
|
||||
clock-names = "iop";
|
||||
};
|
||||
|
||||
usb1: usb@efe0100 {
|
||||
compatible = "hpe,gxp-ohci", "generic-ohci";
|
||||
reg = <0xefe0100 0x110>;
|
||||
interrupts = <6>;
|
||||
interrupt-parent = <&vic0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -275,7 +275,9 @@
|
||||
compatible = "marvell,pdma-1.0";
|
||||
reg = <0xd4000000 0x10000>;
|
||||
interrupts = <48>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <16>;
|
||||
dma-channels = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -38,9 +38,12 @@
|
||||
compatible = "marvell,pdma-1.0";
|
||||
reg = <0x40000000 0x10000>;
|
||||
interrupts = <25>;
|
||||
#dma-channels = <16>;
|
||||
#dma-cells = <2>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <16>;
|
||||
dma-channels = <16>;
|
||||
#dma-requests = <40>;
|
||||
dma-requests = <40>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -12,9 +12,12 @@
|
||||
compatible = "marvell,pdma-1.0";
|
||||
reg = <0x40000000 0x10000>;
|
||||
interrupts = <25>;
|
||||
#dma-channels = <32>;
|
||||
#dma-cells = <2>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <32>;
|
||||
dma-channels = <32>;
|
||||
#dma-requests = <75>;
|
||||
dma-requests = <75>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -122,9 +122,12 @@
|
||||
compatible = "marvell,pdma-1.0";
|
||||
reg = <0x40000000 0x10000>;
|
||||
interrupts = <25>;
|
||||
#dma-channels = <32>;
|
||||
#dma-cells = <2>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <32>;
|
||||
dma-channels = <32>;
|
||||
#dma-requests = <100>;
|
||||
dma-requests = <100>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -330,6 +330,8 @@
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -202,8 +202,9 @@
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3066a-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
|
||||
|
||||
@ -195,8 +195,9 @@
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
@ -484,6 +484,8 @@
|
||||
cru: clock-controller@110e0000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x110e0000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -862,6 +862,8 @@
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3288-cru";
|
||||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -85,24 +85,6 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
amba: bus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@102a0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x102a0000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMAC>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
bus_intmem: sram@10080000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x10080000 0x2000>;
|
||||
@ -259,6 +241,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pdma: dma-controller@102a0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x102a0000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMAC>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
grf: syscon@10300000 {
|
||||
compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
|
||||
reg = <0x10300000 0x1000>;
|
||||
@ -456,6 +449,8 @@
|
||||
cru: clock-controller@20200000 {
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -684,7 +684,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtt: rtt@fffffe20 {
|
||||
rtt: rtc@fffffe20 {
|
||||
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffe20 0x20>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
|
||||
@ -209,7 +209,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtt: rtt@e001d020 {
|
||||
rtt: rtc@e001d020 {
|
||||
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
|
||||
reg = <0xe001d020 0x30>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -463,6 +463,30 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pdmc0: sound@e1608000 {
|
||||
compatible = "microchip,sama7g5-pdmc";
|
||||
reg = <0xe1608000 0x1000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>;
|
||||
dma-names = "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>;
|
||||
clock-names = "pclk", "gclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pdmc1: sound@e160c000 {
|
||||
compatible = "microchip,sama7g5-pdmc";
|
||||
reg = <0xe160c000 0x1000>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>;
|
||||
dma-names = "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>;
|
||||
clock-names = "pclk", "gclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spdifrx: spdifrx@e1614000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "microchip,sama7g5-spdifrx";
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
flash0: n25q00@0 {
|
||||
flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,mt25qu02g", "jedec,spi-nor";
|
||||
|
||||
@ -121,7 +121,7 @@
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
flash0: n25q00@0 {
|
||||
flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,mt25qu02g", "jedec,spi-nor";
|
||||
|
||||
@ -113,7 +113,7 @@
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
flash0: n25q512a@0 {
|
||||
flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q512a", "jedec,spi-nor";
|
||||
|
||||
@ -221,7 +221,7 @@
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
n25q128@0 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128", "jedec,spi-nor";
|
||||
@ -238,7 +238,7 @@
|
||||
cdns,tslch-ns = <4>;
|
||||
};
|
||||
|
||||
n25q00@1 {
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,mt25qu02g", "jedec,spi-nor";
|
||||
|
||||
@ -17,6 +17,7 @@ CONFIG_SOC_SAMA5D2=y
|
||||
CONFIG_SOC_SAMA5D3=y
|
||||
CONFIG_SOC_SAMA5D4=y
|
||||
CONFIG_SOC_SAMA7G5=y
|
||||
CONFIG_SOC_LAN966=y
|
||||
CONFIG_ARCH_BCM=y
|
||||
CONFIG_ARCH_BCM_CYGNUS=y
|
||||
CONFIG_ARCH_BCM_HR2=y
|
||||
@ -43,6 +44,8 @@ CONFIG_ARCH_HI3xxx=y
|
||||
CONFIG_ARCH_HIP01=y
|
||||
CONFIG_ARCH_HIP04=y
|
||||
CONFIG_ARCH_HIX5HD2=y
|
||||
CONFIG_ARCH_HPE=y
|
||||
CONFIG_ARCH_HPE_GXP=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_SOC_IMX50=y
|
||||
CONFIG_SOC_IMX51=y
|
||||
@ -277,6 +280,7 @@ CONFIG_MV643XX_ETH=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_PXA168_ETH=m
|
||||
CONFIG_KS8851=y
|
||||
CONFIG_LAN966X_SWITCH=m
|
||||
CONFIG_R8169=y
|
||||
CONFIG_SH_ETH=y
|
||||
CONFIG_SMSC911X=y
|
||||
@ -287,6 +291,7 @@ CONFIG_TI_CPSW=y
|
||||
CONFIG_TI_CPSW_SWITCHDEV=y
|
||||
CONFIG_TI_CPTS=y
|
||||
CONFIG_XILINX_EMACLITE=y
|
||||
CONFIG_SFP=m
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
@ -294,6 +299,7 @@ CONFIG_AT803X_PHY=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_DP83867_PHY=y
|
||||
CONFIG_USB_BRCMSTB=m
|
||||
CONFIG_MDIO_MSCC_MIIM=m
|
||||
CONFIG_USB_PEGASUS=y
|
||||
CONFIG_USB_RTL8152=m
|
||||
CONFIG_USB_LAN78XX=m
|
||||
@ -430,6 +436,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=m
|
||||
CONFIG_I2C_SLAVE_EEPROM=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_ATMEL=m
|
||||
CONFIG_SPI_ATMEL_QUADSPI=m
|
||||
CONFIG_SPI_BCM2835=y
|
||||
CONFIG_SPI_BCM2835AUX=y
|
||||
CONFIG_SPI_CADENCE=y
|
||||
@ -459,6 +466,8 @@ CONFIG_SPMI=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_PINCTRL_AS3722=y
|
||||
CONFIG_PINCTRL_STMFX=y
|
||||
CONFIG_PINCTRL_MICROCHIP_SGPIO=y
|
||||
CONFIG_PINCTRL_OCELOT=y
|
||||
CONFIG_PINCTRL_PALMAS=y
|
||||
CONFIG_PINCTRL_OWL=y
|
||||
CONFIG_PINCTRL_S500=y
|
||||
@ -517,6 +526,7 @@ CONFIG_CHARGER_TPS65090=y
|
||||
CONFIG_SENSORS_ARM_SCMI=y
|
||||
CONFIG_SENSORS_ASPEED=m
|
||||
CONFIG_SENSORS_IIO_HWMON=y
|
||||
CONFIG_SENSORS_LAN966X=m
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM95245=y
|
||||
CONFIG_SENSORS_NTC_THERMISTOR=m
|
||||
@ -563,6 +573,7 @@ CONFIG_BCM47XX_WDT=y
|
||||
CONFIG_BCM2835_WDT=y
|
||||
CONFIG_BCM_KONA_WDT=y
|
||||
CONFIG_BCM7038_WDT=m
|
||||
CONFIG_GXP_WATCHDOG=y
|
||||
CONFIG_BCMA_HOST_SOC=y
|
||||
CONFIG_BCMA_DRIVER_GMAC_CMN=y
|
||||
CONFIG_BCMA_DRIVER_GPIO=y
|
||||
@ -767,6 +778,8 @@ CONFIG_SND_ATMEL_SOC_WM8904=m
|
||||
CONFIG_SND_ATMEL_SOC_PDMIC=m
|
||||
CONFIG_SND_ATMEL_SOC_I2S=m
|
||||
CONFIG_SND_BCM2835_SOC_I2S=m
|
||||
CONFIG_SND_IMX_SOC=m
|
||||
CONFIG_SND_SOC_FSL_ASOC_CARD=m
|
||||
CONFIG_SND_SOC_FSL_SAI=m
|
||||
CONFIG_SND_PXA_SOC_SSP=m
|
||||
CONFIG_SND_MMP_SOC_SSPA=m
|
||||
@ -1018,6 +1031,7 @@ CONFIG_CROS_EC_SPI=m
|
||||
CONFIG_COMMON_CLK_MAX77686=y
|
||||
CONFIG_COMMON_CLK_RK808=m
|
||||
CONFIG_COMMON_CLK_SCMI=y
|
||||
CONFIG_COMMON_CLK_LAN966X=y
|
||||
CONFIG_COMMON_CLK_S2MPS11=m
|
||||
CONFIG_CLK_RASPBERRYPI=y
|
||||
CONFIG_COMMON_CLK_QCOM=y
|
||||
@ -1145,6 +1159,7 @@ CONFIG_PWM_SUN4I=y
|
||||
CONFIG_PWM_TEGRA=y
|
||||
CONFIG_PWM_VT8500=y
|
||||
CONFIG_KEYSTONE_IRQ=y
|
||||
CONFIG_RESET_MCHP_SPARX5=y
|
||||
CONFIG_PHY_SUN4I_USB=y
|
||||
CONFIG_PHY_SUN9I_USB=y
|
||||
CONFIG_PHY_HIX5HD2_SATA=y
|
||||
@ -1152,6 +1167,7 @@ CONFIG_PHY_BERLIN_SATA=y
|
||||
CONFIG_PHY_BERLIN_USB=y
|
||||
CONFIG_PHY_BRCM_USB=m
|
||||
CONFIG_PHY_MMP3_USB=m
|
||||
CONFIG_PHY_LAN966X_SERDES=m
|
||||
CONFIG_PHY_CPCAP_USB=m
|
||||
CONFIG_PHY_QCOM_APQ8064_SATA=m
|
||||
CONFIG_PHY_QCOM_USB_HS=y
|
||||
|
||||
@ -219,7 +219,7 @@ config SOC_SAMA5
|
||||
select SRAM if PM
|
||||
|
||||
config ATMEL_PM
|
||||
bool "Atmel PM support"
|
||||
bool
|
||||
|
||||
config ATMEL_SECURE_PM
|
||||
bool "Atmel Secure PM support"
|
||||
|
||||
@ -345,9 +345,10 @@ static struct clk_hw *clk_hw_register_ddiv(const char *name,
|
||||
psc->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &psc->hw);
|
||||
if (IS_ERR(clk))
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(psc);
|
||||
|
||||
return ERR_CAST(clk);
|
||||
}
|
||||
return &psc->hw;
|
||||
}
|
||||
|
||||
@ -452,9 +453,10 @@ static struct clk_hw *clk_hw_register_div(const char *name,
|
||||
psc->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &psc->hw);
|
||||
if (IS_ERR(clk))
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(psc);
|
||||
|
||||
return ERR_CAST(clk);
|
||||
}
|
||||
return &psc->hw;
|
||||
}
|
||||
|
||||
|
||||
@ -150,7 +150,7 @@ static struct platform_device ts72xx_nand_flash = {
|
||||
.num_resources = ARRAY_SIZE(ts72xx_nand_resource),
|
||||
};
|
||||
|
||||
void __init ts72xx_register_flash(struct mtd_partition *parts, int n,
|
||||
static void __init ts72xx_register_flash(struct mtd_partition *parts, int n,
|
||||
resource_size_t start)
|
||||
{
|
||||
/*
|
||||
|
||||
23
arch/arm/mach-hpe/Kconfig
Normal file
23
arch/arm/mach-hpe/Kconfig
Normal file
@ -0,0 +1,23 @@
|
||||
menuconfig ARCH_HPE
|
||||
bool "HPE SoC support"
|
||||
depends on ARCH_MULTI_V7
|
||||
help
|
||||
This enables support for HPE ARM based BMC chips.
|
||||
if ARCH_HPE
|
||||
|
||||
config ARCH_HPE_GXP
|
||||
bool "HPE GXP SoC"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARM_VIC
|
||||
select GENERIC_IRQ_CHIP
|
||||
select CLKSRC_MMIO
|
||||
help
|
||||
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
|
||||
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
|
||||
A9 core. It is capable of using an AXI bus to which a memory controller
|
||||
is attached. It has multiple SPI interfaces to connect boot flash and
|
||||
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
|
||||
has multiple i2c engines to drive connectivity with a host
|
||||
infrastructure.
|
||||
|
||||
endif
|
||||
1
arch/arm/mach-hpe/Makefile
Normal file
1
arch/arm/mach-hpe/Makefile
Normal file
@ -0,0 +1 @@
|
||||
obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o
|
||||
16
arch/arm/mach-hpe/gxp.c
Normal file
16
arch/arm/mach-hpe/gxp.c
Normal file
@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static const char * const gxp_board_dt_compat[] = {
|
||||
"hpe,gxp",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(GXP_DT, "HPE GXP")
|
||||
.dt_compat = gxp_board_dt_compat,
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
MACHINE_END
|
||||
@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
|
||||
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
|
||||
socfpga_agilex_socdk.dtb \
|
||||
socfpga_agilex_socdk_nand.dtb \
|
||||
socfpga_n5x_socdk.dtb
|
||||
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
|
||||
|
||||
66
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
Normal file
66
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
Normal file
@ -0,0 +1,66 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021-2022, Intel Corporation
|
||||
*/
|
||||
#include "socfpga_agilex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SoCFPGA Agilex n6000";
|
||||
compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart0;
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
ethernet2 = &gmac2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
/* We expect the bootloader to fill in the reg */
|
||||
reg = <0 0 0 0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
bus@80000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x80000000 0x60000000>,
|
||||
<0xf9000000 0x00100000>;
|
||||
reg-names = "axi_h2f", "axi_h2f_lw";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
|
||||
|
||||
dma-controller@0 {
|
||||
compatible = "intel,hps-copy-engine";
|
||||
reg = <0x00000000 0x00000000 0x00001000>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&osc1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpga_mgr {
|
||||
status = "disabled";
|
||||
};
|
||||
@ -745,10 +745,11 @@
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0x0 0xff500000 0x0 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_RTC32K>;
|
||||
assigned-clock-rates = <32768>;
|
||||
};
|
||||
|
||||
@ -747,6 +747,8 @@
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3368-cru";
|
||||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -652,8 +652,8 @@
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
clocks = <&rk817 1>;
|
||||
clock-names = "lpo";
|
||||
device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
|
||||
|
||||
@ -397,6 +397,8 @@
|
||||
cru: clock-controller@fdd20000 {
|
||||
compatible = "rockchip,rk3568-cru";
|
||||
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
|
||||
@ -126,7 +126,9 @@
|
||||
reg = <0 0x20100000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <32>;
|
||||
dma-channels = <32>;
|
||||
clock-names = "enable";
|
||||
clocks = <&apahb_gate CLK_DMA_EB>;
|
||||
};
|
||||
@ -272,7 +274,9 @@
|
||||
compatible = "sprd,sc9860-dma";
|
||||
reg = <0 0x41580000 0 0x4000>;
|
||||
#dma-cells = <1>;
|
||||
/* For backwards compatibility: */
|
||||
#dma-channels = <32>;
|
||||
dma-channels = <32>;
|
||||
clock-names = "enable", "ashb_eb";
|
||||
clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
|
||||
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
|
||||
|
||||
@ -597,6 +597,14 @@ config CLKSRC_ST_LPC
|
||||
Enable this option to use the Low Power controller timer
|
||||
as clocksource.
|
||||
|
||||
config GXP_TIMER
|
||||
bool "GXP timer driver" if COMPILE_TEST && !ARCH_HPE
|
||||
default ARCH_HPE
|
||||
select TIMER_OF if OF
|
||||
help
|
||||
Provides a driver for the timer control found on HPE
|
||||
GXP SOCs. This is required for all GXP SOCs.
|
||||
|
||||
config RISCV_TIMER
|
||||
bool "Timer for the RISC-V platform" if COMPILE_TEST
|
||||
depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI
|
||||
|
||||
@ -86,3 +86,4 @@ obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
|
||||
obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o
|
||||
obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o
|
||||
obj-$(CONFIG_GOLDFISH_TIMER) += timer-goldfish.o
|
||||
obj-$(CONFIG_GXP_TIMER) += timer-gxp.o
|
||||
|
||||
209
drivers/clocksource/timer-gxp.c
Normal file
209
drivers/clocksource/timer-gxp.c
Normal file
@ -0,0 +1,209 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
#define TIMER0_FREQ 1000000
|
||||
#define GXP_TIMER_CNT_OFS 0x00
|
||||
#define GXP_TIMESTAMP_OFS 0x08
|
||||
#define GXP_TIMER_CTRL_OFS 0x14
|
||||
|
||||
/* TCS Stands for Timer Control/Status: these are masks to be used in */
|
||||
/* the Timer Count Registers */
|
||||
#define MASK_TCS_ENABLE 0x01
|
||||
#define MASK_TCS_PERIOD 0x02
|
||||
#define MASK_TCS_RELOAD 0x04
|
||||
#define MASK_TCS_TC 0x80
|
||||
|
||||
struct gxp_timer {
|
||||
void __iomem *counter;
|
||||
void __iomem *control;
|
||||
struct clock_event_device evt;
|
||||
};
|
||||
|
||||
static struct gxp_timer *gxp_timer;
|
||||
|
||||
static void __iomem *system_clock __ro_after_init;
|
||||
|
||||
static inline struct gxp_timer *to_gxp_timer(struct clock_event_device *evt_dev)
|
||||
{
|
||||
return container_of(evt_dev, struct gxp_timer, evt);
|
||||
}
|
||||
|
||||
static u64 notrace gxp_sched_read(void)
|
||||
{
|
||||
return readl_relaxed(system_clock);
|
||||
}
|
||||
|
||||
static int gxp_time_set_next_event(unsigned long event, struct clock_event_device *evt_dev)
|
||||
{
|
||||
struct gxp_timer *timer = to_gxp_timer(evt_dev);
|
||||
|
||||
/* Stop counting and disable interrupt before updating */
|
||||
writeb_relaxed(MASK_TCS_TC, timer->control);
|
||||
writel_relaxed(event, timer->counter);
|
||||
writeb_relaxed(MASK_TCS_TC | MASK_TCS_ENABLE, timer->control);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t gxp_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct gxp_timer *timer = (struct gxp_timer *)dev_id;
|
||||
|
||||
if (!(readb_relaxed(timer->control) & MASK_TCS_TC))
|
||||
return IRQ_NONE;
|
||||
|
||||
writeb_relaxed(MASK_TCS_TC, timer->control);
|
||||
|
||||
timer->evt.event_handler(&timer->evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __init gxp_timer_init(struct device_node *node)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
u32 freq;
|
||||
int ret, irq;
|
||||
|
||||
gxp_timer = kzalloc(sizeof(*gxp_timer), GFP_KERNEL);
|
||||
if (!gxp_timer) {
|
||||
ret = -ENOMEM;
|
||||
pr_err("Can't allocate gxp_timer");
|
||||
return ret;
|
||||
}
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
ret = (int)PTR_ERR(clk);
|
||||
pr_err("%pOFn clock not found: %d\n", node, ret);
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
pr_err("%pOFn clock enable failed: %d\n", node, ret);
|
||||
goto err_clk_enable;
|
||||
}
|
||||
|
||||
base = of_iomap(node, 0);
|
||||
if (!base) {
|
||||
ret = -ENXIO;
|
||||
pr_err("Can't map timer base registers");
|
||||
goto err_iomap;
|
||||
}
|
||||
|
||||
/* Set the offsets to the clock register and timer registers */
|
||||
gxp_timer->counter = base + GXP_TIMER_CNT_OFS;
|
||||
gxp_timer->control = base + GXP_TIMER_CTRL_OFS;
|
||||
system_clock = base + GXP_TIMESTAMP_OFS;
|
||||
|
||||
gxp_timer->evt.name = node->name;
|
||||
gxp_timer->evt.rating = 300;
|
||||
gxp_timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
|
||||
gxp_timer->evt.set_next_event = gxp_time_set_next_event;
|
||||
gxp_timer->evt.cpumask = cpumask_of(0);
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (irq <= 0) {
|
||||
ret = -EINVAL;
|
||||
pr_err("GXP Timer Can't parse IRQ %d", irq);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
freq = clk_get_rate(clk);
|
||||
|
||||
ret = clocksource_mmio_init(system_clock, node->name, freq,
|
||||
300, 32, clocksource_mmio_readl_up);
|
||||
if (ret) {
|
||||
pr_err("%pOFn init clocksource failed: %d", node, ret);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
sched_clock_register(gxp_sched_read, 32, freq);
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (irq <= 0) {
|
||||
ret = -EINVAL;
|
||||
pr_err("%pOFn Can't parse IRQ %d", node, irq);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
clockevents_config_and_register(&gxp_timer->evt, TIMER0_FREQ,
|
||||
0xf, 0xffffffff);
|
||||
|
||||
ret = request_irq(irq, gxp_timer_interrupt, IRQF_TIMER | IRQF_SHARED,
|
||||
node->name, gxp_timer);
|
||||
if (ret) {
|
||||
pr_err("%pOFn request_irq() failed: %d", node, ret);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
pr_debug("gxp: system timer (irq = %d)\n", irq);
|
||||
return 0;
|
||||
|
||||
err_exit:
|
||||
iounmap(base);
|
||||
err_iomap:
|
||||
clk_disable_unprepare(clk);
|
||||
err_clk_enable:
|
||||
clk_put(clk);
|
||||
err_free:
|
||||
kfree(gxp_timer);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This probe gets called after the timer is already up and running. This will create
|
||||
* the watchdog device as a child since the registers are shared.
|
||||
*/
|
||||
|
||||
static int gxp_timer_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct platform_device *gxp_watchdog_device;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
if (!gxp_timer) {
|
||||
pr_err("Gxp Timer not initialized, cannot create watchdog");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
gxp_watchdog_device = platform_device_alloc("gxp-wdt", -1);
|
||||
if (!gxp_watchdog_device) {
|
||||
pr_err("Timer failed to allocate gxp-wdt");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Pass the base address (counter) as platform data and nothing else */
|
||||
gxp_watchdog_device->dev.platform_data = gxp_timer->counter;
|
||||
gxp_watchdog_device->dev.parent = dev;
|
||||
|
||||
return platform_device_add(gxp_watchdog_device);
|
||||
}
|
||||
|
||||
static const struct of_device_id gxp_timer_of_match[] = {
|
||||
{ .compatible = "hpe,gxp-timer", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver gxp_timer_driver = {
|
||||
.probe = gxp_timer_probe,
|
||||
.driver = {
|
||||
.name = "gxp-timer",
|
||||
.of_match_table = gxp_timer_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(gxp_timer_driver);
|
||||
|
||||
TIMER_OF_DECLARE(gxp, "hpe,gxp-timer", gxp_timer_init);
|
||||
@ -459,7 +459,7 @@ static const struct of_device_id ixp4xx_qmgr_of_match[] = {
|
||||
static struct platform_driver ixp4xx_qmgr_driver = {
|
||||
.driver = {
|
||||
.name = "ixp4xx-qmgr",
|
||||
.of_match_table = of_match_ptr(ixp4xx_qmgr_of_match),
|
||||
.of_match_table = ixp4xx_qmgr_of_match,
|
||||
},
|
||||
.probe = ixp4xx_qmgr_probe,
|
||||
.remove = ixp4xx_qmgr_remove,
|
||||
|
||||
@ -165,12 +165,14 @@ static int __init rockchip_grf_init(void)
|
||||
return -ENODEV;
|
||||
if (!match || !match->data) {
|
||||
pr_err("%s: missing grf data\n", __func__);
|
||||
of_node_put(np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
grf_info = match->data;
|
||||
|
||||
grf = syscon_node_to_regmap(np);
|
||||
of_node_put(np);
|
||||
if (IS_ERR(grf)) {
|
||||
pr_err("%s: could not get grf syscon\n", __func__);
|
||||
return PTR_ERR(grf);
|
||||
|
||||
@ -512,7 +512,7 @@ int optee_check_mem_type(unsigned long start, size_t num_pages)
|
||||
* Allow kernel address to register with OP-TEE as kernel
|
||||
* pages are configured as normal memory only.
|
||||
*/
|
||||
if (virt_addr_valid(start) || is_vmalloc_addr((void *)start))
|
||||
if (virt_addr_valid((void *)start) || is_vmalloc_addr((void *)start))
|
||||
return 0;
|
||||
|
||||
mmap_read_lock(mm);
|
||||
|
||||
@ -1839,6 +1839,17 @@ config RALINK_WDT
|
||||
help
|
||||
Hardware driver for the Ralink SoC Watchdog Timer.
|
||||
|
||||
config GXP_WATCHDOG
|
||||
tristate "HPE GXP watchdog support"
|
||||
depends on ARCH_HPE_GXP
|
||||
select WATCHDOG_CORE
|
||||
help
|
||||
Say Y here to include support for the watchdog timer
|
||||
in HPE GXP SoCs.
|
||||
|
||||
To compile this driver as a module, choose M here.
|
||||
The module will be called gxp-wdt.
|
||||
|
||||
config MT7621_WDT
|
||||
tristate "Mediatek SoC watchdog"
|
||||
select WATCHDOG_CORE
|
||||
|
||||
@ -93,6 +93,7 @@ obj-$(CONFIG_RTD119X_WATCHDOG) += rtd119x_wdt.o
|
||||
obj-$(CONFIG_SPRD_WATCHDOG) += sprd_wdt.o
|
||||
obj-$(CONFIG_PM8916_WATCHDOG) += pm8916_wdt.o
|
||||
obj-$(CONFIG_ARM_SMC_WATCHDOG) += arm_smc_wdt.o
|
||||
obj-$(CONFIG_GXP_WATCHDOG) += gxp-wdt.o
|
||||
obj-$(CONFIG_VISCONTI_WATCHDOG) += visconti_wdt.o
|
||||
obj-$(CONFIG_MSC313E_WATCHDOG) += msc313e_wdt.o
|
||||
obj-$(CONFIG_APPLE_WATCHDOG) += apple_wdt.o
|
||||
|
||||
174
drivers/watchdog/gxp-wdt.c
Normal file
174
drivers/watchdog/gxp-wdt.c
Normal file
@ -0,0 +1,174 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/watchdog.h>
|
||||
|
||||
#define MASK_WDGCS_ENABLE 0x01
|
||||
#define MASK_WDGCS_RELOAD 0x04
|
||||
#define MASK_WDGCS_NMIEN 0x08
|
||||
#define MASK_WDGCS_WARN 0x80
|
||||
|
||||
#define WDT_MAX_TIMEOUT_MS 655350
|
||||
#define WDT_DEFAULT_TIMEOUT 30
|
||||
#define SECS_TO_WDOG_TICKS(x) ((x) * 100)
|
||||
#define WDOG_TICKS_TO_SECS(x) ((x) / 100)
|
||||
|
||||
#define GXP_WDT_CNT_OFS 0x10
|
||||
#define GXP_WDT_CTRL_OFS 0x16
|
||||
|
||||
struct gxp_wdt {
|
||||
void __iomem *base;
|
||||
struct watchdog_device wdd;
|
||||
};
|
||||
|
||||
static void gxp_wdt_enable_reload(struct gxp_wdt *drvdata)
|
||||
{
|
||||
u8 val;
|
||||
|
||||
val = readb(drvdata->base + GXP_WDT_CTRL_OFS);
|
||||
val |= (MASK_WDGCS_ENABLE | MASK_WDGCS_RELOAD);
|
||||
writeb(val, drvdata->base + GXP_WDT_CTRL_OFS);
|
||||
}
|
||||
|
||||
static int gxp_wdt_start(struct watchdog_device *wdd)
|
||||
{
|
||||
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
|
||||
|
||||
writew(SECS_TO_WDOG_TICKS(wdd->timeout), drvdata->base + GXP_WDT_CNT_OFS);
|
||||
gxp_wdt_enable_reload(drvdata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gxp_wdt_stop(struct watchdog_device *wdd)
|
||||
{
|
||||
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
|
||||
u8 val;
|
||||
|
||||
val = readb_relaxed(drvdata->base + GXP_WDT_CTRL_OFS);
|
||||
val &= ~MASK_WDGCS_ENABLE;
|
||||
writeb(val, drvdata->base + GXP_WDT_CTRL_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gxp_wdt_set_timeout(struct watchdog_device *wdd,
|
||||
unsigned int timeout)
|
||||
{
|
||||
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
|
||||
u32 actual;
|
||||
|
||||
wdd->timeout = timeout;
|
||||
actual = min(timeout * 100, wdd->max_hw_heartbeat_ms / 10);
|
||||
writew(actual, drvdata->base + GXP_WDT_CNT_OFS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int gxp_wdt_get_timeleft(struct watchdog_device *wdd)
|
||||
{
|
||||
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
|
||||
u32 val = readw(drvdata->base + GXP_WDT_CNT_OFS);
|
||||
|
||||
return WDOG_TICKS_TO_SECS(val);
|
||||
}
|
||||
|
||||
static int gxp_wdt_ping(struct watchdog_device *wdd)
|
||||
{
|
||||
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
|
||||
|
||||
gxp_wdt_enable_reload(drvdata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gxp_restart(struct watchdog_device *wdd, unsigned long action,
|
||||
void *data)
|
||||
{
|
||||
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
|
||||
|
||||
writew(1, drvdata->base + GXP_WDT_CNT_OFS);
|
||||
gxp_wdt_enable_reload(drvdata);
|
||||
mdelay(100);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct watchdog_ops gxp_wdt_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.start = gxp_wdt_start,
|
||||
.stop = gxp_wdt_stop,
|
||||
.ping = gxp_wdt_ping,
|
||||
.set_timeout = gxp_wdt_set_timeout,
|
||||
.get_timeleft = gxp_wdt_get_timeleft,
|
||||
.restart = gxp_restart,
|
||||
};
|
||||
|
||||
static const struct watchdog_info gxp_wdt_info = {
|
||||
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
|
||||
.identity = "HPE GXP Watchdog timer",
|
||||
};
|
||||
|
||||
static int gxp_wdt_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct gxp_wdt *drvdata;
|
||||
int err;
|
||||
u8 val;
|
||||
|
||||
drvdata = devm_kzalloc(dev, sizeof(struct gxp_wdt), GFP_KERNEL);
|
||||
if (!drvdata)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* The register area where the timer and watchdog reside is disarranged.
|
||||
* Hence mapping individual register blocks for the timer and watchdog
|
||||
* is not recommended as they would have access to each others
|
||||
* registers. Based on feedback the watchdog is no longer part of the
|
||||
* device tree file and the timer driver now creates the watchdog as a
|
||||
* child device. During the watchdogs creation, the timer driver passes
|
||||
* the base address to the watchdog over the private interface.
|
||||
*/
|
||||
|
||||
drvdata->base = (void __iomem *)dev->platform_data;
|
||||
|
||||
drvdata->wdd.info = &gxp_wdt_info;
|
||||
drvdata->wdd.ops = &gxp_wdt_ops;
|
||||
drvdata->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
|
||||
drvdata->wdd.parent = dev;
|
||||
drvdata->wdd.timeout = WDT_DEFAULT_TIMEOUT;
|
||||
|
||||
watchdog_set_drvdata(&drvdata->wdd, drvdata);
|
||||
watchdog_set_nowayout(&drvdata->wdd, WATCHDOG_NOWAYOUT);
|
||||
|
||||
val = readb(drvdata->base + GXP_WDT_CTRL_OFS);
|
||||
|
||||
if (val & MASK_WDGCS_ENABLE)
|
||||
set_bit(WDOG_HW_RUNNING, &drvdata->wdd.status);
|
||||
|
||||
watchdog_set_restart_priority(&drvdata->wdd, 128);
|
||||
|
||||
watchdog_stop_on_reboot(&drvdata->wdd);
|
||||
err = devm_watchdog_register_device(dev, &drvdata->wdd);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed to register watchdog device");
|
||||
return err;
|
||||
}
|
||||
|
||||
dev_info(dev, "HPE GXP watchdog timer");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver gxp_wdt_driver = {
|
||||
.probe = gxp_wdt_probe,
|
||||
.driver = {
|
||||
.name = "gxp-wdt",
|
||||
},
|
||||
};
|
||||
module_platform_driver(gxp_wdt_driver);
|
||||
|
||||
MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>");
|
||||
MODULE_AUTHOR("Jean-Marie Verdun <verdun@hpe.com>");
|
||||
MODULE_DESCRIPTION("Driver for GXP watchdog timer");
|
||||
Loading…
Reference in New Issue
Block a user