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pwm: Add Allwinner SoC support
This adds a generic PWM framework driver for the PWM controller found on Allwinner SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Alexandre Belloni
Thierry Reding
parent
df6922adec
commit
09853ce7bc
@ -284,6 +284,16 @@ config PWM_STI
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To compile this driver as a module, choose M here: the module
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will be called pwm-sti.
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config PWM_SUN4I
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tristate "Allwinner PWM support"
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depends on ARCH_SUNXI || COMPILE_TEST
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depends on HAS_IOMEM && COMMON_CLK
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help
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Generic PWM framework driver for Allwinner SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sun4i.
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config PWM_TEGRA
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tristate "NVIDIA Tegra PWM support"
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depends on ARCH_TEGRA
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@ -26,6 +26,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_STI) += pwm-sti.o
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obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
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obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
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obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
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obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
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366
drivers/pwm/pwm-sun4i.c
Normal file
366
drivers/pwm/pwm-sun4i.c
Normal file
@ -0,0 +1,366 @@
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/*
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* Driver for Allwinner sun4i Pulse Width Modulation Controller
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*
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* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
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*
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* Licensed under GPLv2.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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#define PWM_CTRL_REG 0x0
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#define PWM_CH_PRD_BASE 0x4
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#define PWM_CH_PRD_OFFSET 0x4
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#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
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#define PWMCH_OFFSET 15
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#define PWM_PRESCAL_MASK GENMASK(3, 0)
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#define PWM_PRESCAL_OFF 0
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#define PWM_EN BIT(4)
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#define PWM_ACT_STATE BIT(5)
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#define PWM_CLK_GATING BIT(6)
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#define PWM_MODE BIT(7)
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#define PWM_PULSE BIT(8)
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#define PWM_BYPASS BIT(9)
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#define PWM_RDY_BASE 28
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#define PWM_RDY_OFFSET 1
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#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
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#define PWM_PRD(prd) (((prd) - 1) << 16)
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#define PWM_PRD_MASK GENMASK(15, 0)
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#define PWM_DTY_MASK GENMASK(15, 0)
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#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
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static const u32 prescaler_table[] = {
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120,
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180,
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240,
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360,
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480,
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0,
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0,
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0,
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12000,
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24000,
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36000,
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48000,
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72000,
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0,
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0,
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0, /* Actually 1 but tested separately */
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};
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struct sun4i_pwm_data {
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bool has_prescaler_bypass;
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bool has_rdy;
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};
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struct sun4i_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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spinlock_t ctrl_lock;
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const struct sun4i_pwm_data *data;
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};
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static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct sun4i_pwm_chip, chip);
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}
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static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
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unsigned long offset)
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{
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return readl(chip->base + offset);
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}
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static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
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u32 val, unsigned long offset)
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{
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writel(val, chip->base + offset);
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}
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static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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u32 prd, dty, val, clk_gate;
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u64 clk_rate, div = 0;
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unsigned int prescaler = 0;
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int err;
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clk_rate = clk_get_rate(sun4i_pwm->clk);
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if (sun4i_pwm->data->has_prescaler_bypass) {
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/* First, test without any prescaler when available */
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prescaler = PWM_PRESCAL_MASK;
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/*
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* When not using any prescaler, the clock period in nanoseconds
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* is not an integer so round it half up instead of
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* truncating to get less surprising values.
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*/
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div = clk_rate * period_ns + NSEC_PER_SEC/2;
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do_div(div, NSEC_PER_SEC);
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if (div - 1 > PWM_PRD_MASK)
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prescaler = 0;
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}
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if (prescaler == 0) {
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/* Go up from the first divider */
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for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
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if (!prescaler_table[prescaler])
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continue;
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div = clk_rate;
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do_div(div, prescaler_table[prescaler]);
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div = div * period_ns;
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do_div(div, NSEC_PER_SEC);
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if (div - 1 <= PWM_PRD_MASK)
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break;
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}
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if (div - 1 > PWM_PRD_MASK) {
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dev_err(chip->dev, "period exceeds the maximum value\n");
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return -EINVAL;
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}
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}
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prd = div;
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div *= duty_ns;
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do_div(div, period_ns);
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dty = div;
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err = clk_prepare_enable(sun4i_pwm->clk);
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if (err) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return err;
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}
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spin_lock(&sun4i_pwm->ctrl_lock);
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
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spin_unlock(&sun4i_pwm->ctrl_lock);
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clk_disable_unprepare(sun4i_pwm->clk);
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return -EBUSY;
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}
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clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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if (clk_gate) {
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val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
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}
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
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val |= BIT_CH(prescaler, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
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val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
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if (clk_gate) {
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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val |= clk_gate;
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
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}
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spin_unlock(&sun4i_pwm->ctrl_lock);
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clk_disable_unprepare(sun4i_pwm->clk);
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return 0;
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}
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static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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u32 val;
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int ret;
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ret = clk_prepare_enable(sun4i_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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spin_lock(&sun4i_pwm->ctrl_lock);
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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if (polarity != PWM_POLARITY_NORMAL)
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val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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else
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val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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clk_disable_unprepare(sun4i_pwm->clk);
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return 0;
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}
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static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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u32 val;
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int ret;
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ret = clk_prepare_enable(sun4i_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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spin_lock(&sun4i_pwm->ctrl_lock);
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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val |= BIT_CH(PWM_EN, pwm->hwpwm);
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val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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return 0;
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}
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static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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u32 val;
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spin_lock(&sun4i_pwm->ctrl_lock);
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
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val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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clk_disable_unprepare(sun4i_pwm->clk);
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}
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static const struct pwm_ops sun4i_pwm_ops = {
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.config = sun4i_pwm_config,
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.set_polarity = sun4i_pwm_set_polarity,
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.enable = sun4i_pwm_enable,
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.disable = sun4i_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
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.has_prescaler_bypass = false,
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.has_rdy = false,
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};
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static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
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.has_prescaler_bypass = true,
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.has_rdy = true,
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};
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static const struct of_device_id sun4i_pwm_dt_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-pwm",
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.data = &sun4i_pwm_data_a10,
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}, {
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.compatible = "allwinner,sun7i-a20-pwm",
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.data = &sun4i_pwm_data_a20,
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}, {
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/* sentinel */
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},
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};
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MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
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static int sun4i_pwm_probe(struct platform_device *pdev)
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{
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struct sun4i_pwm_chip *pwm;
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struct resource *res;
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u32 val;
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int i, ret;
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const struct of_device_id *match;
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match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev);
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pwm->base))
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return PTR_ERR(pwm->base);
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pwm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pwm->clk))
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return PTR_ERR(pwm->clk);
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &sun4i_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = 2;
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pwm->chip.can_sleep = true;
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pwm->chip.of_xlate = of_pwm_xlate_with_flags;
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pwm->chip.of_pwm_n_cells = 3;
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pwm->data = match->data;
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spin_lock_init(&pwm->ctrl_lock);
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ret = pwmchip_add(&pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pwm);
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ret = clk_prepare_enable(pwm->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable PWM clock\n");
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goto clk_error;
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}
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val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
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for (i = 0; i < pwm->chip.npwm; i++)
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if (!(val & BIT_CH(PWM_ACT_STATE, i)))
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pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED;
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clk_disable_unprepare(pwm->clk);
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return 0;
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clk_error:
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pwmchip_remove(&pwm->chip);
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return ret;
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}
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static int sun4i_pwm_remove(struct platform_device *pdev)
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{
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struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
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return pwmchip_remove(&pwm->chip);
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}
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static struct platform_driver sun4i_pwm_driver = {
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.driver = {
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.name = "sun4i-pwm",
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.of_match_table = sun4i_pwm_dt_ids,
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},
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.probe = sun4i_pwm_probe,
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.remove = sun4i_pwm_remove,
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};
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module_platform_driver(sun4i_pwm_driver);
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MODULE_ALIAS("platform:sun4i-pwm");
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MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
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MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
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MODULE_LICENSE("GPL v2");
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