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dts: sun8i-h3: Add APB0 related clocks and resets

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APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.

After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Krzysztof Adamski 2016-02-22 14:03:26 +01:00 committed by Maxime Ripard
parent f9ca30440c
commit 097872945e
1 changed files with 25 additions and 0 deletions
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25
arch/arm/boot/dts/sun8i-h3.dtsi
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@ -276,6 +276,25 @@
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
apb0: apb0_clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&osc24M>;
clock-output-names = "apb0";
};
apb0_gates: clk@01f01428 {
compatible = "allwinner,sun8i-h3-apb0-gates-clk",
"allwinner,sun4i-a10-gates-clk";
reg = <0x01f01428 0x4>;
#clock-cells = <1>;
clocks = <&apb0>;
clock-indices = <0>, <1>;
clock-output-names = "apb0_pio", "apb0_ir";
};
};
soc {
@ -493,5 +512,11 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
apb0_reset: reset@01f014b0 {
reg = <0x01f014b0 0x4>;
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
};
};