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arm64: dts: qcom: ipq6018: Add pcie support

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ipq6018 has 1 pcie gen3 port. This patch adds the support for the same.

The GICv2m reg property value is a guess based on similar SoCs
description in downstream Codeaurora kernel. It appears to work.

Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
[baruch: adjust #address-cells/#size-cells; drop unsupported property;
 increase parf registers size]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Link: https://lore.kernel.org/r/0f733656666fa6adaa8e196419ebcfd04677d173.1620203062.git.baruch@tkos.co.il
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Selvam Sathappan Periakaruppan 2021-05-05 12:18:32 +03:00 committed by Bjorn Andersson
parent f70c6dc013
commit 095bbdd9a5
1 changed files with 99 additions and 0 deletions
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99
arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@ -384,6 +384,105 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pcie_phy: phy@84000 {
compatible = "qcom,ipq6018-qmp-pcie-phy";
reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>;
clock-names = "aux", "cfg_ahb";
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
pcie_phy0: lane@84200 {
reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
<0x0 0x84400 0x0 0x200>, /* Serdes Rx */
<0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_pcie0_pipe_clk_src";
#clock-cells = <0>;
};
};
pcie0: pci@20000000 {
compatible = "qcom,pcie-ipq6018";
reg = <0x0 0x20000000 0x0 0xf1d>,
<0x0 0x20000f20 0x0 0xa8>,
<0x0 0x20001000 0x0 0x1000>,
<0x0 0x80000 0x0 0x4000>,
<0x0 0x20100000 0x0 0x1000>;
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_phy0>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0 0x20200000
0 0x10000>, /* downstream I/O */
<0x82000000 0 0x20220000 0 0x20220000
0 0xfde0000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 75
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
<&gcc PCIE0_RCHNG_CLK>;
clock-names = "iface",
"axi_m",
"axi_s",
"axi_bridge",
"rchng";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_SLEEP_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
"axi_m_sticky",
"axi_s_sticky";
status = "disabled";
};
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;