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habanalabs/gaudi: Set DMA5 QMAN internal
DMA5 QMAN is designated to be used for reduction process, hence it will be no longer configured as external queue. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Ofir Bitton
Oded Gabbay
parent
5fe1c17ddf
commit
0940cabafd
@ -38,7 +38,7 @@
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*
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* MMU is always enabled.
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*
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* QMAN DMA channels 0,1,5 (PCI DMAN):
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* QMAN DMA channels 0,1 (PCI DMAN):
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* - DMA is not secured.
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* - PQ and CQ are secured.
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* - CP is secured: The driver needs to parse CB but WREG should be allowed
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@ -55,7 +55,7 @@
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* idle)
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* - MMU page tables area clear (happens on init)
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*
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* QMAN DMA 2-4,6,7, TPC, MME, NIC:
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* QMAN DMA 2-7, TPC, MME, NIC:
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* PQ is secured and is located on the Host (HBM CON TPC3 bug)
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* CQ, CP and the engine are not secured
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*
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@ -113,12 +113,12 @@ static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {
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static const u8 gaudi_dma_assignment[GAUDI_DMA_MAX] = {
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[GAUDI_PCI_DMA_1] = GAUDI_ENGINE_ID_DMA_0,
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[GAUDI_PCI_DMA_2] = GAUDI_ENGINE_ID_DMA_1,
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[GAUDI_PCI_DMA_3] = GAUDI_ENGINE_ID_DMA_5,
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[GAUDI_HBM_DMA_1] = GAUDI_ENGINE_ID_DMA_2,
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[GAUDI_HBM_DMA_2] = GAUDI_ENGINE_ID_DMA_3,
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[GAUDI_HBM_DMA_3] = GAUDI_ENGINE_ID_DMA_4,
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[GAUDI_HBM_DMA_4] = GAUDI_ENGINE_ID_DMA_6,
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[GAUDI_HBM_DMA_5] = GAUDI_ENGINE_ID_DMA_7
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[GAUDI_HBM_DMA_4] = GAUDI_ENGINE_ID_DMA_5,
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[GAUDI_HBM_DMA_5] = GAUDI_ENGINE_ID_DMA_6,
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[GAUDI_HBM_DMA_6] = GAUDI_ENGINE_ID_DMA_7
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};
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static const u8 gaudi_cq_assignment[NUMBER_OF_CMPLT_QUEUES] = {
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@ -130,10 +130,6 @@ static const u8 gaudi_cq_assignment[NUMBER_OF_CMPLT_QUEUES] = {
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[5] = GAUDI_QUEUE_ID_DMA_1_1,
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[6] = GAUDI_QUEUE_ID_DMA_1_2,
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[7] = GAUDI_QUEUE_ID_DMA_1_3,
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[8] = GAUDI_QUEUE_ID_DMA_5_0,
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[9] = GAUDI_QUEUE_ID_DMA_5_1,
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[10] = GAUDI_QUEUE_ID_DMA_5_2,
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[11] = GAUDI_QUEUE_ID_DMA_5_3
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};
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static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = {
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@ -249,10 +245,10 @@ static enum hl_queue_type gaudi_queue_type[GAUDI_QUEUE_ID_SIZE] = {
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_1 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_2 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_3 */
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QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_0 */
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QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_1 */
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QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_2 */
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QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_3 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_0 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_1 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_2 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_3 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_0 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_1 */
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QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_2 */
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@ -978,8 +974,7 @@ static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev)
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q = &gaudi->internal_qmans[i];
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switch (i) {
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case GAUDI_QUEUE_ID_DMA_2_0 ... GAUDI_QUEUE_ID_DMA_4_3:
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case GAUDI_QUEUE_ID_DMA_6_0 ... GAUDI_QUEUE_ID_DMA_7_3:
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case GAUDI_QUEUE_ID_DMA_2_0 ... GAUDI_QUEUE_ID_DMA_7_3:
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q->pq_size = HBM_DMA_QMAN_SIZE_IN_BYTES;
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break;
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case GAUDI_QUEUE_ID_MME_0_0 ... GAUDI_QUEUE_ID_MME_1_3:
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@ -3424,26 +3419,26 @@ static void gaudi_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
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break;
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case GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3:
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dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_3];
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dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
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q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
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db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
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break;
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case GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3:
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dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_4];
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dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
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q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
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db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
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break;
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case GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3:
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case GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3:
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dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_5];
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dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
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q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
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db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
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break;
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case GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3:
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dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_6];
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dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
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q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
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db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
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break;
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case GAUDI_QUEUE_ID_CPU_PQ:
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if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q)
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db_reg_offset = mmCPU_IF_PF_PQ_PI;
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@ -15,7 +15,7 @@
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#include "../include/gaudi/gaudi.h"
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#include "../include/gaudi/gaudi_async_events.h"
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#define NUMBER_OF_EXT_HW_QUEUES 12
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#define NUMBER_OF_EXT_HW_QUEUES 8
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#define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES
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#define NUMBER_OF_CPU_HW_QUEUES 1
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#define NUMBER_OF_INT_HW_QUEUES 100
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@ -62,8 +62,8 @@
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#error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
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#endif
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#define PCI_DMA_NUMBER_OF_CHNLS 3
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#define HBM_DMA_NUMBER_OF_CHNLS 5
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#define PCI_DMA_NUMBER_OF_CHNLS 2
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#define HBM_DMA_NUMBER_OF_CHNLS 6
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#define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \
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HBM_DMA_NUMBER_OF_CHNLS)
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@ -205,12 +205,12 @@
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enum gaudi_dma_channels {
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GAUDI_PCI_DMA_1,
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GAUDI_PCI_DMA_2,
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GAUDI_PCI_DMA_3,
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GAUDI_HBM_DMA_1,
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GAUDI_HBM_DMA_2,
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GAUDI_HBM_DMA_3,
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GAUDI_HBM_DMA_4,
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GAUDI_HBM_DMA_5,
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GAUDI_HBM_DMA_6,
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GAUDI_DMA_MAX
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};
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@ -18,8 +18,8 @@
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#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */
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#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */
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#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 48
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#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 24
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#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 32
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#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 16
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/*
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* Goya queue Numbering
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*
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@ -76,10 +76,10 @@ enum gaudi_queue_id {
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GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */
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GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */
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GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */
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GAUDI_QUEUE_ID_DMA_5_0 = 21, /* external */
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GAUDI_QUEUE_ID_DMA_5_1 = 22, /* external */
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GAUDI_QUEUE_ID_DMA_5_2 = 23, /* external */
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GAUDI_QUEUE_ID_DMA_5_3 = 24, /* external */
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GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */
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GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */
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GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */
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GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */
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GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */
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GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */
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GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */
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