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drm/bridge: tc358767: use more reliable seq when finishing LT

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At the end of the link training, two steps have to be taken: 1)
tc358767's LT mode is disabled by a write to DP0_SRCCTRL, and 2) Remove
LT flag in DPCD 0x102.

Toshiba's documentation tells to first write the DPCD, then modify
DP0_SRCCTRL. In my testing this often causes issues, and the link
disconnects right after those steps.

If I reverse the steps, it works every time. There's a chance that this
is DP sink specific, though, but as my testing shows this sequence to be
much more reliable, let's change it.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190528082747.3631-15-tomi.valkeinen@ti.com
This commit is contained in:
Tomi Valkeinen 2019-05-28 11:27:37 +03:00 committed by Andrzej Hajda
parent 31b4c8848a
commit 0776a269d7
1 changed files with 12 additions and 3 deletions
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15
drivers/gpu/drm/bridge/tc358767.c
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@ -961,6 +961,18 @@ static int tc_main_link_enable(struct tc_data *tc)
if (ret)
goto err;
/*
* Toshiba's documentation suggests to first clear DPCD 0x102, then
* clear the training pattern bit in DP0_SRCCTRL. Testing shows
* that the link sometimes drops if those steps are done in that order,
* but if the steps are done in reverse order, the link stays up.
*
* So we do the steps differently than documented here.
*/
/* Clear Training Pattern, set AutoCorrect Mode = 1 */
tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
/* Clear DPCD 0x102 */
/* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
@ -968,9 +980,6 @@ static int tc_main_link_enable(struct tc_data *tc)
if (ret < 0)
goto err_dpcd_write;
/* Clear Training Pattern, set AutoCorrect Mode = 1 */
tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
/* Wait */
timeout = 100;
do {