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clk: shmobile: div6: Make clock-output-names optional

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Renesas DIV6 clocks provide a single clock output.  Hence make the
"clock-output-names" DT property optional instead of mandatory. In case
the DT property is omitted the DT node name will be used.

Rename the variable "name" to "clk_name" to make the code more similar
with fixed-factor-clock.c, and to avoid a conflict with a nested local
variable while we're at it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Geert Uytterhoeven 2015-09-08 14:46:32 +02:00
parent 189d3a2976
commit 07705583e9
2 changed files with 7 additions and 10 deletions
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4
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
View File

@ -20,6 +20,10 @@ Required Properties:
clocks must be specified. For clocks with multiple parents, invalid clocks must be specified. For clocks with multiple parents, invalid
settings must be specified as "<0>". settings must be specified as "<0>".
- #clock-cells: Must be 0 - #clock-cells: Must be 0
Optional Properties:
- clock-output-names: The name of the clock as a free-form string - clock-output-names: The name of the clock as a free-form string

13
drivers/clk/shmobile/clk-div6.c
View File

@ -178,10 +178,9 @@ static void __init cpg_div6_clock_init(struct device_node *np)
const char **parent_names; const char **parent_names;
struct clk_init_data init; struct clk_init_data init;
struct div6_clock *clock; struct div6_clock *clock;
const char *name; const char *clk_name = np->name;
struct clk *clk; struct clk *clk;
unsigned int i; unsigned int i;
int ret;
clock = kzalloc(sizeof(*clock), GFP_KERNEL); clock = kzalloc(sizeof(*clock), GFP_KERNEL);
if (!clock) if (!clock)
@ -215,13 +214,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
/* Parse the DT properties. */ /* Parse the DT properties. */
ret = of_property_read_string(np, "clock-output-names", &name); of_property_read_string(np, "clock-output-names", &clk_name);
if (ret < 0) {
pr_err("%s: failed to get %s DIV6 clock output name\n",
__func__, np->name);
goto error;
}
for (i = 0, valid_parents = 0; i < num_parents; i++) { for (i = 0, valid_parents = 0; i < num_parents; i++) {
const char *name = of_clk_get_parent_name(np, i); const char *name = of_clk_get_parent_name(np, i);
@ -255,7 +248,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
} }
/* Register the clock. */ /* Register the clock. */
init.name = name; init.name = clk_name;
init.ops = &cpg_div6_clock_ops; init.ops = &cpg_div6_clock_ops;
init.flags = CLK_IS_BASIC; init.flags = CLK_IS_BASIC;
init.parent_names = parent_names; init.parent_names = parent_names;