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clk: shmobile: div6: Make clock-output-names optional
Renesas DIV6 clocks provide a single clock output. Hence make the "clock-output-names" DT property optional instead of mandatory. In case the DT property is omitted the DT node name will be used. Rename the variable "name" to "clk_name" to make the code more similar with fixed-factor-clock.c, and to avoid a conflict with a nested local variable while we're at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -20,6 +20,10 @@ Required Properties:
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clocks must be specified. For clocks with multiple parents, invalid
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settings must be specified as "<0>".
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- #clock-cells: Must be 0
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Optional Properties:
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- clock-output-names: The name of the clock as a free-form string
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@ -178,10 +178,9 @@ static void __init cpg_div6_clock_init(struct device_node *np)
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const char **parent_names;
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struct clk_init_data init;
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struct div6_clock *clock;
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const char *name;
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const char *clk_name = np->name;
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struct clk *clk;
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unsigned int i;
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int ret;
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock)
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@ -215,13 +214,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
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clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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/* Parse the DT properties. */
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ret = of_property_read_string(np, "clock-output-names", &name);
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if (ret < 0) {
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pr_err("%s: failed to get %s DIV6 clock output name\n",
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__func__, np->name);
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goto error;
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}
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of_property_read_string(np, "clock-output-names", &clk_name);
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for (i = 0, valid_parents = 0; i < num_parents; i++) {
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const char *name = of_clk_get_parent_name(np, i);
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@ -255,7 +248,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
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}
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/* Register the clock. */
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init.name = name;
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init.name = clk_name;
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init.ops = &cpg_div6_clock_ops;
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init.flags = CLK_IS_BASIC;
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init.parent_names = parent_names;
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