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iommu/tegra: smmu: Add device tree support for SMMU
The necessary info is expected to pass from DT. For more precise resource reservation, there shouldn't be any overlapping of register range between SMMU and MC. SMMU register offset needs to be calculated correctly, based on its register bank. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Hiroshi Doyu
Joerg Roedel
parent
4e0ee78f2a
commit
0760e8faa9
@ -0,0 +1,21 @@
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NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
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Required properties:
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- compatible : "nvidia,tegra30-smmu"
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- reg : Should contain 3 register banks(address and length) for each
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of the SMMU register blocks.
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- interrupts : Should contain MC General interrupt.
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- nvidia,#asids : # of ASIDs
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- dma-window : IOVA start address and length.
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- nvidia,ahb : phandle to the ahb bus connected to SMMU.
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Example:
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smmu {
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compatible = "nvidia,tegra30-smmu";
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reg = <0x7000f010 0x02c
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0x7000f1f0 0x010
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0x7000f228 0x05c>;
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nvidia,#asids = <4>; /* # of ASIDs */
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dma-window = <0 0x40000000>; /* IOVA start & length */
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nvidia,ahb = <&ahb>;
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};
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@ -158,7 +158,7 @@ config TEGRA_IOMMU_GART
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config TEGRA_IOMMU_SMMU
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bool "Tegra SMMU IOMMU Support"
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depends on ARCH_TEGRA_3x_SOC
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depends on ARCH_TEGRA_3x_SOC && TEGRA_AHB
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select IOMMU_API
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help
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Enables support for remapping discontiguous physical memory
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@ -30,12 +30,15 @@
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#include <linux/sched.h>
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#include <linux/iommu.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_iommu.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <mach/iomap.h>
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#include <mach/smmu.h>
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#include <mach/tegra-ahb.h>
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/* bitmap of the page sizes currently supported */
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#define SMMU_IOMMU_PGSIZES (SZ_4K)
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@ -111,12 +114,6 @@
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#define SMMU_PDE_NEXT_SHIFT 28
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/* AHB Arbiter Registers */
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#define AHB_XBAR_CTRL 0xe0
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#define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE 1
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#define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT 17
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#define SMMU_NUM_ASIDS 4
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#define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
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#define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
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#define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
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@ -136,6 +133,7 @@
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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#define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
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@ -177,6 +175,8 @@
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#define SMMU_ASID_DISABLE 0
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#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
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#define NUM_SMMU_REG_BANKS 3
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#define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
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#define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
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#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
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@ -235,7 +235,7 @@ struct smmu_as {
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* Per SMMU device - IOMMU device
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*/
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struct smmu_device {
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void __iomem *regs, *regs_ahbarb;
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void __iomem *regs[NUM_SMMU_REG_BANKS];
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unsigned long iovmm_base; /* remappable base address */
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unsigned long page_count; /* total remappable size */
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spinlock_t lock;
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@ -252,29 +252,47 @@ struct smmu_device {
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unsigned long translation_enable_1;
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unsigned long translation_enable_2;
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unsigned long asid_security;
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struct device_node *ahb;
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};
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static struct smmu_device *smmu_handle; /* unique for a system */
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/*
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* SMMU/AHB register accessors
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* SMMU register accessors
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*/
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static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
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{
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return readl(smmu->regs + offs);
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}
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static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
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{
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writel(val, smmu->regs + offs);
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BUG_ON(offs < 0x10);
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if (offs < 0x3c)
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return readl(smmu->regs[0] + offs - 0x10);
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BUG_ON(offs < 0x1f0);
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if (offs < 0x200)
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return readl(smmu->regs[1] + offs - 0x1f0);
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BUG_ON(offs < 0x228);
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if (offs < 0x284)
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return readl(smmu->regs[2] + offs - 0x228);
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BUG();
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}
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static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
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static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
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{
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return readl(smmu->regs_ahbarb + offs);
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}
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static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
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{
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writel(val, smmu->regs_ahbarb + offs);
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BUG_ON(offs < 0x10);
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if (offs < 0x3c) {
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writel(val, smmu->regs[0] + offs - 0x10);
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return;
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}
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BUG_ON(offs < 0x1f0);
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if (offs < 0x200) {
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writel(val, smmu->regs[1] + offs - 0x1f0);
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return;
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}
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BUG_ON(offs < 0x228);
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if (offs < 0x284) {
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writel(val, smmu->regs[2] + offs - 0x228);
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return;
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}
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BUG();
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}
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#define VA_PAGE_TO_PA(va, page) \
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@ -370,7 +388,7 @@ static void smmu_flush_regs(struct smmu_device *smmu, int enable)
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FLUSH_SMMU_REGS(smmu);
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}
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static void smmu_setup_regs(struct smmu_device *smmu)
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static int smmu_setup_regs(struct smmu_device *smmu)
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{
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int i;
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u32 val;
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@ -398,10 +416,7 @@ static void smmu_setup_regs(struct smmu_device *smmu)
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smmu_flush_regs(smmu, 1);
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val = ahb_read(smmu, AHB_XBAR_CTRL);
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val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
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AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
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ahb_write(smmu, val, AHB_XBAR_CTRL);
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return tegra_ahb_enable_smmu(smmu->ahb);
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}
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static void flush_ptc_and_tlb(struct smmu_device *smmu,
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@ -873,52 +888,72 @@ static int tegra_smmu_resume(struct device *dev)
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{
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struct smmu_device *smmu = dev_get_drvdata(dev);
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unsigned long flags;
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int err;
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spin_lock_irqsave(&smmu->lock, flags);
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smmu_setup_regs(smmu);
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err = smmu_setup_regs(smmu);
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spin_unlock_irqrestore(&smmu->lock, flags);
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return 0;
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return err;
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}
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static int tegra_smmu_probe(struct platform_device *pdev)
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{
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struct smmu_device *smmu;
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struct resource *regs, *regs2, *window;
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struct device *dev = &pdev->dev;
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int i, err = 0;
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int i, asids, err = 0;
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dma_addr_t base;
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size_t size;
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const void *prop;
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if (smmu_handle)
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return -EIO;
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BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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window = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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if (!regs || !regs2 || !window) {
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dev_err(dev, "No SMMU resources\n");
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return -ENODEV;
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}
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smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
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if (!smmu) {
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dev_err(dev, "failed to allocate smmu_device\n");
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return -ENOMEM;
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}
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smmu->dev = dev;
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smmu->num_as = SMMU_NUM_ASIDS;
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smmu->iovmm_base = (unsigned long)window->start;
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smmu->page_count = resource_size(window) >> SMMU_PAGE_SHIFT;
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smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
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smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
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resource_size(regs2));
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if (!smmu->regs || !smmu->regs_ahbarb) {
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dev_err(dev, "failed to remap SMMU registers\n");
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err = -ENXIO;
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goto fail;
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for (i = 0; i < ARRAY_SIZE(smmu->regs); i++) {
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res)
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return -ENODEV;
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smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
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if (!smmu->regs[i])
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return -EBUSY;
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}
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err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
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if (err)
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return -ENODEV;
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if (size & SMMU_PAGE_MASK)
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return -EINVAL;
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size >>= SMMU_PAGE_SHIFT;
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if (!size)
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return -EINVAL;
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prop = of_get_property(dev->of_node, "nvidia,#asids", NULL);
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if (!prop)
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return -ENODEV;
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asids = be32_to_cpup(prop);
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if (!asids)
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return -ENODEV;
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smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
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if (!smmu->ahb)
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return -ENODEV;
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smmu->dev = dev;
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smmu->num_as = asids;
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smmu->iovmm_base = base;
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smmu->page_count = size;
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smmu->translation_enable_0 = ~0;
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smmu->translation_enable_1 = ~0;
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smmu->translation_enable_2 = ~0;
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@ -945,7 +980,9 @@ static int tegra_smmu_probe(struct platform_device *pdev)
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INIT_LIST_HEAD(&as->client);
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}
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spin_lock_init(&smmu->lock);
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smmu_setup_regs(smmu);
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err = smmu_setup_regs(smmu);
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if (err)
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goto fail;
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platform_set_drvdata(pdev, smmu);
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smmu->avp_vector_page = alloc_page(GFP_KERNEL);
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@ -958,10 +995,6 @@ static int tegra_smmu_probe(struct platform_device *pdev)
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fail:
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if (smmu->avp_vector_page)
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__free_page(smmu->avp_vector_page);
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if (smmu->regs)
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devm_iounmap(dev, smmu->regs);
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if (smmu->regs_ahbarb)
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devm_iounmap(dev, smmu->regs_ahbarb);
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if (smmu && smmu->as) {
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for (i = 0; i < smmu->num_as; i++) {
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if (smmu->as[i].pdir_page) {
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@ -993,8 +1026,6 @@ static int tegra_smmu_remove(struct platform_device *pdev)
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__free_page(smmu->avp_vector_page);
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if (smmu->regs)
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devm_iounmap(dev, smmu->regs);
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if (smmu->regs_ahbarb)
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devm_iounmap(dev, smmu->regs_ahbarb);
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devm_kfree(dev, smmu);
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smmu_handle = NULL;
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return 0;
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@ -1005,6 +1036,14 @@ const struct dev_pm_ops tegra_smmu_pm_ops = {
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.resume = tegra_smmu_resume,
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};
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#ifdef CONFIG_OF
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static struct of_device_id tegra_smmu_of_match[] __devinitdata = {
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{ .compatible = "nvidia,tegra30-smmu", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
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#endif
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static struct platform_driver tegra_smmu_driver = {
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.probe = tegra_smmu_probe,
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.remove = tegra_smmu_remove,
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@ -1012,6 +1051,7 @@ static struct platform_driver tegra_smmu_driver = {
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.owner = THIS_MODULE,
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.name = "tegra-smmu",
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.pm = &tegra_smmu_pm_ops,
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.of_match_table = of_match_ptr(tegra_smmu_of_match),
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},
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};
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@ -1031,4 +1071,5 @@ module_exit(tegra_smmu_exit);
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MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
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MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
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MODULE_ALIAS("platform:tegra-smmu");
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MODULE_LICENSE("GPL v2");
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