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Reset controller updates for v5.15
Add support for the SC7280 PDC Global and RZ/G2L USB/PHY reset controllers, convert UniPhier glue device tree bindings to json-schema and remove a leftover mention of ZTE zx2967 from Kconfig. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCYSOy1BcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwKxPAQDYffSCcsiXIcZqwO8mpBspzw+R rWTqcUeszNXJtPY0rwD/VFs7ESt2RijkKPJeP6VV7VvJkmzaRhFDtLB3MdyG1Qk= =60wV -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmEnXuMACgkQmmx57+YA GNmunBAAv8XVaPA47KvXrsZ8Day6GI9j0EyQAYRvm7MkxD35lDBaooniPT/6bGNs cfz6oolZPAzBtomErZUnqCADYGNKCta+Egsp836GCiX85M1sooic9gmidJW0oywQ 98d+BNjNJDF42RmBdLGqsE4UA/lB/1CgiRKtxkeTDgORQ+UKwwC2CZRwIhyr2ku9 /YsokNOLETSRf7UxERfZVQDoCpCY8rHn9Yk5Ldjf1a3wSNpEFcxY08TtK8wAxw1x ZdnIVMbDX9P3Yowh5LayguXUwXX3ZSiJJKeIaqf4FGn+7e0ISyGX2LSRmsLEP1N/ gi0D3tS/C6GPiIIup92VAVgN60WwxPl7whwpon98ii7krY3LMr9BibqyL9QEkZF7 W64flH+HUqm6zzZC26d73Ub413Y5ndSBzcq8Q8nrcsj/lPfUv1xzQMKm0WVUymxU 7hIognQQCcVIdUk3Ht33wJ3MQOs4kgrQ/VdVqvNRlqE3JpWvd9X4L1D3eUXq9TWV 2nAQoDQC5LmdW8V1HiV4RKmWqQxdGBlIFXscwH8W4TmRLJXGHQbGi9M2sjch3ycr RY0INAN3WpjhI/2saJxkGBeP1HmyQnmxNkfYZLbcFAvStXkgCBI5PIaO0flhevFK K10jMPajFaojRZpkQTc9WOasyv8IGez0TrVIgA1WlJZE6BL+KoE= =/KnZ -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.15' of git://git.pengutronix.de/pza/linux into arm/drivers Reset controller updates for v5.15 Add support for the SC7280 PDC Global and RZ/G2L USB/PHY reset controllers, convert UniPhier glue device tree bindings to json-schema and remove a leftover mention of ZTE zx2967 from Kconfig. * tag 'reset-for-v5.15' of git://git.pengutronix.de/pza/linux: reset: simple: remove ZTE details in Kconfig help reset: renesas: Add RZ/G2L usbphy control driver dt-bindings: reset: Document RZ/G2L USBPHY Control bindings dt-bindings: reset: Convert UniPhier glue reset to json-schema reset: qcom: Add PDC Global reset signals for WPSS dt-bindings: reset: pdc: Add PDC Global bindings dt-bindings: reset: aoss: Add AOSS reset controller binding Link: https://lore.kernel.org/r/d42a75fc17ce718ef1b3fa4c5d3f5c7fb0bd2bc2.camel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
06779631d1
@ -21,6 +21,11 @@ properties:
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- const: "qcom,sc7180-aoss-cc"
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- const: "qcom,sdm845-aoss-cc"
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- description: on SC7280 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sc7280-aoss-cc"
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- const: "qcom,sdm845-aoss-cc"
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- description: on SDM845 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sdm845-aoss-cc"
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@ -21,6 +21,10 @@ properties:
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- const: "qcom,sc7180-pdc-global"
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- const: "qcom,sdm845-pdc-global"
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- description: on SC7280 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sc7280-pdc-global"
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- description: on SDM845 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sdm845-pdc-global"
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@ -0,0 +1,65 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L USBPHY Control
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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description:
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The RZ/G2L USBPHY Control mainly controls reset and power down of the
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USB/PHY.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
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- const: renesas,rzg2l-usbphy-ctrl
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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'#reset-cells':
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const: 1
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description: |
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The phandle's argument in the reset specifier is the PHY reset associated
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with the USB port.
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0 = Port 1 Phy reset
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1 = Port 2 Phy reset
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required:
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- compatible
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- reg
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- clocks
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- resets
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- power-domains
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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phyrst: usbphy-ctrl@11c40000 {
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compatible = "renesas,r9a07g044-usbphy-ctrl",
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"renesas,rzg2l-usbphy-ctrl";
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reg = <0x11c40000 0x10000>;
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clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
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resets = <&cpg R9A07G044_USB_PRESETN>;
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power-domains = <&cpg>;
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#reset-cells = <1>;
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};
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@ -0,0 +1,88 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier peripheral core reset in glue layer
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description: |
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Some peripheral core reset belongs to its own glue layer. Before using
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this core reset, it is necessary to control the clocks and resets to
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enable this layer. These clocks and resets should be described in each
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property.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro4-usb3-reset
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- socionext,uniphier-pro5-usb3-reset
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- socionext,uniphier-pxs2-usb3-reset
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- socionext,uniphier-ld20-usb3-reset
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- socionext,uniphier-pxs3-usb3-reset
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- socionext,uniphier-pro4-ahci-reset
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- socionext,uniphier-pxs2-ahci-reset
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- socionext,uniphier-pxs3-ahci-reset
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reg:
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maxItems: 1
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"#reset-cells":
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const: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items: # for Pro4, Pro5
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- const: gio
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- const: link
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- items: # for others
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- const: link
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for Pro4, Pro5
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- const: gio
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- const: link
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- items: # for others
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- const: link
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#reset-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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examples:
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- |
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usb-glue@65b00000 {
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compatible = "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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};
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@ -1,61 +0,0 @@
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UniPhier glue reset controller
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Peripheral core reset in glue layer
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-----------------------------------
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Some peripheral core reset belongs to its own glue layer. Before using
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this core reset, it is necessary to control the clocks and resets to enable
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this layer. These clocks and resets should be described in each property.
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Required properties:
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- compatible: Should be
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"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
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"socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
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"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
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"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
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"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
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"socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
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"socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
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"socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
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- #reset-cells: Should be 1.
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- reg: Specifies offset and length of the register set for the device.
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- clocks: A list of phandles to the clock gate for the glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names: Should contain
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"gio", "link" - for Pro4 and Pro5 SoCs
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"link" - for others
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- resets: A list of phandles to the reset control for the glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names: Should contain
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"gio", "link" - for Pro4 and Pro5 SoCs
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"link" - for others
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Example:
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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regulator {
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...
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};
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phy {
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...
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};
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...
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};
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@ -181,6 +181,13 @@ config RESET_RASPBERRYPI
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interfacing with RPi4's co-processor and model these firmware
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initialization routines as reset lines.
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config RESET_RZG2L_USBPHY_CTRL
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tristate "Renesas RZ/G2L USBPHY control driver"
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depends on ARCH_R9A07G044 || COMPILE_TEST
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help
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Support for USBPHY Control found on RZ/G2L family. It mainly
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controls reset and power down of the USB/PHY.
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config RESET_SCMI
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tristate "Reset driver controlled via ARM SCMI interface"
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depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
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@ -207,7 +214,6 @@ config RESET_SIMPLE
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- Realtek SoCs
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- RCC reset controller in STM32 MCUs
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- Allwinner SoCs
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- ZTE's zx2967 family
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- SiFive FU740 SoCs
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config RESET_SOCFPGA
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@ -25,6 +25,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
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obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
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obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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@ -11,18 +11,26 @@
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#include <dt-bindings/reset/qcom,sdm845-pdc.h>
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#define RPMH_PDC_SYNC_RESET 0x100
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#define RPMH_SDM845_PDC_SYNC_RESET 0x100
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#define RPMH_SC7280_PDC_SYNC_RESET 0x1000
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struct qcom_pdc_reset_map {
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u8 bit;
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};
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struct qcom_pdc_reset_desc {
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const struct qcom_pdc_reset_map *resets;
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size_t num_resets;
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unsigned int offset;
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};
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struct qcom_pdc_reset_data {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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const struct qcom_pdc_reset_desc *desc;
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};
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static const struct regmap_config sdm845_pdc_regmap_config = {
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static const struct regmap_config pdc_regmap_config = {
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.name = "pdc-reset",
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.reg_bits = 32,
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.reg_stride = 4,
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@ -44,6 +52,33 @@ static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
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[PDC_MODEM_SYNC_RESET] = {9},
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};
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static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
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.resets = sdm845_pdc_resets,
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.num_resets = ARRAY_SIZE(sdm845_pdc_resets),
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.offset = RPMH_SDM845_PDC_SYNC_RESET,
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};
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static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
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[PDC_APPS_SYNC_RESET] = {0},
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[PDC_SP_SYNC_RESET] = {1},
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[PDC_AUDIO_SYNC_RESET] = {2},
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[PDC_SENSORS_SYNC_RESET] = {3},
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[PDC_AOP_SYNC_RESET] = {4},
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[PDC_DEBUG_SYNC_RESET] = {5},
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[PDC_GPU_SYNC_RESET] = {6},
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[PDC_DISPLAY_SYNC_RESET] = {7},
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[PDC_COMPUTE_SYNC_RESET] = {8},
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[PDC_MODEM_SYNC_RESET] = {9},
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[PDC_WLAN_RF_SYNC_RESET] = {10},
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[PDC_WPSS_SYNC_RESET] = {11},
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};
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static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
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.resets = sc7280_pdc_resets,
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.num_resets = ARRAY_SIZE(sc7280_pdc_resets),
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.offset = RPMH_SC7280_PDC_SYNC_RESET,
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};
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static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
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struct reset_controller_dev *rcdev)
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{
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@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
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u32 mask = BIT(data->desc->resets[idx].bit);
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return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
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BIT(sdm845_pdc_resets[idx].bit),
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BIT(sdm845_pdc_resets[idx].bit));
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return regmap_update_bits(data->regmap, data->desc->offset, mask, mask);
|
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}
|
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|
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static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
|
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unsigned long idx)
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{
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struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
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u32 mask = BIT(data->desc->resets[idx].bit);
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return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
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BIT(sdm845_pdc_resets[idx].bit), 0);
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return regmap_update_bits(data->regmap, data->desc->offset, mask, 0);
|
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}
|
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|
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static const struct reset_control_ops qcom_pdc_reset_ops = {
|
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@ -76,22 +110,27 @@ static const struct reset_control_ops qcom_pdc_reset_ops = {
|
||||
|
||||
static int qcom_pdc_reset_probe(struct platform_device *pdev)
|
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{
|
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const struct qcom_pdc_reset_desc *desc;
|
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struct qcom_pdc_reset_data *data;
|
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struct device *dev = &pdev->dev;
|
||||
void __iomem *base;
|
||||
struct resource *res;
|
||||
|
||||
desc = device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->desc = desc;
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
data->regmap = devm_regmap_init_mmio(dev, base,
|
||||
&sdm845_pdc_regmap_config);
|
||||
data->regmap = devm_regmap_init_mmio(dev, base, &pdc_regmap_config);
|
||||
if (IS_ERR(data->regmap)) {
|
||||
dev_err(dev, "Unable to initialize regmap\n");
|
||||
return PTR_ERR(data->regmap);
|
||||
@ -99,14 +138,15 @@ static int qcom_pdc_reset_probe(struct platform_device *pdev)
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.ops = &qcom_pdc_reset_ops;
|
||||
data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
|
||||
data->rcdev.nr_resets = desc->num_resets;
|
||||
data->rcdev.of_node = dev->of_node;
|
||||
|
||||
return devm_reset_controller_register(dev, &data->rcdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_pdc_reset_of_match[] = {
|
||||
{ .compatible = "qcom,sdm845-pdc-global" },
|
||||
{ .compatible = "qcom,sc7280-pdc-global", .data = &sc7280_pdc_reset_desc },
|
||||
{ .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_reset_desc },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
|
||||
|
||||
175
drivers/reset/reset-rzg2l-usbphy-ctrl.c
Normal file
175
drivers/reset/reset-rzg2l-usbphy-ctrl.c
Normal file
@ -0,0 +1,175 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas RZ/G2L USBPHY control driver
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/reset-controller.h>
|
||||
|
||||
#define RESET 0x000
|
||||
|
||||
#define RESET_SEL_PLLRESET BIT(12)
|
||||
#define RESET_PLLRESET BIT(8)
|
||||
|
||||
#define RESET_SEL_P2RESET BIT(5)
|
||||
#define RESET_SEL_P1RESET BIT(4)
|
||||
#define RESET_PHYRST_2 BIT(1)
|
||||
#define RESET_PHYRST_1 BIT(0)
|
||||
|
||||
#define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2)
|
||||
#define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1)
|
||||
|
||||
#define NUM_PORTS 2
|
||||
|
||||
struct rzg2l_usbphy_ctrl_priv {
|
||||
struct reset_controller_dev rcdev;
|
||||
struct reset_control *rstc;
|
||||
void __iomem *base;
|
||||
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
#define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev)
|
||||
|
||||
static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
|
||||
u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2;
|
||||
void __iomem *base = priv->base;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
val = readl(base + RESET);
|
||||
val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
|
||||
if (port_mask == (val & port_mask))
|
||||
val |= RESET_PLLRESET;
|
||||
writel(val, base + RESET);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
|
||||
void __iomem *base = priv->base;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
val = readl(base + RESET);
|
||||
|
||||
val |= RESET_SEL_PLLRESET;
|
||||
val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1));
|
||||
writel(val, base + RESET);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
|
||||
u32 port_mask;
|
||||
|
||||
port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
|
||||
|
||||
return !!(readl(priv->base + RESET) & port_mask);
|
||||
}
|
||||
|
||||
static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
|
||||
{ .compatible = "renesas,rzg2l-usbphy-ctrl" },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
|
||||
|
||||
static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = {
|
||||
.assert = rzg2l_usbphy_ctrl_assert,
|
||||
.deassert = rzg2l_usbphy_ctrl_deassert,
|
||||
.status = rzg2l_usbphy_ctrl_status,
|
||||
};
|
||||
|
||||
static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rzg2l_usbphy_ctrl_priv *priv;
|
||||
unsigned long flags;
|
||||
int error;
|
||||
u32 val;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
|
||||
if (IS_ERR(priv->rstc))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->rstc),
|
||||
"failed to get reset\n");
|
||||
|
||||
reset_control_deassert(priv->rstc);
|
||||
|
||||
priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
|
||||
priv->rcdev.of_reset_n_cells = 1;
|
||||
priv->rcdev.nr_resets = NUM_PORTS;
|
||||
priv->rcdev.of_node = dev->of_node;
|
||||
priv->rcdev.dev = dev;
|
||||
|
||||
error = devm_reset_controller_register(dev, &priv->rcdev);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
spin_lock_init(&priv->lock);
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_resume_and_get(&pdev->dev);
|
||||
|
||||
/* put pll and phy into reset state */
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
val = readl(priv->base + RESET);
|
||||
val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
|
||||
writel(val, priv->base + RESET);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_usbphy_ctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
reset_control_assert(priv->rstc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rzg2l_usbphy_ctrl_driver = {
|
||||
.driver = {
|
||||
.name = "rzg2l_usbphy_ctrl",
|
||||
.of_match_table = rzg2l_usbphy_ctrl_match_table,
|
||||
},
|
||||
.probe = rzg2l_usbphy_ctrl_probe,
|
||||
.remove = rzg2l_usbphy_ctrl_remove,
|
||||
};
|
||||
module_platform_driver(rzg2l_usbphy_ctrl_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
|
||||
MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
|
||||
@ -16,5 +16,7 @@
|
||||
#define PDC_DISPLAY_SYNC_RESET 7
|
||||
#define PDC_COMPUTE_SYNC_RESET 8
|
||||
#define PDC_MODEM_SYNC_RESET 9
|
||||
#define PDC_WLAN_RF_SYNC_RESET 10
|
||||
#define PDC_WPSS_SYNC_RESET 11
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user