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media: s5p-mfc: Fix in register read and write for H264
Few of the H264 encoder registers written were not getting reflected
since the read values were not stored and getting overwritten.
Fixes: 6a9c6f6812
("[media] s5p-mfc: Add variants to access mfc registers")
Cc: stable@vger.kernel.org
Cc: linux-fsd@tesla.com
Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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7318abface
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@ -1060,7 +1060,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
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}
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/* aspect ratio VUI */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x1 << 5);
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reg |= ((p_h264->vui_sar & 0x1) << 5);
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writel(reg, mfc_regs->e_h264_options);
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@ -1083,7 +1083,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
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/* intra picture period for H.264 open GOP */
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/* control */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x1 << 4);
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reg |= ((p_h264->open_gop & 0x1) << 4);
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writel(reg, mfc_regs->e_h264_options);
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@ -1097,23 +1097,23 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
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}
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/* 'WEIGHTED_BI_PREDICTION' for B is disable */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x3 << 9);
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writel(reg, mfc_regs->e_h264_options);
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/* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x1 << 14);
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writel(reg, mfc_regs->e_h264_options);
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/* ASO */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x1 << 6);
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reg |= ((p_h264->aso & 0x1) << 6);
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writel(reg, mfc_regs->e_h264_options);
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/* hier qp enable */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x1 << 8);
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reg |= ((p_h264->open_gop & 0x1) << 8);
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writel(reg, mfc_regs->e_h264_options);
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@ -1134,7 +1134,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
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writel(reg, mfc_regs->e_h264_num_t_layer);
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/* frame packing SEI generation */
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readl(mfc_regs->e_h264_options);
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reg = readl(mfc_regs->e_h264_options);
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reg &= ~(0x1 << 25);
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reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
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writel(reg, mfc_regs->e_h264_options);
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