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dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model

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Deprecate the legacy Rockchip PCIe PHY and encourage users to use per-lane
PHY mode by setting #phy-cells to 1.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Shawn Lin 2017-07-19 17:57:58 +08:00 committed by Bjorn Helgaas
parent 7a55b57031
commit 05b57273ac
1 changed files with 6 additions and 1 deletions
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7
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
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@ -3,7 +3,6 @@ Rockchip PCIE PHY
Required properties:
- compatible: rockchip,rk3399-pcie-phy
- #phy-cells: must be 0
- clocks: Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must be "refclk"
@ -11,6 +10,12 @@ Required properties:
See ../reset/reset.txt for details.
- reset-names: Must be "phy"
Required properties for legacy PHY mode (deprecated):
- #phy-cells: must be 0
Required properties for per-lane PHY mode (preferred):
- #phy-cells: must be 1
Example:
grf: syscon@ff770000 {