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pinctrl: sh-pfc: Updates for v4.15 (take two)
- Add Audio, HSCIF, I2C, and INTC-EX pin groups on R-Car H3 ES2.0, - Add Audio and PWM pin groups on R-Car D3, - Add support for RZ/A1M and RZ/A1L, - Add INTC-EX pin groups on R-Car M3-W, - Add SDHI voltage switching on RZ/G1E, - Make bias control and IOCTRL support more generic, - Add suspend/resume support for R-Car Gen3, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZ6cZfAAoJEEgEtLw/Ve77i7gQAJuvBDsBZjx+bVSSPxkkYoDH bGhkjYSkaYKj/VaJ9Qx6DBG5aCEybrIPKohVfFMDAyzkyHzNTfRsf2cce409P6Oo mzRCIZ93EE9yt49eTZZoHJxLHJcofWvUB97W6XA9Pz4ro3L99TUWNKGVkZG3ZhGE a+KeKu23Jk3ujubHKFK3OnuBYEkugJoacWSbpIKI6siaBaHK4/5kEJ3uVoVGwuNK Uwwex2GAodbVDI4g+CBRyKQTE3epWkC8VbYmRfIPz3yIpbCqumbt4wYLH7Fh8ae4 jD/LNDiP91d90CgdWOK6HKzpENUWJRYuis4OPyEwRs6z/YC5DJ0mR8yyHboUZYCd rnI6jn99xrZbatne6hNk+3q96Snr1HOB6dbzRfNZxNGqrhS8HtDicBxNelExF3mr F0uajUGNzhyK/xbxgKXfdH/YuwksfygX7aSp9bVS1xRYpB7NNcvNhcBXjyIAi7sK RssaLL0dwQploWN5eghhrcqmuL8BVRyx1O/brvQeZk166tpfLWfR3UX7ph6DkYSn mlUiSs+nbczaHlqYy/HFN2Hsc3Ze54OvE0Yn5eerBiavq80naEMowUb6FS/8AwGN 03DopyMczUui9KYgAetpocjKkpmVD2sXIv3BiuvD+Hwp5yL4jDDgvd9cRdy8RaAX s785sK0VtzAFUQ3U+rSc =6Arb -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 (take two) - Add Audio, HSCIF, I2C, and INTC-EX pin groups on R-Car H3 ES2.0, - Add Audio and PWM pin groups on R-Car D3, - Add support for RZ/A1M and RZ/A1L, - Add INTC-EX pin groups on R-Car M3-W, - Add SDHI voltage switching on RZ/G1E, - Make bias control and IOCTRL support more generic, - Add suspend/resume support for R-Car Gen3, - Small fixes and cleanups.
This commit is contained in:
Linus Walleij
commit
051e1674a5
@ -12,8 +12,10 @@ Pin controller node
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-------------------
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Required properties:
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- compatible
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this shall be "renesas,r7s72100-ports".
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- compatible: should be:
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- "renesas,r7s72100-ports": for RZ/A1H
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- "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
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- "renesas,r7s72102-ports": for RZ/A1L
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- reg
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address base and length of the memory area where the pin controller
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@ -302,6 +302,134 @@ static const struct rza1_pinmux_conf rza1h_pmx_conf = {
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.swio_entries = rza1h_swio_entries,
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};
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/* ----------------------------------------------------------------------------
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* RZ/A1L (r7s72102) pinmux flags
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*/
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static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
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{ .pin = 0, .func = 1 },
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{ .pin = 1, .func = 1 },
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{ .pin = 2, .func = 1 },
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{ .pin = 3, .func = 1 },
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{ .pin = 4, .func = 1 },
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{ .pin = 5, .func = 1 },
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{ .pin = 6, .func = 1 },
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{ .pin = 7, .func = 1 },
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};
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static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
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{ .pin = 0, .func = 2 },
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{ .pin = 1, .func = 2 },
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{ .pin = 2, .func = 2 },
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{ .pin = 4, .func = 2 },
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{ .pin = 5, .func = 2 },
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{ .pin = 10, .func = 2 },
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{ .pin = 11, .func = 2 },
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{ .pin = 12, .func = 2 },
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{ .pin = 13, .func = 2 },
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};
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static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
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{ .pin = 1, .func = 4 },
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{ .pin = 2, .func = 2 },
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{ .pin = 3, .func = 2 },
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{ .pin = 6, .func = 2 },
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{ .pin = 7, .func = 2 },
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};
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static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
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{ .pin = 0, .func = 1 },
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{ .pin = 1, .func = 1 },
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{ .pin = 2, .func = 1 },
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{ .pin = 3, .func = 1 },
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{ .pin = 4, .func = 1 },
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{ .pin = 5, .func = 1 },
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{ .pin = 6, .func = 1 },
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{ .pin = 7, .func = 1 },
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{ .pin = 8, .func = 1 },
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{ .pin = 9, .func = 1 },
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{ .pin = 10, .func = 1 },
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{ .pin = 11, .func = 1 },
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{ .pin = 12, .func = 1 },
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{ .pin = 13, .func = 1 },
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{ .pin = 14, .func = 1 },
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{ .pin = 15, .func = 1 },
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{ .pin = 0, .func = 2 },
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{ .pin = 1, .func = 2 },
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{ .pin = 2, .func = 2 },
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{ .pin = 3, .func = 2 },
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};
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static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
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{ .pin = 0, .func = 1 },
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{ .pin = 1, .func = 1 },
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{ .pin = 2, .func = 1 },
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{ .pin = 3, .func = 1 },
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{ .pin = 4, .func = 1 },
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{ .pin = 5, .func = 1 },
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{ .pin = 6, .func = 1 },
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{ .pin = 7, .func = 1 },
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{ .pin = 8, .func = 1 },
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{ .pin = 9, .func = 1 },
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{ .pin = 10, .func = 1 },
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{ .pin = 11, .func = 1 },
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{ .pin = 12, .func = 1 },
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{ .pin = 13, .func = 1 },
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{ .pin = 14, .func = 1 },
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{ .pin = 15, .func = 1 },
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};
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static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
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{ .pin = 2, .func = 2 },
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{ .pin = 3, .func = 2 },
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{ .pin = 5, .func = 2 },
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{ .pin = 6, .func = 2 },
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{ .pin = 7, .func = 2 },
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{ .pin = 2, .func = 3 },
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{ .pin = 3, .func = 3 },
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{ .pin = 5, .func = 3 },
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{ .pin = 6, .func = 3 },
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{ .pin = 7, .func = 3 },
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};
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static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
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{ .pin = 1, .func = 2 },
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{ .pin = 0, .func = 3 },
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{ .pin = 1, .func = 3 },
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{ .pin = 3, .func = 3 },
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{ .pin = 4, .func = 3 },
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{ .pin = 5, .func = 3 },
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};
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static const struct rza1_swio_pin rza1l_swio_pins[] = {
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{ .port = 2, .pin = 8, .func = 2, .input = 0 },
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{ .port = 5, .pin = 6, .func = 3, .input = 0 },
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{ .port = 6, .pin = 6, .func = 3, .input = 0 },
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{ .port = 6, .pin = 10, .func = 3, .input = 0 },
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{ .port = 7, .pin = 10, .func = 2, .input = 0 },
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{ .port = 8, .pin = 2, .func = 3, .input = 0 },
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};
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static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
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[1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
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[3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
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[4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
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[5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
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[6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
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[7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
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[9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
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};
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static const struct rza1_swio_entry rza1l_swio_entries[] = {
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[0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
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};
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/* RZ/A1L (r7s72102x) pinmux flags table */
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static const struct rza1_pinmux_conf rza1l_pmx_conf = {
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.bidir_entries = rza1l_bidir_entries,
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.swio_entries = rza1l_swio_entries,
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};
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/* ----------------------------------------------------------------------------
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* RZ/A1 types
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*/
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@ -1283,9 +1411,15 @@ static int rza1_pinctrl_probe(struct platform_device *pdev)
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static const struct of_device_id rza1_pinctrl_of_match[] = {
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{
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/* RZ/A1H, RZ/A1M */
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.compatible = "renesas,r7s72100-ports",
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.data = &rza1h_pmx_conf,
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},
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{
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/* RZ/A1L */
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.compatible = "renesas,r7s72102-ports",
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.data = &rza1l_pmx_conf,
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},
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{ }
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};
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@ -24,6 +24,7 @@
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#include <linux/of_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_device.h>
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#include <linux/psci.h>
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#include <linux/slab.h>
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#include "core.h"
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@ -175,19 +176,19 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
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BUG();
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}
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u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
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u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
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{
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return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width);
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return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
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}
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void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
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void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
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{
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(
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sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
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~data);
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sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data);
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sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
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}
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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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@ -389,15 +390,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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return 0;
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}
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const struct sh_pfc_bias_info *
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sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
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unsigned int num, unsigned int pin)
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const struct pinmux_bias_reg *
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sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
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unsigned int *bit)
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{
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unsigned int i;
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unsigned int i, j;
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for (i = 0; i < num; i++)
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if (info[i].pin == pin)
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return &info[i];
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for (i = 0; pfc->info->bias_regs[i].puen; i++) {
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for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
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if (pfc->info->bias_regs[i].pins[j] == pin) {
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*bit = j;
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return &pfc->info->bias_regs[i];
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}
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}
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}
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WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
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@ -567,9 +573,99 @@ static const struct of_device_id sh_pfc_of_table[] = {
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};
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#endif
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#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
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static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
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{
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}
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static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
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{
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pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
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}
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static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
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{
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sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
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}
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static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
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void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
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{
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unsigned int i, n = 0;
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if (pfc->info->cfg_regs)
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for (i = 0; pfc->info->cfg_regs[i].reg; i++)
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do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
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if (pfc->info->drive_regs)
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for (i = 0; pfc->info->drive_regs[i].reg; i++)
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do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
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if (pfc->info->bias_regs)
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for (i = 0; pfc->info->bias_regs[i].puen; i++) {
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do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
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if (pfc->info->bias_regs[i].pud)
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do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
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}
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if (pfc->info->ioctrl_regs)
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for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
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do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
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return n;
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}
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static int sh_pfc_suspend_init(struct sh_pfc *pfc)
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{
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unsigned int n;
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/* This is the best we can do to check for the presence of PSCI */
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if (!psci_ops.cpu_suspend)
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return 0;
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n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
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if (!n)
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return 0;
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pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
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sizeof(*pfc->saved_regs),
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GFP_KERNEL);
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if (!pfc->saved_regs)
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return -ENOMEM;
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dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
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return 0;
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}
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static int sh_pfc_suspend_noirq(struct device *dev)
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{
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struct sh_pfc *pfc = dev_get_drvdata(dev);
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if (pfc->saved_regs)
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sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
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return 0;
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}
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static int sh_pfc_resume_noirq(struct device *dev)
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{
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struct sh_pfc *pfc = dev_get_drvdata(dev);
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if (pfc->saved_regs)
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sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
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return 0;
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}
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static const struct dev_pm_ops sh_pfc_pm = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
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};
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#define DEV_PM_OPS &sh_pfc_pm
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#else
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static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
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#define DEV_PM_OPS NULL
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#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
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static int sh_pfc_probe(struct platform_device *pdev)
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{
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const struct platform_device_id *platid = platform_get_device_id(pdev);
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#ifdef CONFIG_OF
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struct device_node *np = pdev->dev.of_node;
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#endif
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@ -582,10 +678,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
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info = of_device_get_match_data(&pdev->dev);
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else
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#endif
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info = platid ? (const void *)platid->driver_data : NULL;
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if (info == NULL)
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return -ENODEV;
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info = (const void *)platform_get_device_id(pdev)->driver_data;
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pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
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if (pfc == NULL)
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@ -609,6 +702,10 @@ static int sh_pfc_probe(struct platform_device *pdev)
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info = pfc->info;
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}
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ret = sh_pfc_suspend_init(pfc);
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if (ret)
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return ret;
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/* Enable dummy states for those platforms without pinctrl support */
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if (!of_have_populated_dt())
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pinctrl_provide_dummies();
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@ -683,7 +780,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
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#ifdef CONFIG_PINCTRL_PFC_SHX3
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{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
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#endif
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{ "sh-pfc", 0 },
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{ },
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};
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@ -693,6 +789,7 @@ static struct platform_driver sh_pfc_driver = {
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.driver = {
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.name = DRV_NAME,
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.of_match_table = of_match_ptr(sh_pfc_of_table),
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.pm = DEV_PM_OPS,
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},
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};
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||||
@ -26,15 +26,14 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
|
||||
u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);
|
||||
void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
|
||||
u32 data);
|
||||
u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
|
||||
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
|
||||
u32 data);
|
||||
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
|
||||
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
|
||||
|
||||
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
|
||||
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
|
||||
|
||||
const struct sh_pfc_bias_info *
|
||||
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
|
||||
unsigned int num, unsigned int pin);
|
||||
const struct pinmux_bias_reg *
|
||||
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *bit);
|
||||
|
||||
#endif /* __SH_PFC_CORE_H__ */
|
||||
|
||||
@ -2912,189 +2912,230 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
#define PUPR0 0x100
|
||||
#define PUPR1 0x104
|
||||
#define PUPR2 0x108
|
||||
#define PUPR3 0x10c
|
||||
#define PUPR4 0x110
|
||||
#define PUPR5 0x114
|
||||
#define PIN_NONE U16_MAX
|
||||
|
||||
static const struct sh_pfc_bias_info bias_info[] = {
|
||||
{ RCAR_GP_PIN(0, 6), PUPR0, 0 }, /* A0 */
|
||||
{ RCAR_GP_PIN(0, 7), PUPR0, 1 }, /* A1 */
|
||||
{ RCAR_GP_PIN(0, 8), PUPR0, 2 }, /* A2 */
|
||||
{ RCAR_GP_PIN(0, 9), PUPR0, 3 }, /* A3 */
|
||||
{ RCAR_GP_PIN(0, 10), PUPR0, 4 }, /* A4 */
|
||||
{ RCAR_GP_PIN(0, 11), PUPR0, 5 }, /* A5 */
|
||||
{ RCAR_GP_PIN(0, 12), PUPR0, 6 }, /* A6 */
|
||||
{ RCAR_GP_PIN(0, 13), PUPR0, 7 }, /* A7 */
|
||||
{ RCAR_GP_PIN(0, 14), PUPR0, 8 }, /* A8 */
|
||||
{ RCAR_GP_PIN(0, 15), PUPR0, 9 }, /* A9 */
|
||||
{ RCAR_GP_PIN(0, 16), PUPR0, 10 }, /* A10 */
|
||||
{ RCAR_GP_PIN(0, 17), PUPR0, 11 }, /* A11 */
|
||||
{ RCAR_GP_PIN(0, 18), PUPR0, 12 }, /* A12 */
|
||||
{ RCAR_GP_PIN(0, 19), PUPR0, 13 }, /* A13 */
|
||||
{ RCAR_GP_PIN(0, 20), PUPR0, 14 }, /* A14 */
|
||||
{ RCAR_GP_PIN(0, 21), PUPR0, 15 }, /* A15 */
|
||||
{ RCAR_GP_PIN(0, 22), PUPR0, 16 }, /* A16 */
|
||||
{ RCAR_GP_PIN(0, 23), PUPR0, 17 }, /* A17 */
|
||||
{ RCAR_GP_PIN(0, 24), PUPR0, 18 }, /* A18 */
|
||||
{ RCAR_GP_PIN(0, 25), PUPR0, 19 }, /* A19 */
|
||||
{ RCAR_GP_PIN(0, 26), PUPR0, 20 }, /* A20 */
|
||||
{ RCAR_GP_PIN(0, 27), PUPR0, 21 }, /* A21 */
|
||||
{ RCAR_GP_PIN(0, 28), PUPR0, 22 }, /* A22 */
|
||||
{ RCAR_GP_PIN(0, 29), PUPR0, 23 }, /* A23 */
|
||||
{ RCAR_GP_PIN(0, 30), PUPR0, 24 }, /* A24 */
|
||||
{ RCAR_GP_PIN(0, 31), PUPR0, 25 }, /* A25 */
|
||||
{ RCAR_GP_PIN(1, 3), PUPR0, 26 }, /* /EX_CS0 */
|
||||
{ RCAR_GP_PIN(1, 4), PUPR0, 27 }, /* /EX_CS1 */
|
||||
{ RCAR_GP_PIN(1, 5), PUPR0, 28 }, /* /EX_CS2 */
|
||||
{ RCAR_GP_PIN(1, 6), PUPR0, 29 }, /* /EX_CS3 */
|
||||
{ RCAR_GP_PIN(1, 7), PUPR0, 30 }, /* /EX_CS4 */
|
||||
{ RCAR_GP_PIN(1, 8), PUPR0, 31 }, /* /EX_CS5 */
|
||||
|
||||
{ RCAR_GP_PIN(0, 0), PUPR1, 0 }, /* /PRESETOUT */
|
||||
{ RCAR_GP_PIN(0, 5), PUPR1, 1 }, /* /BS */
|
||||
{ RCAR_GP_PIN(1, 0), PUPR1, 2 }, /* RD//WR */
|
||||
{ RCAR_GP_PIN(1, 1), PUPR1, 3 }, /* /WE0 */
|
||||
{ RCAR_GP_PIN(1, 2), PUPR1, 4 }, /* /WE1 */
|
||||
{ RCAR_GP_PIN(1, 11), PUPR1, 5 }, /* EX_WAIT0 */
|
||||
{ RCAR_GP_PIN(1, 9), PUPR1, 6 }, /* DREQ0 */
|
||||
{ RCAR_GP_PIN(1, 10), PUPR1, 7 }, /* DACK0 */
|
||||
{ RCAR_GP_PIN(1, 12), PUPR1, 8 }, /* IRQ0 */
|
||||
{ RCAR_GP_PIN(1, 13), PUPR1, 9 }, /* IRQ1 */
|
||||
|
||||
{ RCAR_GP_PIN(1, 22), PUPR2, 0 }, /* DU0_DR0 */
|
||||
{ RCAR_GP_PIN(1, 23), PUPR2, 1 }, /* DU0_DR1 */
|
||||
{ RCAR_GP_PIN(1, 24), PUPR2, 2 }, /* DU0_DR2 */
|
||||
{ RCAR_GP_PIN(1, 25), PUPR2, 3 }, /* DU0_DR3 */
|
||||
{ RCAR_GP_PIN(1, 26), PUPR2, 4 }, /* DU0_DR4 */
|
||||
{ RCAR_GP_PIN(1, 27), PUPR2, 5 }, /* DU0_DR5 */
|
||||
{ RCAR_GP_PIN(1, 28), PUPR2, 6 }, /* DU0_DR6 */
|
||||
{ RCAR_GP_PIN(1, 29), PUPR2, 7 }, /* DU0_DR7 */
|
||||
{ RCAR_GP_PIN(1, 30), PUPR2, 8 }, /* DU0_DG0 */
|
||||
{ RCAR_GP_PIN(1, 31), PUPR2, 9 }, /* DU0_DG1 */
|
||||
{ RCAR_GP_PIN(2, 0), PUPR2, 10 }, /* DU0_DG2 */
|
||||
{ RCAR_GP_PIN(2, 1), PUPR2, 11 }, /* DU0_DG3 */
|
||||
{ RCAR_GP_PIN(2, 2), PUPR2, 12 }, /* DU0_DG4 */
|
||||
{ RCAR_GP_PIN(2, 3), PUPR2, 13 }, /* DU0_DG5 */
|
||||
{ RCAR_GP_PIN(2, 4), PUPR2, 14 }, /* DU0_DG6 */
|
||||
{ RCAR_GP_PIN(2, 5), PUPR2, 15 }, /* DU0_DG7 */
|
||||
{ RCAR_GP_PIN(2, 6), PUPR2, 16 }, /* DU0_DB0 */
|
||||
{ RCAR_GP_PIN(2, 7), PUPR2, 17 }, /* DU0_DB1 */
|
||||
{ RCAR_GP_PIN(2, 8), PUPR2, 18 }, /* DU0_DB2 */
|
||||
{ RCAR_GP_PIN(2, 9), PUPR2, 19 }, /* DU0_DB3 */
|
||||
{ RCAR_GP_PIN(2, 10), PUPR2, 20 }, /* DU0_DB4 */
|
||||
{ RCAR_GP_PIN(2, 11), PUPR2, 21 }, /* DU0_DB5 */
|
||||
{ RCAR_GP_PIN(2, 12), PUPR2, 22 }, /* DU0_DB6 */
|
||||
{ RCAR_GP_PIN(2, 13), PUPR2, 23 }, /* DU0_DB7 */
|
||||
{ RCAR_GP_PIN(2, 14), PUPR2, 24 }, /* DU0_DOTCLKIN */
|
||||
{ RCAR_GP_PIN(2, 15), PUPR2, 25 }, /* DU0_DOTCLKOUT0 */
|
||||
{ RCAR_GP_PIN(2, 17), PUPR2, 26 }, /* DU0_HSYNC */
|
||||
{ RCAR_GP_PIN(2, 18), PUPR2, 27 }, /* DU0_VSYNC */
|
||||
{ RCAR_GP_PIN(2, 19), PUPR2, 28 }, /* DU0_EXODDF */
|
||||
{ RCAR_GP_PIN(2, 20), PUPR2, 29 }, /* DU0_DISP */
|
||||
{ RCAR_GP_PIN(2, 21), PUPR2, 30 }, /* DU0_CDE */
|
||||
{ RCAR_GP_PIN(2, 16), PUPR2, 31 }, /* DU0_DOTCLKOUT1 */
|
||||
|
||||
{ RCAR_GP_PIN(3, 24), PUPR3, 0 }, /* VI0_CLK */
|
||||
{ RCAR_GP_PIN(3, 25), PUPR3, 1 }, /* VI0_CLKENB */
|
||||
{ RCAR_GP_PIN(3, 26), PUPR3, 2 }, /* VI0_FIELD */
|
||||
{ RCAR_GP_PIN(3, 27), PUPR3, 3 }, /* /VI0_HSYNC */
|
||||
{ RCAR_GP_PIN(3, 28), PUPR3, 4 }, /* /VI0_VSYNC */
|
||||
{ RCAR_GP_PIN(3, 29), PUPR3, 5 }, /* VI0_DATA0 */
|
||||
{ RCAR_GP_PIN(3, 30), PUPR3, 6 }, /* VI0_DATA1 */
|
||||
{ RCAR_GP_PIN(3, 31), PUPR3, 7 }, /* VI0_DATA2 */
|
||||
{ RCAR_GP_PIN(4, 0), PUPR3, 8 }, /* VI0_DATA3 */
|
||||
{ RCAR_GP_PIN(4, 1), PUPR3, 9 }, /* VI0_DATA4 */
|
||||
{ RCAR_GP_PIN(4, 2), PUPR3, 10 }, /* VI0_DATA5 */
|
||||
{ RCAR_GP_PIN(4, 3), PUPR3, 11 }, /* VI0_DATA6 */
|
||||
{ RCAR_GP_PIN(4, 4), PUPR3, 12 }, /* VI0_DATA7 */
|
||||
{ RCAR_GP_PIN(4, 5), PUPR3, 13 }, /* VI0_G2 */
|
||||
{ RCAR_GP_PIN(4, 6), PUPR3, 14 }, /* VI0_G3 */
|
||||
{ RCAR_GP_PIN(4, 7), PUPR3, 15 }, /* VI0_G4 */
|
||||
{ RCAR_GP_PIN(4, 8), PUPR3, 16 }, /* VI0_G5 */
|
||||
{ RCAR_GP_PIN(4, 21), PUPR3, 17 }, /* VI1_DATA12 */
|
||||
{ RCAR_GP_PIN(4, 22), PUPR3, 18 }, /* VI1_DATA13 */
|
||||
{ RCAR_GP_PIN(4, 23), PUPR3, 19 }, /* VI1_DATA14 */
|
||||
{ RCAR_GP_PIN(4, 24), PUPR3, 20 }, /* VI1_DATA15 */
|
||||
{ RCAR_GP_PIN(4, 9), PUPR3, 21 }, /* ETH_REF_CLK */
|
||||
{ RCAR_GP_PIN(4, 10), PUPR3, 22 }, /* ETH_TXD0 */
|
||||
{ RCAR_GP_PIN(4, 11), PUPR3, 23 }, /* ETH_TXD1 */
|
||||
{ RCAR_GP_PIN(4, 12), PUPR3, 24 }, /* ETH_CRS_DV */
|
||||
{ RCAR_GP_PIN(4, 13), PUPR3, 25 }, /* ETH_TX_EN */
|
||||
{ RCAR_GP_PIN(4, 14), PUPR3, 26 }, /* ETH_RX_ER */
|
||||
{ RCAR_GP_PIN(4, 15), PUPR3, 27 }, /* ETH_RXD0 */
|
||||
{ RCAR_GP_PIN(4, 16), PUPR3, 28 }, /* ETH_RXD1 */
|
||||
{ RCAR_GP_PIN(4, 17), PUPR3, 29 }, /* ETH_MDC */
|
||||
{ RCAR_GP_PIN(4, 18), PUPR3, 30 }, /* ETH_MDIO */
|
||||
{ RCAR_GP_PIN(4, 19), PUPR3, 31 }, /* ETH_LINK */
|
||||
|
||||
{ RCAR_GP_PIN(3, 6), PUPR4, 0 }, /* SSI_SCK012 */
|
||||
{ RCAR_GP_PIN(3, 7), PUPR4, 1 }, /* SSI_WS012 */
|
||||
{ RCAR_GP_PIN(3, 10), PUPR4, 2 }, /* SSI_SDATA0 */
|
||||
{ RCAR_GP_PIN(3, 9), PUPR4, 3 }, /* SSI_SDATA1 */
|
||||
{ RCAR_GP_PIN(3, 8), PUPR4, 4 }, /* SSI_SDATA2 */
|
||||
{ RCAR_GP_PIN(3, 2), PUPR4, 5 }, /* SSI_SCK34 */
|
||||
{ RCAR_GP_PIN(3, 3), PUPR4, 6 }, /* SSI_WS34 */
|
||||
{ RCAR_GP_PIN(3, 5), PUPR4, 7 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(3, 4), PUPR4, 8 }, /* SSI_SDATA4 */
|
||||
{ RCAR_GP_PIN(2, 31), PUPR4, 9 }, /* SSI_SCK5 */
|
||||
{ RCAR_GP_PIN(3, 0), PUPR4, 10 }, /* SSI_WS5 */
|
||||
{ RCAR_GP_PIN(3, 1), PUPR4, 11 }, /* SSI_SDATA5 */
|
||||
{ RCAR_GP_PIN(2, 28), PUPR4, 12 }, /* SSI_SCK6 */
|
||||
{ RCAR_GP_PIN(2, 29), PUPR4, 13 }, /* SSI_WS6 */
|
||||
{ RCAR_GP_PIN(2, 30), PUPR4, 14 }, /* SSI_SDATA6 */
|
||||
{ RCAR_GP_PIN(2, 24), PUPR4, 15 }, /* SSI_SCK78 */
|
||||
{ RCAR_GP_PIN(2, 25), PUPR4, 16 }, /* SSI_WS78 */
|
||||
{ RCAR_GP_PIN(2, 27), PUPR4, 17 }, /* SSI_SDATA7 */
|
||||
{ RCAR_GP_PIN(2, 26), PUPR4, 18 }, /* SSI_SDATA8 */
|
||||
{ RCAR_GP_PIN(3, 23), PUPR4, 19 }, /* TCLK0 */
|
||||
{ RCAR_GP_PIN(3, 11), PUPR4, 20 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 12), PUPR4, 21 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 13), PUPR4, 22 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 14), PUPR4, 23 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 15), PUPR4, 24 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 16), PUPR4, 25 }, /* SD0_DAT3 */
|
||||
{ RCAR_GP_PIN(3, 17), PUPR4, 26 }, /* SD0_CD */
|
||||
{ RCAR_GP_PIN(3, 18), PUPR4, 27 }, /* SD0_WP */
|
||||
{ RCAR_GP_PIN(2, 22), PUPR4, 28 }, /* AUDIO_CLKA */
|
||||
{ RCAR_GP_PIN(2, 23), PUPR4, 29 }, /* AUDIO_CLKB */
|
||||
{ RCAR_GP_PIN(1, 14), PUPR4, 30 }, /* IRQ2 */
|
||||
{ RCAR_GP_PIN(1, 15), PUPR4, 31 }, /* IRQ3 */
|
||||
|
||||
{ RCAR_GP_PIN(0, 1), PUPR5, 0 }, /* PENC0 */
|
||||
{ RCAR_GP_PIN(0, 2), PUPR5, 1 }, /* PENC1 */
|
||||
{ RCAR_GP_PIN(0, 3), PUPR5, 2 }, /* USB_OVC0 */
|
||||
{ RCAR_GP_PIN(0, 4), PUPR5, 3 }, /* USB_OVC1 */
|
||||
{ RCAR_GP_PIN(1, 16), PUPR5, 4 }, /* SCIF_CLK */
|
||||
{ RCAR_GP_PIN(1, 17), PUPR5, 5 }, /* TX0 */
|
||||
{ RCAR_GP_PIN(1, 18), PUPR5, 6 }, /* RX0 */
|
||||
{ RCAR_GP_PIN(1, 19), PUPR5, 7 }, /* SCK0 */
|
||||
{ RCAR_GP_PIN(1, 20), PUPR5, 8 }, /* /CTS0 */
|
||||
{ RCAR_GP_PIN(1, 21), PUPR5, 9 }, /* /RTS0 */
|
||||
{ RCAR_GP_PIN(3, 19), PUPR5, 10 }, /* HSPI_CLK0 */
|
||||
{ RCAR_GP_PIN(3, 20), PUPR5, 11 }, /* /HSPI_CS0 */
|
||||
{ RCAR_GP_PIN(3, 21), PUPR5, 12 }, /* HSPI_RX0 */
|
||||
{ RCAR_GP_PIN(3, 22), PUPR5, 13 }, /* HSPI_TX0 */
|
||||
{ RCAR_GP_PIN(4, 20), PUPR5, 14 }, /* ETH_MAGIC */
|
||||
{ RCAR_GP_PIN(4, 25), PUPR5, 15 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(4, 26), PUPR5, 16 }, /* AVS2 */
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 6), /* A0 */
|
||||
[ 1] = RCAR_GP_PIN(0, 7), /* A1 */
|
||||
[ 2] = RCAR_GP_PIN(0, 8), /* A2 */
|
||||
[ 3] = RCAR_GP_PIN(0, 9), /* A3 */
|
||||
[ 4] = RCAR_GP_PIN(0, 10), /* A4 */
|
||||
[ 5] = RCAR_GP_PIN(0, 11), /* A5 */
|
||||
[ 6] = RCAR_GP_PIN(0, 12), /* A6 */
|
||||
[ 7] = RCAR_GP_PIN(0, 13), /* A7 */
|
||||
[ 8] = RCAR_GP_PIN(0, 14), /* A8 */
|
||||
[ 9] = RCAR_GP_PIN(0, 15), /* A9 */
|
||||
[10] = RCAR_GP_PIN(0, 16), /* A10 */
|
||||
[11] = RCAR_GP_PIN(0, 17), /* A11 */
|
||||
[12] = RCAR_GP_PIN(0, 18), /* A12 */
|
||||
[13] = RCAR_GP_PIN(0, 19), /* A13 */
|
||||
[14] = RCAR_GP_PIN(0, 20), /* A14 */
|
||||
[15] = RCAR_GP_PIN(0, 21), /* A15 */
|
||||
[16] = RCAR_GP_PIN(0, 22), /* A16 */
|
||||
[17] = RCAR_GP_PIN(0, 23), /* A17 */
|
||||
[18] = RCAR_GP_PIN(0, 24), /* A18 */
|
||||
[19] = RCAR_GP_PIN(0, 25), /* A19 */
|
||||
[20] = RCAR_GP_PIN(0, 26), /* A20 */
|
||||
[21] = RCAR_GP_PIN(0, 27), /* A21 */
|
||||
[22] = RCAR_GP_PIN(0, 28), /* A22 */
|
||||
[23] = RCAR_GP_PIN(0, 29), /* A23 */
|
||||
[24] = RCAR_GP_PIN(0, 30), /* A24 */
|
||||
[25] = RCAR_GP_PIN(0, 31), /* A25 */
|
||||
[26] = RCAR_GP_PIN(1, 3), /* /EX_CS0 */
|
||||
[27] = RCAR_GP_PIN(1, 4), /* /EX_CS1 */
|
||||
[28] = RCAR_GP_PIN(1, 5), /* /EX_CS2 */
|
||||
[29] = RCAR_GP_PIN(1, 6), /* /EX_CS3 */
|
||||
[30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */
|
||||
[31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */
|
||||
[ 1] = RCAR_GP_PIN(0, 5), /* /BS */
|
||||
[ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */
|
||||
[ 3] = RCAR_GP_PIN(1, 1), /* /WE0 */
|
||||
[ 4] = RCAR_GP_PIN(1, 2), /* /WE1 */
|
||||
[ 5] = RCAR_GP_PIN(1, 11), /* EX_WAIT0 */
|
||||
[ 6] = RCAR_GP_PIN(1, 9), /* DREQ0 */
|
||||
[ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
|
||||
[ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
|
||||
[ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
|
||||
[ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */
|
||||
[ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */
|
||||
[ 3] = RCAR_GP_PIN(1, 25), /* DU0_DR3 */
|
||||
[ 4] = RCAR_GP_PIN(1, 26), /* DU0_DR4 */
|
||||
[ 5] = RCAR_GP_PIN(1, 27), /* DU0_DR5 */
|
||||
[ 6] = RCAR_GP_PIN(1, 28), /* DU0_DR6 */
|
||||
[ 7] = RCAR_GP_PIN(1, 29), /* DU0_DR7 */
|
||||
[ 8] = RCAR_GP_PIN(1, 30), /* DU0_DG0 */
|
||||
[ 9] = RCAR_GP_PIN(1, 31), /* DU0_DG1 */
|
||||
[10] = RCAR_GP_PIN(2, 0), /* DU0_DG2 */
|
||||
[11] = RCAR_GP_PIN(2, 1), /* DU0_DG3 */
|
||||
[12] = RCAR_GP_PIN(2, 2), /* DU0_DG4 */
|
||||
[13] = RCAR_GP_PIN(2, 3), /* DU0_DG5 */
|
||||
[14] = RCAR_GP_PIN(2, 4), /* DU0_DG6 */
|
||||
[15] = RCAR_GP_PIN(2, 5), /* DU0_DG7 */
|
||||
[16] = RCAR_GP_PIN(2, 6), /* DU0_DB0 */
|
||||
[17] = RCAR_GP_PIN(2, 7), /* DU0_DB1 */
|
||||
[18] = RCAR_GP_PIN(2, 8), /* DU0_DB2 */
|
||||
[19] = RCAR_GP_PIN(2, 9), /* DU0_DB3 */
|
||||
[20] = RCAR_GP_PIN(2, 10), /* DU0_DB4 */
|
||||
[21] = RCAR_GP_PIN(2, 11), /* DU0_DB5 */
|
||||
[22] = RCAR_GP_PIN(2, 12), /* DU0_DB6 */
|
||||
[23] = RCAR_GP_PIN(2, 13), /* DU0_DB7 */
|
||||
[24] = RCAR_GP_PIN(2, 14), /* DU0_DOTCLKIN */
|
||||
[25] = RCAR_GP_PIN(2, 15), /* DU0_DOTCLKOUT0 */
|
||||
[26] = RCAR_GP_PIN(2, 17), /* DU0_HSYNC */
|
||||
[27] = RCAR_GP_PIN(2, 18), /* DU0_VSYNC */
|
||||
[28] = RCAR_GP_PIN(2, 19), /* DU0_EXODDF */
|
||||
[29] = RCAR_GP_PIN(2, 20), /* DU0_DISP */
|
||||
[30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */
|
||||
[31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */
|
||||
[ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */
|
||||
[ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */
|
||||
[ 3] = RCAR_GP_PIN(3, 27), /* /VI0_HSYNC */
|
||||
[ 4] = RCAR_GP_PIN(3, 28), /* /VI0_VSYNC */
|
||||
[ 5] = RCAR_GP_PIN(3, 29), /* VI0_DATA0 */
|
||||
[ 6] = RCAR_GP_PIN(3, 30), /* VI0_DATA1 */
|
||||
[ 7] = RCAR_GP_PIN(3, 31), /* VI0_DATA2 */
|
||||
[ 8] = RCAR_GP_PIN(4, 0), /* VI0_DATA3 */
|
||||
[ 9] = RCAR_GP_PIN(4, 1), /* VI0_DATA4 */
|
||||
[10] = RCAR_GP_PIN(4, 2), /* VI0_DATA5 */
|
||||
[11] = RCAR_GP_PIN(4, 3), /* VI0_DATA6 */
|
||||
[12] = RCAR_GP_PIN(4, 4), /* VI0_DATA7 */
|
||||
[13] = RCAR_GP_PIN(4, 5), /* VI0_G2 */
|
||||
[14] = RCAR_GP_PIN(4, 6), /* VI0_G3 */
|
||||
[15] = RCAR_GP_PIN(4, 7), /* VI0_G4 */
|
||||
[16] = RCAR_GP_PIN(4, 8), /* VI0_G5 */
|
||||
[17] = RCAR_GP_PIN(4, 21), /* VI1_DATA12 */
|
||||
[18] = RCAR_GP_PIN(4, 22), /* VI1_DATA13 */
|
||||
[19] = RCAR_GP_PIN(4, 23), /* VI1_DATA14 */
|
||||
[20] = RCAR_GP_PIN(4, 24), /* VI1_DATA15 */
|
||||
[21] = RCAR_GP_PIN(4, 9), /* ETH_REF_CLK */
|
||||
[22] = RCAR_GP_PIN(4, 10), /* ETH_TXD0 */
|
||||
[23] = RCAR_GP_PIN(4, 11), /* ETH_TXD1 */
|
||||
[24] = RCAR_GP_PIN(4, 12), /* ETH_CRS_DV */
|
||||
[25] = RCAR_GP_PIN(4, 13), /* ETH_TX_EN */
|
||||
[26] = RCAR_GP_PIN(4, 14), /* ETH_RX_ER */
|
||||
[27] = RCAR_GP_PIN(4, 15), /* ETH_RXD0 */
|
||||
[28] = RCAR_GP_PIN(4, 16), /* ETH_RXD1 */
|
||||
[29] = RCAR_GP_PIN(4, 17), /* ETH_MDC */
|
||||
[30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */
|
||||
[31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */
|
||||
[ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */
|
||||
[ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */
|
||||
[ 3] = RCAR_GP_PIN(3, 9), /* SSI_SDATA1 */
|
||||
[ 4] = RCAR_GP_PIN(3, 8), /* SSI_SDATA2 */
|
||||
[ 5] = RCAR_GP_PIN(3, 2), /* SSI_SCK34 */
|
||||
[ 6] = RCAR_GP_PIN(3, 3), /* SSI_WS34 */
|
||||
[ 7] = RCAR_GP_PIN(3, 5), /* SSI_SDATA3 */
|
||||
[ 8] = RCAR_GP_PIN(3, 4), /* SSI_SDATA4 */
|
||||
[ 9] = RCAR_GP_PIN(2, 31), /* SSI_SCK5 */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SSI_WS5 */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SSI_SDATA5 */
|
||||
[12] = RCAR_GP_PIN(2, 28), /* SSI_SCK6 */
|
||||
[13] = RCAR_GP_PIN(2, 29), /* SSI_WS6 */
|
||||
[14] = RCAR_GP_PIN(2, 30), /* SSI_SDATA6 */
|
||||
[15] = RCAR_GP_PIN(2, 24), /* SSI_SCK78 */
|
||||
[16] = RCAR_GP_PIN(2, 25), /* SSI_WS78 */
|
||||
[17] = RCAR_GP_PIN(2, 27), /* SSI_SDATA7 */
|
||||
[18] = RCAR_GP_PIN(2, 26), /* SSI_SDATA8 */
|
||||
[19] = RCAR_GP_PIN(3, 23), /* TCLK0 */
|
||||
[20] = RCAR_GP_PIN(3, 11), /* SD0_CLK */
|
||||
[21] = RCAR_GP_PIN(3, 12), /* SD0_CMD */
|
||||
[22] = RCAR_GP_PIN(3, 13), /* SD0_DAT0 */
|
||||
[23] = RCAR_GP_PIN(3, 14), /* SD0_DAT1 */
|
||||
[24] = RCAR_GP_PIN(3, 15), /* SD0_DAT2 */
|
||||
[25] = RCAR_GP_PIN(3, 16), /* SD0_DAT3 */
|
||||
[26] = RCAR_GP_PIN(3, 17), /* SD0_CD */
|
||||
[27] = RCAR_GP_PIN(3, 18), /* SD0_WP */
|
||||
[28] = RCAR_GP_PIN(2, 22), /* AUDIO_CLKA */
|
||||
[29] = RCAR_GP_PIN(2, 23), /* AUDIO_CLKB */
|
||||
[30] = RCAR_GP_PIN(1, 14), /* IRQ2 */
|
||||
[31] = RCAR_GP_PIN(1, 15), /* IRQ3 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */
|
||||
[ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */
|
||||
[ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */
|
||||
[ 3] = RCAR_GP_PIN(0, 4), /* USB_OVC1 */
|
||||
[ 4] = RCAR_GP_PIN(1, 16), /* SCIF_CLK */
|
||||
[ 5] = RCAR_GP_PIN(1, 17), /* TX0 */
|
||||
[ 6] = RCAR_GP_PIN(1, 18), /* RX0 */
|
||||
[ 7] = RCAR_GP_PIN(1, 19), /* SCK0 */
|
||||
[ 8] = RCAR_GP_PIN(1, 20), /* /CTS0 */
|
||||
[ 9] = RCAR_GP_PIN(1, 21), /* /RTS0 */
|
||||
[10] = RCAR_GP_PIN(3, 19), /* HSPI_CLK0 */
|
||||
[11] = RCAR_GP_PIN(3, 20), /* /HSPI_CS0 */
|
||||
[12] = RCAR_GP_PIN(3, 21), /* HSPI_RX0 */
|
||||
[13] = RCAR_GP_PIN(3, 22), /* HSPI_TX0 */
|
||||
[14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
|
||||
[15] = RCAR_GP_PIN(4, 25), /* AVS1 */
|
||||
[16] = RCAR_GP_PIN(4, 26), /* AVS2 */
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct sh_pfc_bias_info *info;
|
||||
const struct pinmux_bias_reg *reg;
|
||||
void __iomem *addr;
|
||||
unsigned int bit;
|
||||
|
||||
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
|
||||
if (!info)
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
addr = pfc->windows->virt + info->reg;
|
||||
addr = pfc->windows->virt + reg->puen;
|
||||
|
||||
if (ioread32(addr) & BIT(info->bit))
|
||||
if (ioread32(addr) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
@ -3103,21 +3144,20 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct sh_pfc_bias_info *info;
|
||||
const struct pinmux_bias_reg *reg;
|
||||
void __iomem *addr;
|
||||
unsigned int bit;
|
||||
u32 value;
|
||||
u32 bit;
|
||||
|
||||
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
|
||||
if (!info)
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
addr = pfc->windows->virt + info->reg;
|
||||
bit = BIT(info->bit);
|
||||
addr = pfc->windows->virt + reg->puen;
|
||||
|
||||
value = ioread32(addr) & ~bit;
|
||||
value = ioread32(addr) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
value |= bit;
|
||||
value |= BIT(bit);
|
||||
iowrite32(value, addr);
|
||||
}
|
||||
|
||||
@ -3144,6 +3184,7 @@ const struct sh_pfc_soc_info r8a7778_pinmux_info = {
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
||||
@ -5097,6 +5097,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7745
|
||||
const struct sh_pfc_soc_info r8a7745_pinmux_info = {
|
||||
.name = "r8a77450_pfc",
|
||||
.ops = &r8a7794_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -1443,12 +1443,13 @@ static const u16 pinmux_data[] = {
|
||||
};
|
||||
|
||||
/*
|
||||
* R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
|
||||
* R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
|
||||
* Physical layout rows: A - AW, cols: 1 - 39.
|
||||
*/
|
||||
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
|
||||
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
|
||||
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
|
||||
#define PIN_NONE U16_MAX
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
@ -3101,23 +3102,6 @@ static const unsigned int pwm6_b_mux[] = {
|
||||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - USB30 ------------------------------------------------------------------ */
|
||||
static const unsigned int usb30_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int usb30_mux[] = {
|
||||
USB30_PWEN_MARK, USB30_OVC_MARK,
|
||||
};
|
||||
/* - USB31 ------------------------------------------------------------------ */
|
||||
static const unsigned int usb31_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
static const unsigned int usb31_mux[] = {
|
||||
USB31_PWEN_MARK, USB31_OVC_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
@ -3791,6 +3775,23 @@ static const unsigned int usb2_mux[] = {
|
||||
USB2_PWEN_MARK, USB2_OVC_MARK,
|
||||
};
|
||||
|
||||
/* - USB30 ------------------------------------------------------------------ */
|
||||
static const unsigned int usb30_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int usb30_mux[] = {
|
||||
USB30_PWEN_MARK, USB30_OVC_MARK,
|
||||
};
|
||||
/* - USB31 ------------------------------------------------------------------ */
|
||||
static const unsigned int usb31_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
static const unsigned int usb31_mux[] = {
|
||||
USB31_PWEN_MARK, USB31_OVC_MARK,
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_b),
|
||||
@ -5422,12 +5423,21 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
POCCTRL,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL] = { 0xe6060380, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
*pocctrl = 0xe6060380;
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
|
||||
bit = pin & 0x1f;
|
||||
@ -5438,242 +5448,261 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
return bit;
|
||||
}
|
||||
|
||||
#define PUEN 0xe6060400
|
||||
#define PUD 0xe6060440
|
||||
|
||||
#define PU0 0x00
|
||||
#define PU1 0x04
|
||||
#define PU2 0x08
|
||||
#define PU3 0x0c
|
||||
#define PU4 0x10
|
||||
#define PU5 0x14
|
||||
#define PU6 0x18
|
||||
|
||||
static const struct sh_pfc_bias_info bias_info[] = {
|
||||
{ RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
|
||||
{ RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
|
||||
{ PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
|
||||
{ PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
|
||||
{ PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
|
||||
{ PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
|
||||
{ PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
|
||||
{ PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
|
||||
{ PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
|
||||
{ PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
|
||||
{ PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
|
||||
{ PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
|
||||
{ PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
|
||||
{ PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
|
||||
{ PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
|
||||
{ PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
|
||||
{ PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
|
||||
{ PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
|
||||
{ PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
|
||||
{ PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
|
||||
{ PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
|
||||
{ PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
|
||||
{ PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
|
||||
{ PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
|
||||
{ PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
|
||||
{ PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
|
||||
{ PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
|
||||
|
||||
{ RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
|
||||
{ RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
|
||||
{ RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
|
||||
{ RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
|
||||
{ RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
|
||||
{ RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
|
||||
{ RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
|
||||
{ RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
|
||||
{ RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
|
||||
{ RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
|
||||
{ RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
|
||||
{ RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
|
||||
{ RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
|
||||
{ RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
|
||||
{ RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
|
||||
{ RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
|
||||
{ RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
|
||||
{ RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
|
||||
{ RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
|
||||
{ RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
|
||||
{ RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
|
||||
{ RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
|
||||
{ RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
|
||||
{ RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
|
||||
{ RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
|
||||
{ RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
|
||||
{ RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
|
||||
{ RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
|
||||
{ RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
|
||||
{ RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
|
||||
{ RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
|
||||
{ RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
|
||||
|
||||
{ PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
|
||||
{ PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
|
||||
{ RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
|
||||
{ RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
|
||||
{ RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
|
||||
{ RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
|
||||
{ RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
|
||||
{ RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
|
||||
{ RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
|
||||
{ RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
|
||||
{ RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
|
||||
{ RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
|
||||
{ RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
|
||||
{ RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
|
||||
{ RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
|
||||
{ RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
|
||||
{ RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
|
||||
{ RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
|
||||
{ RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
|
||||
{ PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
|
||||
{ RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
|
||||
{ RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
|
||||
{ RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
|
||||
{ RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
|
||||
{ RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
|
||||
{ RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
|
||||
{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
|
||||
{ RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
|
||||
{ PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
|
||||
|
||||
{ RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
|
||||
{ RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
|
||||
{ RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
|
||||
{ RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
|
||||
{ RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
|
||||
{ RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
|
||||
{ RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
|
||||
{ RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
|
||||
{ RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
|
||||
{ RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
|
||||
{ RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
|
||||
{ RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
|
||||
{ RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
|
||||
{ RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
|
||||
{ RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
|
||||
{ PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
|
||||
/* bit 8 n/a */
|
||||
{ PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
|
||||
{ PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
|
||||
{ PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
|
||||
{ PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
|
||||
{ PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
|
||||
{ PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
|
||||
{ PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
|
||||
|
||||
{ RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
|
||||
{ RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
|
||||
{ RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
|
||||
{ RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
|
||||
{ RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
|
||||
{ RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
|
||||
{ RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
|
||||
{ RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
|
||||
{ RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
|
||||
{ RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
|
||||
{ RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
|
||||
{ RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
|
||||
{ RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
|
||||
{ RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
|
||||
{ RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
|
||||
{ RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
|
||||
{ RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
|
||||
{ RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
|
||||
{ RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
|
||||
{ RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
|
||||
{ RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
|
||||
{ RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
|
||||
{ RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
|
||||
{ RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
|
||||
{ RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
|
||||
{ RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
|
||||
{ RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
|
||||
{ RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
|
||||
{ RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
|
||||
{ RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
|
||||
{ RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
|
||||
{ RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
|
||||
|
||||
{ RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
|
||||
{ RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
|
||||
{ RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
|
||||
{ RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
|
||||
{ RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
|
||||
{ RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
|
||||
{ RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
|
||||
{ RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
|
||||
{ RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
|
||||
{ RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
|
||||
{ RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
|
||||
{ RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
|
||||
{ RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
|
||||
{ RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
|
||||
{ RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
|
||||
{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
|
||||
{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
|
||||
{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
|
||||
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
|
||||
{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
|
||||
{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
|
||||
{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
|
||||
{ RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
|
||||
{ RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
|
||||
{ PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
|
||||
{ RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
|
||||
{ RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
|
||||
{ RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
|
||||
{ RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
|
||||
{ RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
|
||||
{ RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
|
||||
|
||||
{ RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
|
||||
{ RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
|
||||
{ RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
|
||||
{ RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
|
||||
{ RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
|
||||
{ RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
|
||||
{ RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
|
||||
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
|
||||
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
|
||||
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
|
||||
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
|
||||
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
|
||||
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
|
||||
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
|
||||
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
|
||||
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
|
||||
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
|
||||
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
|
||||
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
|
||||
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
|
||||
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
|
||||
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
|
||||
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
|
||||
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
|
||||
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
|
||||
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
|
||||
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
|
||||
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
|
||||
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
|
||||
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
|
||||
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
|
||||
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
|
||||
[ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
|
||||
[ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
|
||||
[ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
|
||||
[ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
|
||||
[ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
|
||||
[ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
|
||||
[ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
|
||||
[ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
|
||||
[ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
|
||||
[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
|
||||
[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
|
||||
[12] = RCAR_GP_PIN(1, 0), /* A0 */
|
||||
[13] = RCAR_GP_PIN(1, 1), /* A1 */
|
||||
[14] = RCAR_GP_PIN(1, 2), /* A2 */
|
||||
[15] = RCAR_GP_PIN(1, 3), /* A3 */
|
||||
[16] = RCAR_GP_PIN(1, 4), /* A4 */
|
||||
[17] = RCAR_GP_PIN(1, 5), /* A5 */
|
||||
[18] = RCAR_GP_PIN(1, 6), /* A6 */
|
||||
[19] = RCAR_GP_PIN(1, 7), /* A7 */
|
||||
[20] = RCAR_GP_PIN(1, 8), /* A8 */
|
||||
[21] = RCAR_GP_PIN(1, 9), /* A9 */
|
||||
[22] = RCAR_GP_PIN(1, 10), /* A10 */
|
||||
[23] = RCAR_GP_PIN(1, 11), /* A11 */
|
||||
[24] = RCAR_GP_PIN(1, 12), /* A12 */
|
||||
[25] = RCAR_GP_PIN(1, 13), /* A13 */
|
||||
[26] = RCAR_GP_PIN(1, 14), /* A14 */
|
||||
[27] = RCAR_GP_PIN(1, 15), /* A15 */
|
||||
[28] = RCAR_GP_PIN(1, 16), /* A16 */
|
||||
[29] = RCAR_GP_PIN(1, 17), /* A17 */
|
||||
[30] = RCAR_GP_PIN(1, 18), /* A18 */
|
||||
[31] = RCAR_GP_PIN(1, 19), /* A19 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
|
||||
[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
|
||||
[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
|
||||
[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
|
||||
[ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
|
||||
[ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
|
||||
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
|
||||
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
|
||||
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
|
||||
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
|
||||
[10] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[11] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[12] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
[13] = RCAR_GP_PIN(0, 3), /* D3 */
|
||||
[14] = RCAR_GP_PIN(0, 4), /* D4 */
|
||||
[15] = RCAR_GP_PIN(0, 5), /* D5 */
|
||||
[16] = RCAR_GP_PIN(0, 6), /* D6 */
|
||||
[17] = RCAR_GP_PIN(0, 7), /* D7 */
|
||||
[18] = RCAR_GP_PIN(0, 8), /* D8 */
|
||||
[19] = RCAR_GP_PIN(0, 9), /* D9 */
|
||||
[20] = RCAR_GP_PIN(0, 10), /* D10 */
|
||||
[21] = RCAR_GP_PIN(0, 11), /* D11 */
|
||||
[22] = RCAR_GP_PIN(0, 12), /* D12 */
|
||||
[23] = RCAR_GP_PIN(0, 13), /* D13 */
|
||||
[24] = RCAR_GP_PIN(0, 14), /* D14 */
|
||||
[25] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
|
||||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
|
||||
[ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
|
||||
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
|
||||
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
|
||||
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
|
||||
[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
|
||||
[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
|
||||
[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
|
||||
[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
|
||||
[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
|
||||
[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
|
||||
[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
|
||||
[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
|
||||
[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
|
||||
[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
|
||||
[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
|
||||
[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
|
||||
[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
|
||||
[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
|
||||
[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
|
||||
[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
|
||||
[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
|
||||
[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
|
||||
[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
|
||||
[ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
|
||||
[ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
|
||||
[ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
|
||||
[ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
|
||||
[ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
|
||||
[ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
|
||||
[ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
|
||||
[ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
|
||||
[ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
|
||||
[ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
|
||||
[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
|
||||
[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
|
||||
[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
|
||||
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
|
||||
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
|
||||
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
|
||||
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
|
||||
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
|
||||
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
|
||||
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
|
||||
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
|
||||
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
|
||||
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
|
||||
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
|
||||
[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
|
||||
[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
|
||||
[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
|
||||
[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
|
||||
[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
|
||||
[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
|
||||
[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
|
||||
[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
|
||||
[ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
|
||||
[ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
|
||||
[ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
|
||||
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
|
||||
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
|
||||
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
|
||||
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
|
||||
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
|
||||
[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
|
||||
[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
|
||||
[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
|
||||
[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
|
||||
[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
|
||||
[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
|
||||
[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
|
||||
[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
|
||||
[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
|
||||
[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
|
||||
[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
|
||||
[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
|
||||
[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
|
||||
[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
|
||||
[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
|
||||
[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
|
||||
[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
|
||||
[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
|
||||
[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
|
||||
[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
|
||||
[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
|
||||
[ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
|
||||
[ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
|
||||
[ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
|
||||
[ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
|
||||
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
|
||||
[ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
|
||||
[ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
|
||||
[ 7] = PIN_NONE,
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct sh_pfc_bias_info *info;
|
||||
u32 reg;
|
||||
u32 bit;
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
|
||||
if (!info)
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
reg = info->reg;
|
||||
bit = BIT(info->bit);
|
||||
|
||||
if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
@ -5682,28 +5711,24 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct sh_pfc_bias_info *info;
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
u32 reg;
|
||||
u32 bit;
|
||||
unsigned int bit;
|
||||
|
||||
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
|
||||
if (!info)
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
reg = info->reg;
|
||||
bit = BIT(info->bit);
|
||||
|
||||
enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= bit;
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= bit;
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
|
||||
sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
|
||||
@ -5728,6 +5753,8 @@ const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.drive_regs = pinmux_drive_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -495,7 +495,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
|
||||
#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
|
||||
#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
|
||||
|
||||
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
|
||||
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
|
||||
#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
|
||||
#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
|
||||
#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
|
||||
@ -1518,6 +1518,7 @@ static const u16 pinmux_data[] = {
|
||||
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
|
||||
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
|
||||
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
|
||||
#define PIN_NONE U16_MAX
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
@ -2392,6 +2393,50 @@ static const unsigned int i2c6_c_mux[] = {
|
||||
SDA6_C_MARK, SCL6_C_MARK,
|
||||
};
|
||||
|
||||
/* - INTC-EX ---------------------------------------------------------------- */
|
||||
static const unsigned int intc_ex_irq0_pins[] = {
|
||||
/* IRQ0 */
|
||||
RCAR_GP_PIN(2, 0),
|
||||
};
|
||||
static const unsigned int intc_ex_irq0_mux[] = {
|
||||
IRQ0_MARK,
|
||||
};
|
||||
static const unsigned int intc_ex_irq1_pins[] = {
|
||||
/* IRQ1 */
|
||||
RCAR_GP_PIN(2, 1),
|
||||
};
|
||||
static const unsigned int intc_ex_irq1_mux[] = {
|
||||
IRQ1_MARK,
|
||||
};
|
||||
static const unsigned int intc_ex_irq2_pins[] = {
|
||||
/* IRQ2 */
|
||||
RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int intc_ex_irq2_mux[] = {
|
||||
IRQ2_MARK,
|
||||
};
|
||||
static const unsigned int intc_ex_irq3_pins[] = {
|
||||
/* IRQ3 */
|
||||
RCAR_GP_PIN(2, 3),
|
||||
};
|
||||
static const unsigned int intc_ex_irq3_mux[] = {
|
||||
IRQ3_MARK,
|
||||
};
|
||||
static const unsigned int intc_ex_irq4_pins[] = {
|
||||
/* IRQ4 */
|
||||
RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int intc_ex_irq4_mux[] = {
|
||||
IRQ4_MARK,
|
||||
};
|
||||
static const unsigned int intc_ex_irq5_pins[] = {
|
||||
/* IRQ5 */
|
||||
RCAR_GP_PIN(2, 5),
|
||||
};
|
||||
static const unsigned int intc_ex_irq5_mux[] = {
|
||||
IRQ5_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
@ -3922,6 +3967,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(i2c6_a),
|
||||
SH_PFC_PIN_GROUP(i2c6_b),
|
||||
SH_PFC_PIN_GROUP(i2c6_c),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq0),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq1),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq2),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq3),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq4),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq5),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
SH_PFC_PIN_GROUP(msiof0_ss1),
|
||||
@ -4286,6 +4337,15 @@ static const char * const i2c6_groups[] = {
|
||||
"i2c6_c",
|
||||
};
|
||||
|
||||
static const char * const intc_ex_groups[] = {
|
||||
"intc_ex_irq0",
|
||||
"intc_ex_irq1",
|
||||
"intc_ex_irq2",
|
||||
"intc_ex_irq3",
|
||||
"intc_ex_irq4",
|
||||
"intc_ex_irq5",
|
||||
};
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
@ -4580,6 +4640,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c6),
|
||||
SH_PFC_FUNCTION(intc_ex),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
SH_PFC_FUNCTION(msiof1),
|
||||
SH_PFC_FUNCTION(msiof2),
|
||||
@ -5416,11 +5477,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
POCCTRL,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL] = { 0xe6060380, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
*pocctrl = 0xe6060380;
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
|
||||
bit = pin & 0x1f;
|
||||
@ -5431,242 +5501,261 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
||||
return bit;
|
||||
}
|
||||
|
||||
#define PUEN 0xe6060400
|
||||
#define PUD 0xe6060440
|
||||
|
||||
#define PU0 0x00
|
||||
#define PU1 0x04
|
||||
#define PU2 0x08
|
||||
#define PU3 0x0c
|
||||
#define PU4 0x10
|
||||
#define PU5 0x14
|
||||
#define PU6 0x18
|
||||
|
||||
static const struct sh_pfc_bias_info bias_info[] = {
|
||||
{ RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
|
||||
{ RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
|
||||
{ PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
|
||||
{ PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
|
||||
{ PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
|
||||
{ PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
|
||||
{ PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
|
||||
{ PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
|
||||
{ PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
|
||||
{ PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
|
||||
{ PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
|
||||
{ PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
|
||||
{ PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
|
||||
{ PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
|
||||
{ PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
|
||||
{ PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
|
||||
{ PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
|
||||
{ PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
|
||||
{ PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
|
||||
{ PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
|
||||
{ PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
|
||||
{ PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
|
||||
{ PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
|
||||
{ PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
|
||||
{ PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
|
||||
{ PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
|
||||
{ PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
|
||||
|
||||
{ RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
|
||||
{ RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
|
||||
{ RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
|
||||
{ RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
|
||||
{ RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
|
||||
{ RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
|
||||
{ RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
|
||||
{ RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
|
||||
{ RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
|
||||
{ RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
|
||||
{ RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
|
||||
{ RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
|
||||
{ RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
|
||||
{ RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
|
||||
{ RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
|
||||
{ RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
|
||||
{ RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
|
||||
{ RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
|
||||
{ RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
|
||||
{ RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
|
||||
{ RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
|
||||
{ RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
|
||||
{ RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
|
||||
{ RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
|
||||
{ RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
|
||||
{ RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
|
||||
{ RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
|
||||
{ RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
|
||||
{ RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
|
||||
{ RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
|
||||
{ RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
|
||||
{ RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
|
||||
|
||||
{ PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
|
||||
{ PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
|
||||
{ RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */
|
||||
{ RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
|
||||
{ RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
|
||||
{ RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
|
||||
{ RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
|
||||
{ RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
|
||||
{ RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
|
||||
{ RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
|
||||
{ RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
|
||||
{ RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
|
||||
{ RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
|
||||
{ RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
|
||||
{ RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
|
||||
{ RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
|
||||
{ RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
|
||||
{ RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
|
||||
{ RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
|
||||
{ PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
|
||||
{ RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
|
||||
{ RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
|
||||
{ RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
|
||||
{ RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
|
||||
{ RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
|
||||
{ RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
|
||||
{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
|
||||
{ RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
|
||||
{ RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */
|
||||
|
||||
{ RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
|
||||
{ RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
|
||||
{ RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
|
||||
{ RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
|
||||
{ RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
|
||||
{ RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
|
||||
{ RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
|
||||
{ RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
|
||||
{ RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
|
||||
{ RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
|
||||
{ RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
|
||||
{ RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
|
||||
{ RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
|
||||
{ RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
|
||||
{ RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
|
||||
{ PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
|
||||
/* bit 8 n/a */
|
||||
{ PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
|
||||
{ PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
|
||||
{ PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
|
||||
{ PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
|
||||
{ PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
|
||||
{ PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */
|
||||
/* bit 1 n/a on M3*/
|
||||
{ PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */
|
||||
|
||||
{ RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
|
||||
{ RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
|
||||
{ RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
|
||||
{ RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
|
||||
{ RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
|
||||
{ RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
|
||||
{ RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
|
||||
{ RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
|
||||
{ RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
|
||||
{ RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
|
||||
{ RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
|
||||
{ RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
|
||||
{ RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
|
||||
{ RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
|
||||
{ RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
|
||||
{ RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
|
||||
{ RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
|
||||
{ RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
|
||||
{ RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
|
||||
{ RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
|
||||
{ RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
|
||||
{ RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
|
||||
{ RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
|
||||
{ RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
|
||||
{ RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
|
||||
{ RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
|
||||
{ RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
|
||||
{ RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
|
||||
{ RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
|
||||
{ RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
|
||||
{ RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
|
||||
{ RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
|
||||
|
||||
{ RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
|
||||
{ RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
|
||||
{ RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
|
||||
{ RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
|
||||
{ RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
|
||||
{ RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
|
||||
{ RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
|
||||
{ RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
|
||||
{ RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
|
||||
{ RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
|
||||
{ RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
|
||||
{ RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
|
||||
{ RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
|
||||
{ RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
|
||||
{ RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
|
||||
{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
|
||||
{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
|
||||
{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
|
||||
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
|
||||
{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
|
||||
{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
|
||||
{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
|
||||
{ RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
|
||||
{ RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
|
||||
{ PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
|
||||
{ RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
|
||||
{ RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
|
||||
{ RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
|
||||
{ RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
|
||||
{ RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
|
||||
{ RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
|
||||
|
||||
{ RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */
|
||||
{ RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */
|
||||
{ RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
|
||||
{ RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
|
||||
{ RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
|
||||
{ RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
|
||||
{ RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
|
||||
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
|
||||
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
|
||||
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
|
||||
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
|
||||
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
|
||||
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
|
||||
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
|
||||
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
|
||||
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
|
||||
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
|
||||
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
|
||||
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
|
||||
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
|
||||
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
|
||||
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
|
||||
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
|
||||
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
|
||||
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
|
||||
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
|
||||
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
|
||||
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
|
||||
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
|
||||
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
|
||||
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
|
||||
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
|
||||
[ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
|
||||
[ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
|
||||
[ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
|
||||
[ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
|
||||
[ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
|
||||
[ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
|
||||
[ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
|
||||
[ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
|
||||
[ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
|
||||
[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
|
||||
[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
|
||||
[12] = RCAR_GP_PIN(1, 0), /* A0 */
|
||||
[13] = RCAR_GP_PIN(1, 1), /* A1 */
|
||||
[14] = RCAR_GP_PIN(1, 2), /* A2 */
|
||||
[15] = RCAR_GP_PIN(1, 3), /* A3 */
|
||||
[16] = RCAR_GP_PIN(1, 4), /* A4 */
|
||||
[17] = RCAR_GP_PIN(1, 5), /* A5 */
|
||||
[18] = RCAR_GP_PIN(1, 6), /* A6 */
|
||||
[19] = RCAR_GP_PIN(1, 7), /* A7 */
|
||||
[20] = RCAR_GP_PIN(1, 8), /* A8 */
|
||||
[21] = RCAR_GP_PIN(1, 9), /* A9 */
|
||||
[22] = RCAR_GP_PIN(1, 10), /* A10 */
|
||||
[23] = RCAR_GP_PIN(1, 11), /* A11 */
|
||||
[24] = RCAR_GP_PIN(1, 12), /* A12 */
|
||||
[25] = RCAR_GP_PIN(1, 13), /* A13 */
|
||||
[26] = RCAR_GP_PIN(1, 14), /* A14 */
|
||||
[27] = RCAR_GP_PIN(1, 15), /* A15 */
|
||||
[28] = RCAR_GP_PIN(1, 16), /* A16 */
|
||||
[29] = RCAR_GP_PIN(1, 17), /* A17 */
|
||||
[30] = RCAR_GP_PIN(1, 18), /* A18 */
|
||||
[31] = RCAR_GP_PIN(1, 19), /* A19 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
|
||||
[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
|
||||
[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
|
||||
[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
|
||||
[ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
|
||||
[ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
|
||||
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
|
||||
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
|
||||
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
|
||||
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
|
||||
[10] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[11] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[12] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
[13] = RCAR_GP_PIN(0, 3), /* D3 */
|
||||
[14] = RCAR_GP_PIN(0, 4), /* D4 */
|
||||
[15] = RCAR_GP_PIN(0, 5), /* D5 */
|
||||
[16] = RCAR_GP_PIN(0, 6), /* D6 */
|
||||
[17] = RCAR_GP_PIN(0, 7), /* D7 */
|
||||
[18] = RCAR_GP_PIN(0, 8), /* D8 */
|
||||
[19] = RCAR_GP_PIN(0, 9), /* D9 */
|
||||
[20] = RCAR_GP_PIN(0, 10), /* D10 */
|
||||
[21] = RCAR_GP_PIN(0, 11), /* D11 */
|
||||
[22] = RCAR_GP_PIN(0, 12), /* D12 */
|
||||
[23] = RCAR_GP_PIN(0, 13), /* D13 */
|
||||
[24] = RCAR_GP_PIN(0, 14), /* D14 */
|
||||
[25] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
|
||||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
|
||||
[ 1] = PIN_NONE,
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
|
||||
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
|
||||
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
|
||||
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
|
||||
[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
|
||||
[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
|
||||
[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
|
||||
[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
|
||||
[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
|
||||
[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
|
||||
[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
|
||||
[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
|
||||
[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
|
||||
[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
|
||||
[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
|
||||
[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
|
||||
[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
|
||||
[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
|
||||
[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
|
||||
[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
|
||||
[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
|
||||
[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
|
||||
[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
|
||||
[ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
|
||||
[ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
|
||||
[ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
|
||||
[ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
|
||||
[ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
|
||||
[ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
|
||||
[ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
|
||||
[ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
|
||||
[ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
|
||||
[ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
|
||||
[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
|
||||
[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
|
||||
[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
|
||||
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
|
||||
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
|
||||
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
|
||||
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
|
||||
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
|
||||
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
|
||||
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
|
||||
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
|
||||
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
|
||||
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
|
||||
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
|
||||
[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
|
||||
[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
|
||||
[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
|
||||
[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
|
||||
[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
|
||||
[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
|
||||
[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
|
||||
[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
|
||||
[ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
|
||||
[ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
|
||||
[ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
|
||||
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
|
||||
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
|
||||
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
|
||||
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
|
||||
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
|
||||
[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
|
||||
[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
|
||||
[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
|
||||
[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
|
||||
[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
|
||||
[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
|
||||
[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
|
||||
[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
|
||||
[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
|
||||
[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
|
||||
[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
|
||||
[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
|
||||
[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
|
||||
[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
|
||||
[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
|
||||
[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
|
||||
[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
|
||||
[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
|
||||
[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
|
||||
[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
|
||||
[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
|
||||
[ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
|
||||
[ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
|
||||
[ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
|
||||
[ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
|
||||
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
|
||||
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
|
||||
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
|
||||
[ 7] = PIN_NONE,
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct sh_pfc_bias_info *info;
|
||||
u32 reg;
|
||||
u32 bit;
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
|
||||
if (!info)
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
reg = info->reg;
|
||||
bit = BIT(info->bit);
|
||||
|
||||
if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
@ -5675,28 +5764,24 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct sh_pfc_bias_info *info;
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
u32 reg;
|
||||
u32 bit;
|
||||
unsigned int bit;
|
||||
|
||||
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
|
||||
if (!info)
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
reg = info->reg;
|
||||
bit = BIT(info->bit);
|
||||
|
||||
enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= bit;
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= bit;
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
|
||||
sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
|
||||
@ -5721,6 +5806,8 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = {
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.drive_regs = pinmux_drive_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
||||
@ -198,8 +198,8 @@
|
||||
#define GPSR6_0 FM(QSPI0_SPCLK)
|
||||
|
||||
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
@ -522,10 +522,8 @@ static const u16 pinmux_data[] = {
|
||||
/* IPSR0 */
|
||||
PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
|
||||
PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
|
||||
PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
|
||||
PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
|
||||
PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
|
||||
@ -936,6 +934,36 @@ static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ------------------------------------------------------------- */
|
||||
static const unsigned int audio_clk_a_pins[] = {
|
||||
/* CLK A */
|
||||
RCAR_GP_PIN(4, 1),
|
||||
};
|
||||
static const unsigned int audio_clk_a_mux[] = {
|
||||
AUDIO_CLKA_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_b_pins[] = {
|
||||
/* CLK B */
|
||||
RCAR_GP_PIN(2, 27),
|
||||
};
|
||||
static const unsigned int audio_clk_b_mux[] = {
|
||||
AUDIO_CLKB_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int audio_clkout_mux[] = {
|
||||
AUDIO_CLKOUT_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout1_pins[] = {
|
||||
/* CLKOUT1 */
|
||||
RCAR_GP_PIN(4, 22),
|
||||
};
|
||||
static const unsigned int audio_clkout1_mux[] = {
|
||||
AUDIO_CLKOUT1_MARK,
|
||||
};
|
||||
|
||||
/* - EtherAVB --------------------------------------------------------------- */
|
||||
static const unsigned int avb0_link_pins[] = {
|
||||
/* AVB0_LINK */
|
||||
@ -1111,6 +1139,118 @@ static const unsigned int mmc_ctrl_mux[] = {
|
||||
MMC_CLK_MARK, MMC_CMD_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0 ------------------------------------------------------------------ */
|
||||
static const unsigned int pwm0_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 1),
|
||||
};
|
||||
|
||||
static const unsigned int pwm0_a_mux[] = {
|
||||
PWM0_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm0_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 18),
|
||||
};
|
||||
|
||||
static const unsigned int pwm0_b_mux[] = {
|
||||
PWM0_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm0_c_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 29),
|
||||
};
|
||||
|
||||
static const unsigned int pwm0_c_mux[] = {
|
||||
PWM0_C_MARK,
|
||||
};
|
||||
|
||||
/* - PWM1 ------------------------------------------------------------------ */
|
||||
static const unsigned int pwm1_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
|
||||
static const unsigned int pwm1_a_mux[] = {
|
||||
PWM1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm1_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 19),
|
||||
};
|
||||
|
||||
static const unsigned int pwm1_b_mux[] = {
|
||||
PWM1_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm1_c_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 30),
|
||||
};
|
||||
|
||||
static const unsigned int pwm1_c_mux[] = {
|
||||
PWM1_C_MARK,
|
||||
};
|
||||
|
||||
/* - PWM2 ------------------------------------------------------------------ */
|
||||
static const unsigned int pwm2_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 3),
|
||||
};
|
||||
|
||||
static const unsigned int pwm2_a_mux[] = {
|
||||
PWM2_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm2_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 22),
|
||||
};
|
||||
|
||||
static const unsigned int pwm2_b_mux[] = {
|
||||
PWM2_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm2_c_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 31),
|
||||
};
|
||||
|
||||
static const unsigned int pwm2_c_mux[] = {
|
||||
PWM2_C_MARK,
|
||||
};
|
||||
|
||||
/* - PWM3 ------------------------------------------------------------------ */
|
||||
static const unsigned int pwm3_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
|
||||
static const unsigned int pwm3_a_mux[] = {
|
||||
PWM3_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm3_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 27),
|
||||
};
|
||||
|
||||
static const unsigned int pwm3_b_mux[] = {
|
||||
PWM3_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int pwm3_c_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(4, 0),
|
||||
};
|
||||
|
||||
static const unsigned int pwm3_c_mux[] = {
|
||||
PWM3_C_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_a_pins[] = {
|
||||
/* RX, TX */
|
||||
@ -1295,6 +1435,50 @@ static const unsigned int scif_clk_mux[] = {
|
||||
SCIF_CLK_MARK,
|
||||
};
|
||||
|
||||
/* - SSI ---------------------------------------------------------------*/
|
||||
static const unsigned int ssi3_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(4, 3),
|
||||
};
|
||||
static const unsigned int ssi3_data_mux[] = {
|
||||
SSI_SDATA3_MARK,
|
||||
};
|
||||
static const unsigned int ssi34_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
|
||||
};
|
||||
static const unsigned int ssi34_ctrl_mux[] = {
|
||||
SSI_SCK34_MARK, SSI_WS34_MARK,
|
||||
};
|
||||
static const unsigned int ssi4_ctrl_a_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
|
||||
};
|
||||
static const unsigned int ssi4_ctrl_a_mux[] = {
|
||||
SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi4_data_a_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(4, 6),
|
||||
};
|
||||
static const unsigned int ssi4_data_a_mux[] = {
|
||||
SSI_SDATA4_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi4_ctrl_b_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
|
||||
};
|
||||
static const unsigned int ssi4_ctrl_b_mux[] = {
|
||||
SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
|
||||
};
|
||||
static const unsigned int ssi4_data_b_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(2, 16),
|
||||
};
|
||||
static const unsigned int ssi4_data_b_mux[] = {
|
||||
SSI_SDATA4_B_MARK,
|
||||
};
|
||||
|
||||
/* - USB0 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb0_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
@ -1305,6 +1489,10 @@ static const unsigned int usb0_mux[] = {
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_b),
|
||||
SH_PFC_PIN_GROUP(audio_clkout),
|
||||
SH_PFC_PIN_GROUP(audio_clkout1),
|
||||
SH_PFC_PIN_GROUP(avb0_link),
|
||||
SH_PFC_PIN_GROUP(avb0_magic),
|
||||
SH_PFC_PIN_GROUP(avb0_phy_int),
|
||||
@ -1326,6 +1514,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(pwm0_a),
|
||||
SH_PFC_PIN_GROUP(pwm0_b),
|
||||
SH_PFC_PIN_GROUP(pwm0_c),
|
||||
SH_PFC_PIN_GROUP(pwm1_a),
|
||||
SH_PFC_PIN_GROUP(pwm1_b),
|
||||
SH_PFC_PIN_GROUP(pwm1_c),
|
||||
SH_PFC_PIN_GROUP(pwm2_a),
|
||||
SH_PFC_PIN_GROUP(pwm2_b),
|
||||
SH_PFC_PIN_GROUP(pwm2_c),
|
||||
SH_PFC_PIN_GROUP(pwm3_a),
|
||||
SH_PFC_PIN_GROUP(pwm3_b),
|
||||
SH_PFC_PIN_GROUP(pwm3_c),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
@ -1351,9 +1551,22 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif5_data_b),
|
||||
SH_PFC_PIN_GROUP(scif5_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif_clk),
|
||||
SH_PFC_PIN_GROUP(ssi3_data),
|
||||
SH_PFC_PIN_GROUP(ssi34_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi4_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi4_data_a),
|
||||
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(ssi4_data_b),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
"audio_clk_a",
|
||||
"audio_clk_b",
|
||||
"audio_clkout",
|
||||
"audio_clkout1",
|
||||
};
|
||||
|
||||
static const char * const avb0_groups[] = {
|
||||
"avb0_link",
|
||||
"avb0_magic",
|
||||
@ -1392,6 +1605,30 @@ static const char * const mmc_groups[] = {
|
||||
"mmc_ctrl",
|
||||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"pwm0_a",
|
||||
"pwm0_b",
|
||||
"pwm0_c",
|
||||
};
|
||||
|
||||
static const char * const pwm1_groups[] = {
|
||||
"pwm1_a",
|
||||
"pwm1_b",
|
||||
"pwm1_c",
|
||||
};
|
||||
|
||||
static const char * const pwm2_groups[] = {
|
||||
"pwm2_a",
|
||||
"pwm2_b",
|
||||
"pwm2_c",
|
||||
};
|
||||
|
||||
static const char * const pwm3_groups[] = {
|
||||
"pwm3_a",
|
||||
"pwm3_b",
|
||||
"pwm3_c",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data_a",
|
||||
"scif0_clk_a",
|
||||
@ -1438,17 +1675,31 @@ static const char * const scif_clk_groups[] = {
|
||||
"scif_clk",
|
||||
};
|
||||
|
||||
static const char * const ssi_groups[] = {
|
||||
"ssi3_data",
|
||||
"ssi34_ctrl",
|
||||
"ssi4_ctrl_a",
|
||||
"ssi4_data_a",
|
||||
"ssi4_ctrl_b",
|
||||
"ssi4_data_b",
|
||||
};
|
||||
|
||||
static const char * const usb0_groups[] = {
|
||||
"usb0",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb0),
|
||||
SH_PFC_FUNCTION(i2c0),
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(mmc),
|
||||
SH_PFC_FUNCTION(pwm0),
|
||||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
@ -1456,6 +1707,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(scif4),
|
||||
SH_PFC_FUNCTION(scif5),
|
||||
SH_PFC_FUNCTION(scif_clk),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
};
|
||||
|
||||
|
||||
@ -513,7 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
val = sh_pfc_read_reg(pfc, reg, 32);
|
||||
val = sh_pfc_read(pfc, reg);
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
val = (val >> offset) & GENMASK(size - 1, 0);
|
||||
@ -550,11 +550,11 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
|
||||
val = sh_pfc_read_reg(pfc, reg, 32);
|
||||
val = sh_pfc_read(pfc, reg);
|
||||
val &= ~GENMASK(offset + size - 1, offset);
|
||||
val |= strength << offset;
|
||||
|
||||
sh_pfc_write_reg(pfc, reg, 32, val);
|
||||
sh_pfc_write(pfc, reg, val);
|
||||
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
@ -645,7 +645,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
|
||||
return bit;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
val = sh_pfc_read_reg(pfc, pocctrl, 32);
|
||||
val = sh_pfc_read(pfc, pocctrl);
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
arg = (val & BIT(bit)) ? 3300 : 1800;
|
||||
@ -716,12 +716,12 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
val = sh_pfc_read_reg(pfc, pocctrl, 32);
|
||||
val = sh_pfc_read(pfc, pocctrl);
|
||||
if (mV == 3300)
|
||||
val |= BIT(bit);
|
||||
else
|
||||
val &= ~BIT(bit);
|
||||
sh_pfc_write_reg(pfc, pocctrl, 32, val);
|
||||
sh_pfc_write(pfc, pocctrl, val);
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
|
||||
break;
|
||||
|
||||
@ -148,6 +148,21 @@ struct pinmux_drive_reg {
|
||||
.reg = r, \
|
||||
.fields =
|
||||
|
||||
struct pinmux_bias_reg {
|
||||
u32 puen; /* Pull-enable or pull-up control register */
|
||||
u32 pud; /* Pull-up/down control register (optional) */
|
||||
const u16 pins[32];
|
||||
};
|
||||
|
||||
#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
|
||||
.puen = r1, \
|
||||
.pud = r2, \
|
||||
.pins =
|
||||
|
||||
struct pinmux_ioctrl_reg {
|
||||
u32 reg;
|
||||
};
|
||||
|
||||
struct pinmux_data_reg {
|
||||
u32 reg;
|
||||
u8 reg_width;
|
||||
@ -189,12 +204,6 @@ struct sh_pfc_window {
|
||||
unsigned long size;
|
||||
};
|
||||
|
||||
struct sh_pfc_bias_info {
|
||||
u16 pin;
|
||||
u16 reg : 11;
|
||||
u16 bit : 5;
|
||||
};
|
||||
|
||||
struct sh_pfc_pin_range;
|
||||
|
||||
struct sh_pfc {
|
||||
@ -213,6 +222,7 @@ struct sh_pfc {
|
||||
unsigned int nr_gpio_pins;
|
||||
|
||||
struct sh_pfc_chip *gpio;
|
||||
u32 *saved_regs;
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_operations {
|
||||
@ -245,6 +255,8 @@ struct sh_pfc_soc_info {
|
||||
|
||||
const struct pinmux_cfg_reg *cfg_regs;
|
||||
const struct pinmux_drive_reg *drive_regs;
|
||||
const struct pinmux_bias_reg *bias_regs;
|
||||
const struct pinmux_ioctrl_reg *ioctrl_regs;
|
||||
const struct pinmux_data_reg *data_regs;
|
||||
|
||||
const u16 *pinmux_data;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user