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ionic: dynamic interrupt moderation
Use the dim library to manage dynamic interrupt moderation in ionic. v3: rebase v2: untangled declarations in ionic_dim_work() Signed-off-by: Shannon Nelson <snelson@pensando.io> Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -189,6 +189,8 @@ void ionic_debugfs_add_qcq(struct ionic_lif *lif, struct ionic_qcq *qcq)
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&intr->index);
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debugfs_create_u32("vector", 0400, intr_dentry,
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&intr->vector);
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debugfs_create_u32("dim_coal_hw", 0400, intr_dentry,
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&intr->dim_coal_hw);
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intr_ctrl_regset = devm_kzalloc(dev, sizeof(*intr_ctrl_regset),
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GFP_KERNEL);
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@ -237,6 +237,7 @@ struct ionic_intr_info {
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u64 rearm_count;
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unsigned int cpu;
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cpumask_t affinity_mask;
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u32 dim_coal_hw;
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};
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struct ionic_cq {
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@ -406,6 +406,13 @@ static int ionic_get_coalesce(struct net_device *netdev,
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coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs;
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coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs;
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if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
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coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
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else
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coalesce->use_adaptive_tx_coalesce = 0;
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coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
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return 0;
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}
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@ -414,10 +421,9 @@ static int ionic_set_coalesce(struct net_device *netdev,
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic_identity *ident;
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struct ionic_qcq *qcq;
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u32 rx_coal, rx_dim;
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u32 tx_coal, tx_dim;
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unsigned int i;
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u32 rx_coal;
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u32 tx_coal;
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ident = &lif->ionic->ident;
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if (ident->dev.intr_coal_div == 0) {
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@ -426,10 +432,11 @@ static int ionic_set_coalesce(struct net_device *netdev,
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return -EIO;
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}
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/* Tx normally shares Rx interrupt, so only change Rx */
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/* Tx normally shares Rx interrupt, so only change Rx if not split */
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if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) &&
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coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs) {
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netdev_warn(netdev, "only the rx-usecs can be changed\n");
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(coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs ||
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coalesce->use_adaptive_tx_coalesce)) {
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netdev_warn(netdev, "only rx parameters can be changed\n");
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return -EINVAL;
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}
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@ -449,32 +456,44 @@ static int ionic_set_coalesce(struct net_device *netdev,
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/* Save the new values */
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lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs;
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if (rx_coal != lif->rx_coalesce_hw) {
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lif->rx_coalesce_hw = rx_coal;
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if (test_bit(IONIC_LIF_F_UP, lif->state)) {
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for (i = 0; i < lif->nxqs; i++) {
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qcq = lif->rxqcqs[i];
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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qcq->intr.index,
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lif->rx_coalesce_hw);
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}
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}
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}
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lif->rx_coalesce_hw = rx_coal;
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if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
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lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs;
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else
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lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs;
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if (tx_coal != lif->tx_coalesce_hw) {
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lif->tx_coalesce_hw = tx_coal;
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lif->tx_coalesce_hw = tx_coal;
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if (test_bit(IONIC_LIF_F_UP, lif->state)) {
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for (i = 0; i < lif->nxqs; i++) {
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qcq = lif->txqcqs[i];
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if (coalesce->use_adaptive_rx_coalesce) {
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set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
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rx_dim = rx_coal;
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} else {
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clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
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rx_dim = 0;
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}
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if (coalesce->use_adaptive_tx_coalesce) {
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set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
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tx_dim = tx_coal;
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} else {
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clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
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tx_dim = 0;
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}
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if (test_bit(IONIC_LIF_F_UP, lif->state)) {
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for (i = 0; i < lif->nxqs; i++) {
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if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) {
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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qcq->intr.index,
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lif->rxqcqs[i]->intr.index,
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lif->rx_coalesce_hw);
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lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim;
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}
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if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) {
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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lif->txqcqs[i]->intr.index,
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lif->tx_coalesce_hw);
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lif->txqcqs[i]->intr.dim_coal_hw = tx_dim;
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}
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}
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}
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@ -850,7 +869,9 @@ static int ionic_nway_reset(struct net_device *netdev)
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}
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static const struct ethtool_ops ionic_ethtool_ops = {
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.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
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.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
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ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
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ETHTOOL_COALESCE_USE_ADAPTIVE_TX,
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.get_drvinfo = ionic_get_drvinfo,
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.get_regs_len = ionic_get_regs_len,
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.get_regs = ionic_get_regs,
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@ -42,6 +42,20 @@ static int ionic_start_queues(struct ionic_lif *lif);
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static void ionic_stop_queues(struct ionic_lif *lif);
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static void ionic_lif_queue_identify(struct ionic_lif *lif);
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static void ionic_dim_work(struct work_struct *work)
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{
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struct dim *dim = container_of(work, struct dim, work);
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struct dim_cq_moder cur_moder;
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struct ionic_qcq *qcq;
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u32 new_coal;
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cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
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qcq = container_of(dim, struct ionic_qcq, dim);
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new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
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qcq->intr.dim_coal_hw = new_coal ? new_coal : 1;
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dim->state = DIM_START_MEASURE;
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}
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static void ionic_lif_deferred_work(struct work_struct *work)
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{
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struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
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@ -270,6 +284,7 @@ static int ionic_qcq_disable(struct ionic_qcq *qcq)
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ctx.cmd.q_control.index, ctx.cmd.q_control.type);
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if (qcq->flags & IONIC_QCQ_F_INTR) {
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cancel_work_sync(&qcq->dim.work);
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ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
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IONIC_INTR_MASK_SET);
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synchronize_irq(qcq->intr.vector);
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@ -542,6 +557,9 @@ static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
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ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
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}
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INIT_WORK(&new->dim.work, ionic_dim_work);
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new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
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*qcq = new;
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return 0;
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@ -834,7 +852,7 @@ static int ionic_adminq_napi(struct napi_struct *napi, int budget)
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work_done = max(n_work, a_work);
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if (work_done < budget && napi_complete_done(napi, work_done)) {
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flags |= IONIC_INTR_CRED_UNMASK;
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DEBUG_STATS_INTR_REARM(intr);
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lif->adminqcq->cq.bound_intr->rearm_count++;
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}
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if (work_done || flags) {
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@ -1639,10 +1657,13 @@ static int ionic_txrx_alloc(struct ionic_lif *lif)
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if (err)
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goto err_out;
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if (flags & IONIC_QCQ_F_INTR)
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if (flags & IONIC_QCQ_F_INTR) {
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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lif->txqcqs[i]->intr.index,
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lif->tx_coalesce_hw);
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if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
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lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
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}
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ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
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}
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@ -1661,6 +1682,8 @@ static int ionic_txrx_alloc(struct ionic_lif *lif)
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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lif->rxqcqs[i]->intr.index,
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lif->rx_coalesce_hw);
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if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
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lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
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if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
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ionic_link_qcq_interrupts(lif->rxqcqs[i],
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@ -2234,6 +2257,8 @@ int ionic_reconfigure_queues(struct ionic_lif *lif,
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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lif->txqcqs[i]->intr.index,
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lif->tx_coalesce_hw);
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if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
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lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
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} else {
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lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
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ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
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@ -2361,6 +2386,8 @@ int ionic_lif_alloc(struct ionic *ionic)
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lif->rx_coalesce_usecs);
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lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
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lif->tx_coalesce_hw = lif->rx_coalesce_hw;
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set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
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set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
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snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
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@ -4,6 +4,7 @@
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#ifndef _IONIC_LIF_H_
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#define _IONIC_LIF_H_
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#include <linux/dim.h>
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#include <linux/pci.h>
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#include "ionic_rx_filter.h"
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@ -66,6 +67,7 @@ struct ionic_qcq {
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void *sg_base;
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dma_addr_t sg_base_pa;
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u32 sg_size;
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struct dim dim;
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struct ionic_queue q;
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struct ionic_cq cq;
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struct ionic_intr_info intr;
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@ -131,6 +133,8 @@ enum ionic_lif_state_flags {
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IONIC_LIF_F_LINK_CHECK_REQUESTED,
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IONIC_LIF_F_FW_RESET,
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IONIC_LIF_F_SPLIT_INTR,
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IONIC_LIF_F_TX_DIM_INTR,
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IONIC_LIF_F_RX_DIM_INTR,
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/* leave this as last */
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IONIC_LIF_F_STATE_SIZE
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@ -288,7 +292,6 @@ static inline void debug_stats_napi_poll(struct ionic_qcq *qcq,
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#define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++)
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#define DEBUG_STATS_RX_BUFF_CNT(q) ((q)->lif->rxqstats[q->index].buffers_posted++)
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#define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++)
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#define DEBUG_STATS_TXQ_POST(q, dbell) debug_stats_txq_post(q, dbell)
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#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
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debug_stats_napi_poll(qcq, work_done)
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@ -432,6 +432,30 @@ void ionic_rx_empty(struct ionic_queue *q)
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}
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}
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static void ionic_dim_update(struct ionic_qcq *qcq)
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{
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struct dim_sample dim_sample;
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struct ionic_lif *lif;
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unsigned int qi;
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if (!qcq->intr.dim_coal_hw)
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return;
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lif = qcq->q.lif;
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qi = qcq->cq.bound_q->index;
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ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
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lif->rxqcqs[qi]->intr.index,
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qcq->intr.dim_coal_hw);
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dim_update_sample(qcq->cq.bound_intr->rearm_count,
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lif->txqstats[qi].pkts,
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lif->txqstats[qi].bytes,
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&dim_sample);
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net_dim(&qcq->dim, dim_sample);
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}
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int ionic_tx_napi(struct napi_struct *napi, int budget)
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{
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struct ionic_qcq *qcq = napi_to_qcq(napi);
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@ -448,8 +472,9 @@ int ionic_tx_napi(struct napi_struct *napi, int budget)
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ionic_tx_service, NULL, NULL);
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if (work_done < budget && napi_complete_done(napi, work_done)) {
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ionic_dim_update(qcq);
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flags |= IONIC_INTR_CRED_UNMASK;
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DEBUG_STATS_INTR_REARM(cq->bound_intr);
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cq->bound_intr->rearm_count++;
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}
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if (work_done || flags) {
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@ -483,8 +508,9 @@ int ionic_rx_napi(struct napi_struct *napi, int budget)
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ionic_rx_fill(cq->bound_q);
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if (work_done < budget && napi_complete_done(napi, work_done)) {
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ionic_dim_update(qcq);
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flags |= IONIC_INTR_CRED_UNMASK;
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DEBUG_STATS_INTR_REARM(cq->bound_intr);
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cq->bound_intr->rearm_count++;
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}
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if (work_done || flags) {
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@ -524,8 +550,9 @@ int ionic_txrx_napi(struct napi_struct *napi, int budget)
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ionic_rx_fill_cb(rxcq->bound_q);
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if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) {
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ionic_dim_update(qcq);
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flags |= IONIC_INTR_CRED_UNMASK;
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DEBUG_STATS_INTR_REARM(rxcq->bound_intr);
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rxcq->bound_intr->rearm_count++;
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}
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if (rx_work_done || flags) {
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