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drm/doc/rfc: i915 new parallel submission uAPI plan
Add entry for i915 new parallel submission uAPI plan. v2: (Daniel Vetter): - Expand logical order explaination - Add dummy header - Only allow N BBs in execbuf IOCTL - Configure parallel submission per slot not per gem context v3: (Marcin Ślusarz): - Lot's of typos / bad english fixed (Tvrtko Ursulin): - Consistent pseudo code, clean up wording in descriptions v4: (Daniel Vetter) - Drop flags - Add kernel doc - Reword a few things / fix typos (Tvrtko) - Reword a few things / fix typos v5: (Checkpatch) - Fix typos (Docs) - Fix warning Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Tony Ye <tony.ye@intel.com> CC: Carl Zhang <carl.zhang@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Tony Ye <tony.ye@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210629193511.124099-3-matthew.brost@intel.com
This commit is contained in:
Matthew Brost
Daniel Vetter
parent
f587623b78
commit
0454a490bd
122
Documentation/gpu/rfc/i915_parallel_execbuf.h
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122
Documentation/gpu/rfc/i915_parallel_execbuf.h
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
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/**
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* struct drm_i915_context_engines_parallel_submit - Configure engine for
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* parallel submission.
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*
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* Setup a slot in the context engine map to allow multiple BBs to be submitted
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* in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
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* in parallel. Multiple hardware contexts are created internally in the i915
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* run these BBs. Once a slot is configured for N BBs only N BBs can be
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* submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
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* doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
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* many BBs there are based on the slot's configuration. The N BBs are the last
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* N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
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*
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* The default placement behavior is to create implicit bonds between each
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* context if each context maps to more than 1 physical engine (e.g. context is
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* a virtual engine). Also we only allow contexts of same engine class and these
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* contexts must be in logically contiguous order. Examples of the placement
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* behavior described below. Lastly, the default is to not allow BBs to
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* preempted mid BB rather insert coordinated preemption on all hardware
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* contexts between each set of BBs. Flags may be added in the future to change
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* both of these default behaviors.
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*
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* Returns -EINVAL if hardware context placement configuration is invalid or if
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* the placement configuration isn't supported on the platform / submission
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* interface.
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* Returns -ENODEV if extension isn't supported on the platform / submission
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* interface.
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*
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* .. code-block:: none
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*
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* Example 1 pseudo code:
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* CS[X] = generic engine of same class, logical instance X
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
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* set_engines(INVALID)
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* set_parallel(engine_index=0, width=2, num_siblings=1,
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* engines=CS[0],CS[1])
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*
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* Results in the following valid placement:
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* CS[0], CS[1]
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*
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* Example 2 pseudo code:
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* CS[X] = generic engine of same class, logical instance X
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
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* set_engines(INVALID)
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* set_parallel(engine_index=0, width=2, num_siblings=2,
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* engines=CS[0],CS[2],CS[1],CS[3])
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*
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* Results in the following valid placements:
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* CS[0], CS[1]
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* CS[2], CS[3]
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*
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* This can also be thought of as 2 virtual engines described by 2-D array
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* in the engines the field with bonds placed between each index of the
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* virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to
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* CS[3].
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* VE[0] = CS[0], CS[2]
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* VE[1] = CS[1], CS[3]
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*
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* Example 3 pseudo code:
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* CS[X] = generic engine of same class, logical instance X
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
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* set_engines(INVALID)
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* set_parallel(engine_index=0, width=2, num_siblings=2,
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* engines=CS[0],CS[1],CS[1],CS[3])
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*
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* Results in the following valid and invalid placements:
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* CS[0], CS[1]
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* CS[1], CS[3] - Not logical contiguous, return -EINVAL
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*/
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struct drm_i915_context_engines_parallel_submit {
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/**
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* @base: base user extension.
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*/
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struct i915_user_extension base;
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/**
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* @engine_index: slot for parallel engine
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*/
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__u16 engine_index;
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/**
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* @width: number of contexts per parallel engine
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*/
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__u16 width;
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/**
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* @num_siblings: number of siblings per context
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*/
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__u16 num_siblings;
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/**
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* @mbz16: reserved for future use; must be zero
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*/
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__u16 mbz16;
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/**
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* @flags: all undefined flags must be zero, currently not defined flags
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*/
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__u64 flags;
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/**
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* @mbz64: reserved for future use; must be zero
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*/
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__u64 mbz64[3];
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/**
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* @engines: 2-d array of engine instances to configure parallel engine
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*
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* length = width (i) * num_siblings (j)
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* index = j + i * num_siblings
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*/
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struct i915_engine_class_instance engines[0];
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} __packed;
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@ -88,4 +88,61 @@ Spec references:
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New parallel submission uAPI
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============================
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Details to come in a following patch.
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The existing bonding uAPI is completely broken with GuC submission because
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whether a submission is a single context submit or parallel submit isn't known
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until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
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contexts in parallel with the GuC the context must be explicitly registered with
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N contexts and all N contexts must be submitted in a single command to the GuC.
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The GuC interfaces do not support dynamically changing between N contexts as the
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bonding uAPI does. Hence the need for a new parallel submission interface. Also
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the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore
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I915_SUBMIT_FENCE is by design a future fence, so not really something we should
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continue to support.
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The new parallel submission uAPI consists of 3 parts:
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* Export engines logical mapping
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* A 'set_parallel' extension to configure contexts for parallel
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submission
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* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
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Export engines logical mapping
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------------------------------
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Certain use cases require BBs to be placed on engine instances in logical order
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(e.g. split-frame on gen11+). The logical mapping of engine instances can change
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based on fusing. Rather than making UMDs be aware of fusing, simply expose the
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logical mapping with the existing query engine info IOCTL. Also the GuC
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submission interface currently only supports submitting multiple contexts to
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engines in logical order which is a new requirement compared to execlists.
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Lastly, all current platforms have at most 2 engine instances and the logical
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order is the same as uAPI order. This will change on platforms with more than 2
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engine instances.
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A single bit will be added to drm_i915_engine_info.flags indicating that the
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logical instance has been returned and a new field,
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drm_i915_engine_info.logical_instance, returns the logical instance.
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A 'set_parallel' extension to configure contexts for parallel submission
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------------------------------------------------------------------------
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The 'set_parallel' extension configures a slot for parallel submission of N BBs.
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It is a setup step that must be called before using any of the contexts. See
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I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
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similar existing examples. Once a slot is configured for parallel submission the
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execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only
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supports GuC submission. Execlists supports can be added later if needed.
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Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
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drm_i915_context_engines_parallel_submit to the uAPI to implement this
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extension.
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.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h
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:functions: drm_i915_context_engines_parallel_submit
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Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
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-------------------------------------------------------------------
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Contexts that have been configured with the 'set_parallel' extension can only
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submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects
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in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST is
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set. The number of BBs is implicit based on the slot submitted and how it has
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been configured by 'set_parallel' or other extensions. No uAPI changes are
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required to the execbuf2 IOCTL.
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