mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-24 11:34:50 +08:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Don't drag a platform specific header into generic arch code.
This commit is contained in:
commit
044f620ac6
@ -13,9 +13,9 @@
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#include <asm/system.h>
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#include <asm/hardirq.h>
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#include <asm/hazards.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheflush.h>
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#include <asm/time.h>
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@ -614,7 +614,7 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new,
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
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unsigned int vpe = current_cpu_data.vpe_id;
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vpemask[vpe][irq - MIPSCPU_INT_BASE] = 1;
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vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
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#endif
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irq_hwmask[irq] = hwmask;
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@ -822,7 +822,7 @@ void ipi_decode(struct smtc_ipi *pipi)
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switch (type_copy) {
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case SMTC_CLOCK_TICK:
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irq_enter();
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kstat_this_cpu.irqs[MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR]++;
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kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_perfcount_irq]++;
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/* Invoke Clock "Interrupt" */
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ipi_timer_latch[dest_copy] = 0;
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
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@ -199,11 +199,16 @@ int (*perf_irq)(void) = null_perf_irq;
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EXPORT_SYMBOL(null_perf_irq);
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EXPORT_SYMBOL(perf_irq);
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/*
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* Timer interrupt
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*/
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int cp0_compare_irq;
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/*
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* Performance counter IRQ or -1 if shared with timer
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*/
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int mipsxx_perfcount_irq;
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EXPORT_SYMBOL(mipsxx_perfcount_irq);
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int cp0_perfcount_irq;
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EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
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/*
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* Possibly handle a performance counter interrupt.
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@ -213,12 +218,12 @@ static inline int handle_perf_irq (int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (mipsxx_perfcount_irq < 0). If it is and a
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (mipsxx_perfcount_irq < 0) &&
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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@ -1350,9 +1350,6 @@ void __init per_cpu_trap_init(void)
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if (!secondaryTC) {
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#endif /* CONFIG_MIPS_MT_SMTC */
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/*
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* Interrupt handling.
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*/
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if (cpu_has_veic || cpu_has_vint) {
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write_c0_ebase (ebase);
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/* Setting vector spacing enables EI/VI mode */
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@ -1366,6 +1363,23 @@ void __init per_cpu_trap_init(void)
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} else
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set_c0_cause(CAUSEF_IV);
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}
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/*
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* Before R2 both interrupt numbers were fixed to 7, so on R2 only:
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*
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* o read IntCtl.IPTI to determine the timer interrupt
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* o read IntCtl.IPPCI to determine the performance counter interrupt
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*/
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if (cpu_has_mips_r2) {
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cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
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cp0_perfcount_irq = -1;
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} else {
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cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
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if (cp0_perfcount_irq != cp0_compare_irq)
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cp0_perfcount_irq = -1;
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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@ -189,7 +189,7 @@ asmlinkage void plat_irq_dispatch(void)
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if (irq == MIPSCPU_INT_ATLAS)
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atlas_hw0_irqdispatch();
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else if (irq >= 0)
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do_IRQ(MIPSCPU_INT_BASE + irq);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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else
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spurious_interrupt();
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}
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@ -261,11 +261,11 @@ void __init arch_init_irq(void)
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} else if (cpu_has_vint) {
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set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
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setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
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&atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
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#else /* Not SMTC */
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setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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} else
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setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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}
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@ -54,7 +54,7 @@
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unsigned long cpu_khz;
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static int mips_cpu_timer_irq;
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extern int mipsxx_perfcount_irq;
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extern int cp0_perfcount_irq;
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extern void smtc_timer_broadcast(int);
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static void mips_timer_dispatch(void)
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@ -64,7 +64,7 @@ static void mips_timer_dispatch(void)
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static void mips_perf_dispatch(void)
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{
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do_IRQ(mipsxx_perfcount_irq);
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do_IRQ(cp0_perfcount_irq);
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}
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/*
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@ -82,12 +82,12 @@ static inline int handle_perf_irq (int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (mipsxx_perfcount_irq < 0). If it is and a
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (mipsxx_perfcount_irq < 0) &&
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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@ -259,42 +259,31 @@ static struct irqaction perf_irqaction = {
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void __init plat_perf_setup(struct irqaction *irq)
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{
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int hwint = 0;
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mipsxx_perfcount_irq = -1;
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cp0_perfcount_irq = -1;
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
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mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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} else
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#endif
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if (cpu_has_mips_r2) {
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/*
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* Read IntCtl.IPPCI to determine the performance
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* counter interrupt
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*/
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hwint = (read_c0_intctl () >> 26) & 7;
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if (hwint != MIPSCPU_INT_CPUCTR) {
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if (cp0_perfcount_irq >= 0) {
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if (cpu_has_vint)
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set_vi_handler (hwint, mips_perf_dispatch);
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mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint;
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}
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}
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if (mipsxx_perfcount_irq >= 0) {
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set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint);
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setup_irq_smtc(cp0_perfcount_irq, irq,
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0x100 << cp0_perfcount_irq);
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#else
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setup_irq(mipsxx_perfcount_irq, irq);
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setup_irq(cp0_perfcount_irq, irq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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#ifdef CONFIG_SMP
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set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq);
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set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
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#endif
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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int hwint = 0;
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
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@ -303,22 +292,15 @@ void __init plat_timer_setup(struct irqaction *irq)
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else
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#endif
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{
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if (cpu_has_mips_r2)
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/*
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* Read IntCtl.IPTI to determine the timer interrupt
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*/
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hwint = (read_c0_intctl () >> 29) & 7;
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else
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hwint = MIPSCPU_INT_CPUCTR;
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if (cpu_has_vint)
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set_vi_handler (hwint, mips_timer_dispatch);
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mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint;
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set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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/* we are using the cpu counter for timer interrupts */
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irq->handler = mips_timer_interrupt; /* we use our own handler */
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint);
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setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
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#else
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setup_irq(mips_cpu_timer_irq, irq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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@ -257,7 +257,7 @@ asmlinkage void plat_irq_dispatch(void)
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if (irq == MIPSCPU_INT_I8259A)
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malta_hw0_irqdispatch();
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else if (irq > 0)
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do_IRQ(MIPSCPU_INT_BASE + irq);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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else
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spurious_interrupt();
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}
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@ -326,17 +326,17 @@ void __init arch_init_irq(void)
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set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
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set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
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setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
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(0x100 << MIPSCPU_INT_I8259A));
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setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
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setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
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&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
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#else /* Not SMTC */
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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else {
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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}
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}
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@ -106,7 +106,7 @@ asmlinkage void plat_irq_dispatch(void)
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irq = irq_ffs(pending);
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if (irq >= 0)
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do_IRQ(MIPSCPU_INT_BASE + irq);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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else
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spurious_interrupt();
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}
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|
@ -68,7 +68,7 @@ static void __init serial_init(void)
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#else
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s.iobase = SEAD_UART0_REGS_BASE+3;
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#endif
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s.irq = MIPSCPU_INT_BASE + MIPSCPU_INT_UART0;
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s.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_UART0;
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s.uartclk = SEAD_BASE_BAUD * 16;
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s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
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s.iotype = UPIO_PORT;
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|
@ -77,7 +77,7 @@ asmlinkage void plat_irq_dispatch(void)
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irq = irq_ffs(pending);
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if (irq > 0)
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do_IRQ(MIPSCPU_INT_BASE + irq);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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else
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spurious_interrupt();
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}
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|
@ -71,8 +71,8 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
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int vpflags = dvpe();
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write_c0_compare (read_c0_count() - 1);
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clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR);
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set_c0_status(0x100 << MIPSCPU_INT_CPUCTR);
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clear_c0_cause(0x100 << cp0_compare_irq);
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set_c0_status(0x100 << cp0_compare_irq);
|
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irq_enable_hazard();
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evpe(vpflags);
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|
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@ -183,8 +183,8 @@ void __init plat_timer_setup(struct irqaction *irq)
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}
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else {
|
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if (cpu_has_vint)
|
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set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
|
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mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
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set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
|
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
|
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/* we are using the cpu counter for timer interrupts */
|
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|
@ -240,7 +240,7 @@ static int __init mipsnet_probe(struct device *dev)
|
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* TODO: probe for these or load them from PARAM
|
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*/
|
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netdev->base_addr = 0x4200;
|
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netdev->irq = MIPSCPU_INT_BASE + MIPSCPU_INT_MB0 +
|
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netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
|
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inl(mipsnet_reg_address(netdev, interruptInfo));
|
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|
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// Get the io region now, get irq on open()
|
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|
@ -72,4 +72,13 @@ extern int allocate_irqno(void);
|
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extern void alloc_legacy_irqno(void);
|
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extern void free_irqno(unsigned int irq);
|
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|
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/*
|
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* Before R2 the timer and performance counter interrupts were both fixed to
|
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* IE7. Since R2 their number has to be read from the c0_intctl register.
|
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*/
|
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#define CP0_LEGACY_COMPARE_IRQ 7
|
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|
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extern int cp0_compare_irq;
|
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extern int cp0_perfcount_irq;
|
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|
||||
#endif /* _ASM_IRQ_H */
|
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|
@ -28,11 +28,6 @@
|
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|
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#include <irq.h>
|
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|
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/*
|
||||
* Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
|
||||
*/
|
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#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
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|
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/* CPU interrupt offsets */
|
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#define MIPSCPU_INT_SW0 0
|
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#define MIPSCPU_INT_SW1 1
|
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@ -42,7 +37,6 @@
|
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#define MIPSCPU_INT_MB2 4
|
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#define MIPSCPU_INT_MB3 5
|
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#define MIPSCPU_INT_MB4 6
|
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#define MIPSCPU_INT_CPUCTR 7
|
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|
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/*
|
||||
* Interrupts 8..39 are used for Atlas interrupt controller interrupts
|
||||
|
@ -32,11 +32,6 @@
|
||||
*/
|
||||
#define MALTA_INT_BASE 0
|
||||
|
||||
/*
|
||||
* Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
|
||||
*/
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
|
||||
/* CPU interrupt offsets */
|
||||
#define MIPSCPU_INT_SW0 0
|
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#define MIPSCPU_INT_SW1 1
|
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@ -49,7 +44,6 @@
|
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#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
|
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#define MIPSCPU_INT_MB4 6
|
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#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
|
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#define MIPSCPU_INT_CPUCTR 7
|
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|
||||
/*
|
||||
* Interrupts 64..127 are used for Soc-it Classic interrupts
|
||||
|
@ -22,14 +22,7 @@
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* Interrupts 0..7 are used for SEAD CPU interrupts
|
||||
*/
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
|
||||
#define MIPSCPU_INT_UART0 2
|
||||
#define MIPSCPU_INT_UART1 3
|
||||
|
||||
#define MIPSCPU_INT_CPUCTR 7
|
||||
|
||||
#endif /* !(_MIPS_SEADINT_H) */
|
||||
|
@ -21,15 +21,11 @@
|
||||
|
||||
#define SIM_INT_BASE 0
|
||||
#define MIPSCPU_INT_MB0 2
|
||||
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
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|
||||
|
||||
#define MIPSCPU_INT_CPUCTR 7
|
||||
|
||||
#define MSC01E_INT_BASE 64
|
||||
|
||||
#define MIPSCPU_INT_CPUCTR 7
|
||||
#define MSC01E_INT_CPUCTR 11
|
||||
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user