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net: dsa: felix: use DEFINE_RES_MEM_NAMED for resources

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Use less verbose resource definitions in vsc9959 and vsc9953. This also
sets IORESOURCE_MEM in the constant array of resources, so we don't have
to do this from felix_init_structs() - in fact, in the future, we may
even support IORESOURCE_REG resources.

Note that this macro takes start and length as argument, and we had
start and end before. So transform end into length.

While at it, sort the resources according to their offset.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Vladimir Oltean 2022-09-27 22:15:19 +03:00 committed by Jakub Kicinski
parent 8f66c64bfc
commit 044d447a80
3 changed files with 38 additions and 188 deletions
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2
drivers/net/dsa/ocelot/felix.c
View File

@ -1356,7 +1356,6 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports)
continue; continue;
memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); memcpy(&res, &felix->info->target_io_res[i], sizeof(res));
res.flags = IORESOURCE_MEM;
res.start += felix->switch_base; res.start += felix->switch_base;
res.end += felix->switch_base; res.end += felix->switch_base;
@ -1393,7 +1392,6 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports)
} }
memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); memcpy(&res, &felix->info->port_io_res[port], sizeof(res));
res.flags = IORESOURCE_MEM;
res.start += felix->switch_base; res.start += felix->switch_base;
res.end += felix->switch_base; res.end += felix->switch_base;

104
drivers/net/dsa/ocelot/felix_vsc9959.c
View File

@ -478,99 +478,32 @@ static const u32 *vsc9959_regmap[TARGET_MAX] = {
/* Addresses are relative to the PCI device's base address */ /* Addresses are relative to the PCI device's base address */
static const struct resource vsc9959_target_io_res[TARGET_MAX] = { static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
[ANA] = { [SYS] = DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"),
.start = 0x0280000, [REW] = DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"),
.end = 0x028ffff, [S0] = DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"),
.name = "ana", [S1] = DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"),
}, [S2] = DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"),
[QS] = { [GCB] = DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"),
.start = 0x0080000, [QS] = DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"),
.end = 0x00800ff, [PTP] = DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"),
.name = "qs", [QSYS] = DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
}, [ANA] = DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"),
[QSYS] = {
.start = 0x0200000,
.end = 0x021ffff,
.name = "qsys",
},
[REW] = {
.start = 0x0030000,
.end = 0x003ffff,
.name = "rew",
},
[SYS] = {
.start = 0x0010000,
.end = 0x001ffff,
.name = "sys",
},
[S0] = {
.start = 0x0040000,
.end = 0x00403ff,
.name = "s0",
},
[S1] = {
.start = 0x0050000,
.end = 0x00503ff,
.name = "s1",
},
[S2] = {
.start = 0x0060000,
.end = 0x00603ff,
.name = "s2",
},
[PTP] = {
.start = 0x0090000,
.end = 0x00900cb,
.name = "ptp",
},
[GCB] = {
.start = 0x0070000,
.end = 0x00701ff,
.name = "devcpu_gcb",
},
}; };
static const struct resource vsc9959_port_io_res[] = { static const struct resource vsc9959_port_io_res[] = {
{ DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"),
.start = 0x0100000, DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"),
.end = 0x010ffff, DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"),
.name = "port0", DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"),
}, DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"),
{ DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"),
.start = 0x0110000,
.end = 0x011ffff,
.name = "port1",
},
{
.start = 0x0120000,
.end = 0x012ffff,
.name = "port2",
},
{
.start = 0x0130000,
.end = 0x013ffff,
.name = "port3",
},
{
.start = 0x0140000,
.end = 0x014ffff,
.name = "port4",
},
{
.start = 0x0150000,
.end = 0x015ffff,
.name = "port5",
},
}; };
/* Port MAC 0 Internal MDIO bus through which the SerDes acting as an /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
* SGMII/QSGMII MAC PCS can be found. * SGMII/QSGMII MAC PCS can be found.
*/ */
static const struct resource vsc9959_imdio_res = { static const struct resource vsc9959_imdio_res =
.start = 0x8030, DEFINE_RES_MEM_NAMED(0x8030, 0x8040, "imdio");
.end = 0x8040,
.name = "imdio",
};
static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
@ -1026,7 +959,6 @@ static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
memcpy(&res, &vsc9959_imdio_res, sizeof(res)); memcpy(&res, &vsc9959_imdio_res, sizeof(res));
res.flags = IORESOURCE_MEM;
res.start += imdio_base; res.start += imdio_base;
res.end += imdio_base; res.end += imdio_base;

120
drivers/net/dsa/ocelot/seville_vsc9953.c
View File

@ -459,109 +459,29 @@ static const u32 *vsc9953_regmap[TARGET_MAX] = {
/* Addresses are relative to the device's base address */ /* Addresses are relative to the device's base address */
static const struct resource vsc9953_target_io_res[TARGET_MAX] = { static const struct resource vsc9953_target_io_res[TARGET_MAX] = {
[ANA] = { [SYS] = DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"),
.start = 0x0280000, [REW] = DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"),
.end = 0x028ffff, [S0] = DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"),
.name = "ana", [S1] = DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"),
}, [S2] = DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"),
[QS] = { [GCB] = DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"),
.start = 0x0080000, [QS] = DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"),
.end = 0x00800ff, [PTP] = DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"),
.name = "qs", [QSYS] = DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
}, [ANA] = DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"),
[QSYS] = {
.start = 0x0200000,
.end = 0x021ffff,
.name = "qsys",
},
[REW] = {
.start = 0x0030000,
.end = 0x003ffff,
.name = "rew",
},
[SYS] = {
.start = 0x0010000,
.end = 0x001ffff,
.name = "sys",
},
[S0] = {
.start = 0x0040000,
.end = 0x00403ff,
.name = "s0",
},
[S1] = {
.start = 0x0050000,
.end = 0x00503ff,
.name = "s1",
},
[S2] = {
.start = 0x0060000,
.end = 0x00603ff,
.name = "s2",
},
[PTP] = {
.start = 0x0090000,
.end = 0x00900cb,
.name = "ptp",
},
[GCB] = {
.start = 0x0070000,
.end = 0x00701ff,
.name = "devcpu_gcb",
},
}; };
static const struct resource vsc9953_port_io_res[] = { static const struct resource vsc9953_port_io_res[] = {
{ DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"),
.start = 0x0100000, DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"),
.end = 0x010ffff, DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"),
.name = "port0", DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"),
}, DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"),
{ DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"),
.start = 0x0110000, DEFINE_RES_MEM_NAMED(0x0160000, 0x0010000, "port6"),
.end = 0x011ffff, DEFINE_RES_MEM_NAMED(0x0170000, 0x0010000, "port7"),
.name = "port1", DEFINE_RES_MEM_NAMED(0x0180000, 0x0010000, "port8"),
}, DEFINE_RES_MEM_NAMED(0x0190000, 0x0010000, "port9"),
{
.start = 0x0120000,
.end = 0x012ffff,
.name = "port2",
},
{
.start = 0x0130000,
.end = 0x013ffff,
.name = "port3",
},
{
.start = 0x0140000,
.end = 0x014ffff,
.name = "port4",
},
{
.start = 0x0150000,
.end = 0x015ffff,
.name = "port5",
},
{
.start = 0x0160000,
.end = 0x016ffff,
.name = "port6",
},
{
.start = 0x0170000,
.end = 0x017ffff,
.name = "port7",
},
{
.start = 0x0180000,
.end = 0x018ffff,
.name = "port8",
},
{
.start = 0x0190000,
.end = 0x019ffff,
.name = "port9",
},
}; };
static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = { static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {