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More OMAP hwmod and clock fixes for v3.10-rc. Fixes the AM33xx UART2.
Also fixes some CCF-related breakage on OMAP36xx/37xx, affecting DSS at the very least. Basic test logs for this branch are here: http://www.pwsan.com/omap/testlogs/fixes_b_v3.10-rc/20130606093449/ -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRsMp7AAoJEMePsQ0LvSpL9bsP/0gRY5Vb9qXQPEiUz+UqtwBr TjugjMmCOlvU8MkHKVI3Cp5qxfvBIsDT7x74AjA6q5E7In3+1njIxLwoa81osgTU s97LkjbBo4RuB6G9EWTQCedYLgyyIzqTQA3JCUx46K6E0ERonjf+viPZl3GvYb+Z cl9oZYya0DC+5QBJzZlodMu/5JHGpFrqgs505KFovVcxnWCRcZGx3hMH9Be6pSsD je24xjpjMWfhTToQMpbW58ZDWSTh5GLnu87blff8C8ojWlwmF+iwfECSZQfrPHCA 9g1aSsA37DWUB1krOZ1nUUdQ7eP6fjR4lWpz1mNOT5cBlncDqT/2M4lumkjCIsie +Nv24xGQwpJRzAyYzJGJqedB1j7i8/HbCVzCkAqJnNCiimW7LKUwDqzHBYiZAhcI Gs2/xUDBhLNfjSbGeCj+nnRMP5VpiT2ZEWtk1W+Icld/tG3//7TF3OYm1gzG57Xg Dza6uAeO9ZxTZtGkYQtnzwT9Wm19i87ExD9nORclr5vT//uqKWHye9JaddXFL86Z oePaTikhZK2HJIUP2JgDYGDB7PBAE9gMJ16JeKd6OfGn8ISJD6TPsuJ8wM98FKXQ CRblPO6i0NTOe1Gsfy2Z+9gLZi2HxDLLNcVTnx+V/VXg1Srpjg2ZQ8yLDfOPHFYm /IuIiZTq97dmTicqm5dj =HWUH -----END PGP SIGNATURE----- Merge tag 'omap-fixes-b-for-3.10-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.10/fixes More OMAP hwmod and clock fixes for v3.10-rc. Fixes the AM33xx UART2. Also fixes some CCF-related breakage on OMAP36xx/37xx, affecting DSS at the very least. Basic test logs for this branch are here: http://www.pwsan.com/omap/testlogs/fixes_b_v3.10-rc/20130606093449/
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commit
03c0d27119
@ -20,11 +20,12 @@
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock36xx.h"
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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/**
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* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
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@ -39,29 +40,28 @@
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*/
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int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
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{
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struct clk_hw_omap *parent;
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struct clk_divider *parent;
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struct clk_hw *parent_hw;
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u32 dummy_v, orig_v, clksel_shift;
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u32 dummy_v, orig_v;
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
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parent = to_clk_hw_omap(parent_hw);
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parent = to_clk_divider(parent_hw);
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/* Restore the dividers */
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if (!ret) {
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clksel_shift = __ffs(parent->clksel_mask);
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orig_v = __raw_readl(parent->clksel_reg);
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orig_v = __raw_readl(parent->reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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dummy_v ^= (1 << clksel_shift);
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__raw_writel(dummy_v, parent->clksel_reg);
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dummy_v ^= (1 << parent->shift);
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__raw_writel(dummy_v, parent->reg);
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/* Write the original divider */
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__raw_writel(orig_v, parent->clksel_reg);
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__raw_writel(orig_v, parent->reg);
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}
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return ret;
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@ -2007,6 +2007,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
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},
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};
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/* uart2 */
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static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
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{ .name = "tx", .dma_req = 28, },
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{ .name = "rx", .dma_req = 29, },
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{ .dma_req = -1 }
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};
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static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
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{ .irq = 73 + OMAP_INTC_START, },
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{ .irq = -1 },
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@ -2018,7 +2025,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
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.clkdm_name = "l4ls_clkdm",
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.flags = HWMOD_SWSUP_SIDLE_ACT,
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.mpu_irqs = am33xx_uart2_irqs,
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.sdma_reqs = uart1_edma_reqs,
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.sdma_reqs = uart2_edma_reqs,
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.main_clk = "dpll_per_m2_div4_ck",
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.prcm = {
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.omap4 = {
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