Renesas ARM Based SoC Updates for v5.3

* Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M
 * Don't init CNTVOFF/counter if PSCI is available
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAl0MksAACgkQ189kaWo3
 T75qLhAAq4ezsma/ajA++m+K1zF16t4TMKt8iSLGQXANZ0rDd7zkaXZ7H0ztfrh1
 WqTVUklYAR55qHWvxH+wyhT312cBg1Tx2+Jvx9IgA5nRVVylOzKAHhEj1TIfAsIZ
 tE6xR/oNEXGH4f97KFl6IypVPfBoG6tRK1pj59Ns0oXf4HSwRIk8tfaUQfIbfihY
 Z7TQ0AljthbNLpWxHyDj6VWWBSAGtRcjgV5SezgN141C1BTeRX0rovJ0gIGWFZCt
 NxL+kaBSAQ2h6GVy/4KPP6h/gS5IuojdJ2npuRxG0IQGieAPsm0MbxD2YmXWzCLX
 rz3PmCgoKd9fvRYZw4YhG7FIc3wFACpcXfbImoArMelt9Th/9xPwUAoidTCg/meS
 ON/lVJckA5KquE89yjSJIJHrqLcXT6AKkMWPK2KqT0KP7l+MSX6hJEg6PAkEPtaQ
 DdrnmDcl3dMKwbEp0f7OL2dKXQvcusRZCY/eILr11RWsd/oThZ4y1magxypHUhxb
 iVVMRkNgaKFlMpRTCTMSAvchUOm3fiIKK75MBr0CPfFb1x7S0le2COa/5yNsnuJd
 rj8gTwhXlAU/BSVHzEjUnoH0JKCs1p9VYu8KiAfpgrBQOxaEhpO0tiO/EuUSTKvv
 xwqZGgJF93cPNKKLDzKrLp2pClL77jwxUk2sfPdr/x92Gfe1ycI=
 =dMJy
 -----END PGP SIGNATURE-----

Merge tag 'renesas-arm-soc-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/soc

Renesas ARM Based SoC Updates for v5.3

* Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M
* Don't init CNTVOFF/counter if PSCI is available

* tag 'renesas-arm-soc-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M
  ARM: mach-shmobile: Don't init CNTVOFF/counter if PSCI is available

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-06-25 05:47:24 -07:00
commit 03890f477c
2 changed files with 20 additions and 1 deletions

View File

@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/psci.h>
#include <asm/mach/arch.h>
#include <asm/secure_cntvoff.h>
#include "common.h"
@ -60,9 +61,24 @@ static unsigned int __init get_extal_freq(void)
void __init rcar_gen2_timer_init(void)
{
bool need_update = true;
void __iomem *base;
u32 freq;
/*
* If PSCI is available then most likely we are running on PSCI-enabled
* U-Boot which, we assume, has already taken care of resetting CNTVOFF
* and updating counter module before switching to non-secure mode
* and we don't need to.
*/
#ifdef CONFIG_ARM_PSCI_FW
if (psci_ops.cpu_on)
need_update = false;
#endif
if (need_update == false)
goto skip_update;
secure_cntvoff_init();
if (of_machine_is_compatible("renesas,r8a7745") ||
@ -102,6 +118,7 @@ void __init rcar_gen2_timer_init(void)
iounmap(base);
skip_update:
of_clk_init(NULL);
timer_probe();
}

View File

@ -57,14 +57,16 @@ config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_MTU2
select RENESAS_OSTM
select RENESAS_RZA1_IRQC
select SYS_SUPPORTS_SH_MTU2
config ARCH_R7S9210
bool "RZ/A2 (R7S9210)"
select PM
select PM_GENERIC_DOMAINS
select RENESAS_OSTM
select RENESAS_RZA1_IRQC
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"