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Renesas ARM Based SoC Updates for v5.3
* Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M * Don't init CNTVOFF/counter if PSCI is available -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAl0MksAACgkQ189kaWo3 T75qLhAAq4ezsma/ajA++m+K1zF16t4TMKt8iSLGQXANZ0rDd7zkaXZ7H0ztfrh1 WqTVUklYAR55qHWvxH+wyhT312cBg1Tx2+Jvx9IgA5nRVVylOzKAHhEj1TIfAsIZ tE6xR/oNEXGH4f97KFl6IypVPfBoG6tRK1pj59Ns0oXf4HSwRIk8tfaUQfIbfihY Z7TQ0AljthbNLpWxHyDj6VWWBSAGtRcjgV5SezgN141C1BTeRX0rovJ0gIGWFZCt NxL+kaBSAQ2h6GVy/4KPP6h/gS5IuojdJ2npuRxG0IQGieAPsm0MbxD2YmXWzCLX rz3PmCgoKd9fvRYZw4YhG7FIc3wFACpcXfbImoArMelt9Th/9xPwUAoidTCg/meS ON/lVJckA5KquE89yjSJIJHrqLcXT6AKkMWPK2KqT0KP7l+MSX6hJEg6PAkEPtaQ DdrnmDcl3dMKwbEp0f7OL2dKXQvcusRZCY/eILr11RWsd/oThZ4y1magxypHUhxb iVVMRkNgaKFlMpRTCTMSAvchUOm3fiIKK75MBr0CPfFb1x7S0le2COa/5yNsnuJd rj8gTwhXlAU/BSVHzEjUnoH0JKCs1p9VYu8KiAfpgrBQOxaEhpO0tiO/EuUSTKvv xwqZGgJF93cPNKKLDzKrLp2pClL77jwxUk2sfPdr/x92Gfe1ycI= =dMJy -----END PGP SIGNATURE----- Merge tag 'renesas-arm-soc-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/soc Renesas ARM Based SoC Updates for v5.3 * Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M * Don't init CNTVOFF/counter if PSCI is available * tag 'renesas-arm-soc-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M ARM: mach-shmobile: Don't init CNTVOFF/counter if PSCI is available Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
03890f477c
@ -17,6 +17,7 @@
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/psci.h>
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#include <asm/mach/arch.h>
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#include <asm/secure_cntvoff.h>
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#include "common.h"
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@ -60,9 +61,24 @@ static unsigned int __init get_extal_freq(void)
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void __init rcar_gen2_timer_init(void)
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{
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bool need_update = true;
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void __iomem *base;
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u32 freq;
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/*
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* If PSCI is available then most likely we are running on PSCI-enabled
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* U-Boot which, we assume, has already taken care of resetting CNTVOFF
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* and updating counter module before switching to non-secure mode
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* and we don't need to.
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*/
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#ifdef CONFIG_ARM_PSCI_FW
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if (psci_ops.cpu_on)
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need_update = false;
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#endif
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if (need_update == false)
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goto skip_update;
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secure_cntvoff_init();
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if (of_machine_is_compatible("renesas,r8a7745") ||
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@ -102,6 +118,7 @@ void __init rcar_gen2_timer_init(void)
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iounmap(base);
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skip_update:
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of_clk_init(NULL);
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timer_probe();
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}
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@ -57,14 +57,16 @@ config ARCH_R7S72100
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bool "RZ/A1H (R7S72100)"
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select PM
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select PM_GENERIC_DOMAINS
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select SYS_SUPPORTS_SH_MTU2
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select RENESAS_OSTM
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select RENESAS_RZA1_IRQC
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select SYS_SUPPORTS_SH_MTU2
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config ARCH_R7S9210
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bool "RZ/A2 (R7S9210)"
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_OSTM
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select RENESAS_RZA1_IRQC
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config ARCH_R8A73A4
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bool "R-Mobile APE6 (R8A73A40)"
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