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Merge branch 'pci/irq'
- Convert irq_find_mapping() + generic_handle_irq() to generic_handle_domain_irq() (Marc Zyngier) * pci/irq: PCI: Bulk conversion to generic_handle_domain_irq()
This commit is contained in:
commit
03816e7f78
@ -204,7 +204,7 @@ static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
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{
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned long val;
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unsigned long val;
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int pos, irq;
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int pos;
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val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
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val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
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(index * MSI_REG_CTRL_BLOCK_SIZE));
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(index * MSI_REG_CTRL_BLOCK_SIZE));
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@ -213,9 +213,8 @@ static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 0);
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 0);
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while (pos != MAX_MSI_IRQS_PER_CTRL) {
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while (pos != MAX_MSI_IRQS_PER_CTRL) {
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irq = irq_find_mapping(pp->irq_domain,
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generic_handle_domain_irq(pp->irq_domain,
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(index * MAX_MSI_IRQS_PER_CTRL) + pos);
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(index * MAX_MSI_IRQS_PER_CTRL) + pos);
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generic_handle_irq(irq);
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pos++;
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pos++;
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
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}
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}
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@ -257,7 +256,7 @@ static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
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struct dw_pcie *pci;
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struct dw_pcie *pci;
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struct pcie_port *pp;
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struct pcie_port *pp;
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unsigned long reg;
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unsigned long reg;
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u32 virq, bit;
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u32 bit;
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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@ -276,11 +275,8 @@ static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
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case INTB:
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case INTB:
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case INTC:
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case INTC:
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case INTD:
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case INTD:
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for_each_set_bit(bit, ®, PCI_NUM_INTX) {
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for_each_set_bit(bit, ®, PCI_NUM_INTX)
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virq = irq_find_mapping(dra7xx->irq_domain, bit);
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generic_handle_domain_irq(dra7xx->irq_domain, bit);
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if (virq)
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generic_handle_irq(virq);
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}
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break;
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break;
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}
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}
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@ -259,14 +259,12 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
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struct dw_pcie *pci = ks_pcie->pci;
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struct dw_pcie *pci = ks_pcie->pci;
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struct device *dev = pci->dev;
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struct device *dev = pci->dev;
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u32 pending;
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u32 pending;
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int virq;
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pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset));
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pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset));
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if (BIT(0) & pending) {
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if (BIT(0) & pending) {
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virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
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dev_dbg(dev, ": irq: irq_offset %d", offset);
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dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
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generic_handle_domain_irq(ks_pcie->legacy_irq_domain, offset);
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generic_handle_irq(virq);
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}
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}
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/* EOI the INTx interrupt */
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/* EOI the INTx interrupt */
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@ -579,7 +577,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
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struct pcie_port *pp = &pci->pp;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = pci->dev;
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struct device *dev = pci->dev;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 vector, virq, reg, pos;
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u32 vector, reg, pos;
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dev_dbg(dev, "%s, irq %d\n", __func__, irq);
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dev_dbg(dev, "%s, irq %d\n", __func__, irq);
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@ -600,10 +598,8 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
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continue;
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continue;
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vector = offset + (pos << 3);
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vector = offset + (pos << 3);
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virq = irq_linear_revmap(pp->irq_domain, vector);
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dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector);
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dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector,
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generic_handle_domain_irq(pp->irq_domain, vector);
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virq);
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generic_handle_irq(virq);
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}
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}
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chained_irq_exit(chip, desc);
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chained_irq_exit(chip, desc);
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@ -55,7 +55,7 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
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/* MSI int handler */
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/* MSI int handler */
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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{
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int i, pos, irq;
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int i, pos;
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unsigned long val;
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unsigned long val;
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u32 status, num_ctrls;
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u32 status, num_ctrls;
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irqreturn_t ret = IRQ_NONE;
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irqreturn_t ret = IRQ_NONE;
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@ -74,10 +74,9 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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pos = 0;
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pos = 0;
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while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
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while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
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pos)) != MAX_MSI_IRQS_PER_CTRL) {
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pos)) != MAX_MSI_IRQS_PER_CTRL) {
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irq = irq_find_mapping(pp->irq_domain,
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generic_handle_domain_irq(pp->irq_domain,
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(i * MAX_MSI_IRQS_PER_CTRL) +
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(i * MAX_MSI_IRQS_PER_CTRL) +
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pos);
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pos);
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generic_handle_irq(irq);
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pos++;
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pos++;
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}
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}
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}
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}
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@ -235,7 +235,7 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long reg;
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unsigned long reg;
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u32 val, bit, virq;
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u32 val, bit;
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/* INT for debug */
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/* INT for debug */
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val = readl(priv->base + PCL_RCV_INT);
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val = readl(priv->base + PCL_RCV_INT);
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@ -257,10 +257,8 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)
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val = readl(priv->base + PCL_RCV_INTX);
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val = readl(priv->base + PCL_RCV_INTX);
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reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
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reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
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for_each_set_bit(bit, ®, PCI_NUM_INTX) {
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for_each_set_bit(bit, ®, PCI_NUM_INTX)
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virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
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generic_handle_domain_irq(priv->legacy_irq_domain, bit);
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generic_handle_irq(virq);
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}
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chained_irq_exit(chip, desc);
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chained_irq_exit(chip, desc);
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}
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}
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@ -92,7 +92,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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u32 msi_data, msi_addr_lo, msi_addr_hi;
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u32 msi_data, msi_addr_lo, msi_addr_hi;
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u32 intr_status, msi_status;
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u32 intr_status, msi_status;
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unsigned long shifted_status;
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unsigned long shifted_status;
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u32 bit, virq, val, mask;
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u32 bit, val, mask;
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/*
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/*
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* The core provides a single interrupt for both INTx/MSI messages.
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* The core provides a single interrupt for both INTx/MSI messages.
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@ -114,11 +114,10 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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shifted_status >>= PAB_INTX_START;
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shifted_status >>= PAB_INTX_START;
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do {
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do {
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for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
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for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
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virq = irq_find_mapping(rp->intx_domain,
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int ret;
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bit + 1);
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ret = generic_handle_domain_irq(rp->intx_domain,
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if (virq)
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bit + 1);
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generic_handle_irq(virq);
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if (ret)
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else
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dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
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dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
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bit);
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bit);
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@ -155,9 +154,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
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msi_data, msi_addr_hi, msi_addr_lo);
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msi_data, msi_addr_hi, msi_addr_lo);
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virq = irq_find_mapping(msi->dev_domain, msi_data);
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generic_handle_domain_irq(msi->dev_domain, msi_data);
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if (virq)
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generic_handle_irq(virq);
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msi_status = readl_relaxed(pcie->apb_csr_base +
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msi_status = readl_relaxed(pcie->apb_csr_base +
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MSI_STATUS_OFFSET);
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MSI_STATUS_OFFSET);
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@ -1049,7 +1049,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
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{
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{
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u32 isr0_val, isr0_mask, isr0_status;
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u32 isr0_val, isr0_mask, isr0_status;
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u32 isr1_val, isr1_mask, isr1_status;
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u32 isr1_val, isr1_mask, isr1_status;
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int i, virq;
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int i;
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isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
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isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
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isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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@ -1077,8 +1077,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
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advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
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advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
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PCIE_ISR1_REG);
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PCIE_ISR1_REG);
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virq = irq_find_mapping(pcie->irq_domain, i);
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generic_handle_domain_irq(pcie->irq_domain, i);
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generic_handle_irq(virq);
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}
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}
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}
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}
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@ -314,7 +314,7 @@ static void faraday_pci_irq_handler(struct irq_desc *desc)
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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if ((irq_stat & BIT(i)) == 0)
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if ((irq_stat & BIT(i)) == 0)
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continue;
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continue;
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generic_handle_irq(irq_find_mapping(p->irqdomain, i));
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generic_handle_domain_irq(p->irqdomain, i);
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}
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}
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chained_irq_exit(irqchip, desc);
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chained_irq_exit(irqchip, desc);
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@ -1553,12 +1553,10 @@ static void tegra_pcie_msi_irq(struct irq_desc *desc)
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while (reg) {
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while (reg) {
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unsigned int offset = find_first_bit(®, 32);
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unsigned int offset = find_first_bit(®, 32);
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unsigned int index = i * 32 + offset;
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unsigned int index = i * 32 + offset;
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unsigned int irq;
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int ret;
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irq = irq_find_mapping(msi->domain->parent, index);
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ret = generic_handle_domain_irq(msi->domain->parent, index);
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if (irq) {
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if (ret) {
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generic_handle_irq(irq);
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} else {
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/*
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/*
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* that's weird who triggered this?
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* that's weird who triggered this?
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* just clear it
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* just clear it
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@ -291,8 +291,7 @@ static void xgene_msi_isr(struct irq_desc *desc)
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct xgene_msi_group *msi_groups;
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struct xgene_msi_group *msi_groups;
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struct xgene_msi *xgene_msi;
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struct xgene_msi *xgene_msi;
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unsigned int virq;
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int msir_index, msir_val, hw_irq, ret;
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int msir_index, msir_val, hw_irq;
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u32 intr_index, grp_select, msi_grp;
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u32 intr_index, grp_select, msi_grp;
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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@ -330,10 +329,8 @@ static void xgene_msi_isr(struct irq_desc *desc)
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* CPU0
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* CPU0
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*/
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*/
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hw_irq = hwirq_to_canonical_hwirq(hw_irq);
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hw_irq = hwirq_to_canonical_hwirq(hw_irq);
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virq = irq_find_mapping(xgene_msi->inner_domain, hw_irq);
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ret = generic_handle_domain_irq(xgene_msi->inner_domain, hw_irq);
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WARN_ON(!virq);
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WARN_ON_ONCE(ret);
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if (virq != 0)
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generic_handle_irq(virq);
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msir_val &= ~(1 << intr_index);
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msir_val &= ~(1 << intr_index);
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}
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}
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grp_select &= ~(1 << msir_index);
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grp_select &= ~(1 << msir_index);
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@ -55,7 +55,7 @@ static void altera_msi_isr(struct irq_desc *desc)
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struct altera_msi *msi;
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struct altera_msi *msi;
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unsigned long status;
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unsigned long status;
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u32 bit;
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u32 bit;
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u32 virq;
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int ret;
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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msi = irq_desc_get_handler_data(desc);
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msi = irq_desc_get_handler_data(desc);
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@ -65,11 +65,9 @@ static void altera_msi_isr(struct irq_desc *desc)
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/* Dummy read from vector to clear the interrupt */
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/* Dummy read from vector to clear the interrupt */
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readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
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readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
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virq = irq_find_mapping(msi->inner_domain, bit);
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ret = generic_handle_domain_irq(msi->inner_domain, bit);
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if (virq)
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if (ret)
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generic_handle_irq(virq);
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dev_err_ratelimited(&msi->pdev->dev, "unexpected MSI\n");
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else
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dev_err(&msi->pdev->dev, "unexpected MSI\n");
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}
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}
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}
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}
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@ -646,7 +646,7 @@ static void altera_pcie_isr(struct irq_desc *desc)
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struct device *dev;
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struct device *dev;
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unsigned long status;
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unsigned long status;
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u32 bit;
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u32 bit;
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u32 virq;
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int ret;
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|
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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pcie = irq_desc_get_handler_data(desc);
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pcie = irq_desc_get_handler_data(desc);
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@ -658,11 +658,9 @@ static void altera_pcie_isr(struct irq_desc *desc)
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/* clear interrupts */
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/* clear interrupts */
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cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
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cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
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|
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virq = irq_find_mapping(pcie->irq_domain, bit);
|
ret = generic_handle_domain_irq(pcie->irq_domain, bit);
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if (virq)
|
if (ret)
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generic_handle_irq(virq);
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dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
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else
|
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dev_err(dev, "unexpected IRQ, INT%d\n", bit);
|
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}
|
}
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}
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}
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@ -476,7 +476,7 @@ static struct msi_domain_info brcm_msi_domain_info = {
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static void brcm_pcie_msi_isr(struct irq_desc *desc)
|
static void brcm_pcie_msi_isr(struct irq_desc *desc)
|
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{
|
{
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struct irq_chip *chip = irq_desc_get_chip(desc);
|
struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long status, virq;
|
unsigned long status;
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struct brcm_msi *msi;
|
struct brcm_msi *msi;
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struct device *dev;
|
struct device *dev;
|
||||||
u32 bit;
|
u32 bit;
|
||||||
@ -489,10 +489,9 @@ static void brcm_pcie_msi_isr(struct irq_desc *desc)
|
|||||||
status >>= msi->legacy_shift;
|
status >>= msi->legacy_shift;
|
||||||
|
|
||||||
for_each_set_bit(bit, &status, msi->nr) {
|
for_each_set_bit(bit, &status, msi->nr) {
|
||||||
virq = irq_find_mapping(msi->inner_domain, bit);
|
int ret;
|
||||||
if (virq)
|
ret = generic_handle_domain_irq(msi->inner_domain, bit);
|
||||||
generic_handle_irq(virq);
|
if (ret)
|
||||||
else
|
|
||||||
dev_dbg(dev, "unexpected MSI\n");
|
dev_dbg(dev, "unexpected MSI\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -326,7 +326,6 @@ static void iproc_msi_handler(struct irq_desc *desc)
|
|||||||
struct iproc_msi *msi;
|
struct iproc_msi *msi;
|
||||||
u32 eq, head, tail, nr_events;
|
u32 eq, head, tail, nr_events;
|
||||||
unsigned long hwirq;
|
unsigned long hwirq;
|
||||||
int virq;
|
|
||||||
|
|
||||||
chained_irq_enter(chip, desc);
|
chained_irq_enter(chip, desc);
|
||||||
|
|
||||||
@ -362,8 +361,7 @@ static void iproc_msi_handler(struct irq_desc *desc)
|
|||||||
/* process all outstanding events */
|
/* process all outstanding events */
|
||||||
while (nr_events--) {
|
while (nr_events--) {
|
||||||
hwirq = decode_msi_hwirq(msi, eq, head);
|
hwirq = decode_msi_hwirq(msi, eq, head);
|
||||||
virq = irq_find_mapping(msi->inner_domain, hwirq);
|
generic_handle_domain_irq(msi->inner_domain, hwirq);
|
||||||
generic_handle_irq(virq);
|
|
||||||
|
|
||||||
head++;
|
head++;
|
||||||
head %= EQ_LEN;
|
head %= EQ_LEN;
|
||||||
|
@ -645,7 +645,6 @@ static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx)
|
|||||||
{
|
{
|
||||||
struct mtk_msi_set *msi_set = &port->msi_sets[set_idx];
|
struct mtk_msi_set *msi_set = &port->msi_sets[set_idx];
|
||||||
unsigned long msi_enable, msi_status;
|
unsigned long msi_enable, msi_status;
|
||||||
unsigned int virq;
|
|
||||||
irq_hw_number_t bit, hwirq;
|
irq_hw_number_t bit, hwirq;
|
||||||
|
|
||||||
msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
|
msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
|
||||||
@ -659,8 +658,7 @@ static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx)
|
|||||||
|
|
||||||
for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
|
for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
|
||||||
hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
|
hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
|
||||||
virq = irq_find_mapping(port->msi_bottom_domain, hwirq);
|
generic_handle_domain_irq(port->msi_bottom_domain, hwirq);
|
||||||
generic_handle_irq(virq);
|
|
||||||
}
|
}
|
||||||
} while (true);
|
} while (true);
|
||||||
}
|
}
|
||||||
@ -670,18 +668,15 @@ static void mtk_pcie_irq_handler(struct irq_desc *desc)
|
|||||||
struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
|
struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
|
||||||
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
||||||
unsigned long status;
|
unsigned long status;
|
||||||
unsigned int virq;
|
|
||||||
irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
|
irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
|
||||||
|
|
||||||
chained_irq_enter(irqchip, desc);
|
chained_irq_enter(irqchip, desc);
|
||||||
|
|
||||||
status = readl_relaxed(port->base + PCIE_INT_STATUS_REG);
|
status = readl_relaxed(port->base + PCIE_INT_STATUS_REG);
|
||||||
for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
|
for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
|
||||||
PCIE_INTX_SHIFT) {
|
PCIE_INTX_SHIFT)
|
||||||
virq = irq_find_mapping(port->intx_domain,
|
generic_handle_domain_irq(port->intx_domain,
|
||||||
irq_bit - PCIE_INTX_SHIFT);
|
irq_bit - PCIE_INTX_SHIFT);
|
||||||
generic_handle_irq(virq);
|
|
||||||
}
|
|
||||||
|
|
||||||
irq_bit = PCIE_MSI_SHIFT;
|
irq_bit = PCIE_MSI_SHIFT;
|
||||||
for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
|
for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
|
||||||
|
@ -602,7 +602,6 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
|
|||||||
struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
|
struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
|
||||||
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
||||||
unsigned long status;
|
unsigned long status;
|
||||||
u32 virq;
|
|
||||||
u32 bit = INTX_SHIFT;
|
u32 bit = INTX_SHIFT;
|
||||||
|
|
||||||
chained_irq_enter(irqchip, desc);
|
chained_irq_enter(irqchip, desc);
|
||||||
@ -612,9 +611,8 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
|
|||||||
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
|
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
|
||||||
/* Clear the INTx */
|
/* Clear the INTx */
|
||||||
writel(1 << bit, port->base + PCIE_INT_STATUS);
|
writel(1 << bit, port->base + PCIE_INT_STATUS);
|
||||||
virq = irq_find_mapping(port->irq_domain,
|
generic_handle_domain_irq(port->irq_domain,
|
||||||
bit - INTX_SHIFT);
|
bit - INTX_SHIFT);
|
||||||
generic_handle_irq(virq);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -623,10 +621,8 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
|
|||||||
unsigned long imsi_status;
|
unsigned long imsi_status;
|
||||||
|
|
||||||
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
|
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
|
||||||
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
|
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
|
||||||
virq = irq_find_mapping(port->inner_domain, bit);
|
generic_handle_domain_irq(port->inner_domain, bit);
|
||||||
generic_handle_irq(virq);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
/* Clear MSI interrupt status */
|
/* Clear MSI interrupt status */
|
||||||
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
|
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
|
||||||
|
@ -412,16 +412,14 @@ static void mc_handle_msi(struct irq_desc *desc)
|
|||||||
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
||||||
unsigned long status;
|
unsigned long status;
|
||||||
u32 bit;
|
u32 bit;
|
||||||
u32 virq;
|
int ret;
|
||||||
|
|
||||||
status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
|
status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
|
||||||
if (status & PM_MSI_INT_MSI_MASK) {
|
if (status & PM_MSI_INT_MSI_MASK) {
|
||||||
status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
|
status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
|
||||||
for_each_set_bit(bit, &status, msi->num_vectors) {
|
for_each_set_bit(bit, &status, msi->num_vectors) {
|
||||||
virq = irq_find_mapping(msi->dev_domain, bit);
|
ret = generic_handle_domain_irq(msi->dev_domain, bit);
|
||||||
if (virq)
|
if (ret)
|
||||||
generic_handle_irq(virq);
|
|
||||||
else
|
|
||||||
dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
|
dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
|
||||||
bit);
|
bit);
|
||||||
}
|
}
|
||||||
@ -570,17 +568,15 @@ static void mc_handle_intx(struct irq_desc *desc)
|
|||||||
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
||||||
unsigned long status;
|
unsigned long status;
|
||||||
u32 bit;
|
u32 bit;
|
||||||
u32 virq;
|
int ret;
|
||||||
|
|
||||||
status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
|
status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
|
||||||
if (status & PM_MSI_INT_INTX_MASK) {
|
if (status & PM_MSI_INT_INTX_MASK) {
|
||||||
status &= PM_MSI_INT_INTX_MASK;
|
status &= PM_MSI_INT_INTX_MASK;
|
||||||
status >>= PM_MSI_INT_INTX_SHIFT;
|
status >>= PM_MSI_INT_INTX_SHIFT;
|
||||||
for_each_set_bit(bit, &status, PCI_NUM_INTX) {
|
for_each_set_bit(bit, &status, PCI_NUM_INTX) {
|
||||||
virq = irq_find_mapping(port->intx_domain, bit);
|
ret = generic_handle_domain_irq(port->intx_domain, bit);
|
||||||
if (virq)
|
if (ret)
|
||||||
generic_handle_irq(virq);
|
|
||||||
else
|
|
||||||
dev_err_ratelimited(dev, "bad INTx IRQ %d\n",
|
dev_err_ratelimited(dev, "bad INTx IRQ %d\n",
|
||||||
bit);
|
bit);
|
||||||
}
|
}
|
||||||
@ -745,7 +741,7 @@ static void mc_handle_event(struct irq_desc *desc)
|
|||||||
events = get_events(port);
|
events = get_events(port);
|
||||||
|
|
||||||
for_each_set_bit(bit, &events, NUM_EVENTS)
|
for_each_set_bit(bit, &events, NUM_EVENTS)
|
||||||
generic_handle_irq(irq_find_mapping(port->event_domain, bit));
|
generic_handle_domain_irq(port->event_domain, bit);
|
||||||
|
|
||||||
chained_irq_exit(chip, desc);
|
chained_irq_exit(chip, desc);
|
||||||
}
|
}
|
||||||
|
@ -486,12 +486,10 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
|
|||||||
|
|
||||||
while (reg) {
|
while (reg) {
|
||||||
unsigned int index = find_first_bit(®, 32);
|
unsigned int index = find_first_bit(®, 32);
|
||||||
unsigned int msi_irq;
|
int ret;
|
||||||
|
|
||||||
msi_irq = irq_find_mapping(msi->domain->parent, index);
|
ret = generic_handle_domain_irq(msi->domain->parent, index);
|
||||||
if (msi_irq) {
|
if (ret) {
|
||||||
generic_handle_irq(msi_irq);
|
|
||||||
} else {
|
|
||||||
/* Unknown MSI, just clear it */
|
/* Unknown MSI, just clear it */
|
||||||
dev_dbg(dev, "unexpected MSI\n");
|
dev_dbg(dev, "unexpected MSI\n");
|
||||||
rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
|
rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
|
||||||
|
@ -517,7 +517,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
|
|||||||
struct device *dev = rockchip->dev;
|
struct device *dev = rockchip->dev;
|
||||||
u32 reg;
|
u32 reg;
|
||||||
u32 hwirq;
|
u32 hwirq;
|
||||||
u32 virq;
|
int ret;
|
||||||
|
|
||||||
chained_irq_enter(chip, desc);
|
chained_irq_enter(chip, desc);
|
||||||
|
|
||||||
@ -528,10 +528,8 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
|
|||||||
hwirq = ffs(reg) - 1;
|
hwirq = ffs(reg) - 1;
|
||||||
reg &= ~BIT(hwirq);
|
reg &= ~BIT(hwirq);
|
||||||
|
|
||||||
virq = irq_find_mapping(rockchip->irq_domain, hwirq);
|
ret = generic_handle_domain_irq(rockchip->irq_domain, hwirq);
|
||||||
if (virq)
|
if (ret)
|
||||||
generic_handle_irq(virq);
|
|
||||||
else
|
|
||||||
dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
|
dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -222,7 +222,7 @@ static void xilinx_cpm_pcie_intx_flow(struct irq_desc *desc)
|
|||||||
pcie_read(port, XILINX_CPM_PCIE_REG_IDRN));
|
pcie_read(port, XILINX_CPM_PCIE_REG_IDRN));
|
||||||
|
|
||||||
for_each_set_bit(i, &val, PCI_NUM_INTX)
|
for_each_set_bit(i, &val, PCI_NUM_INTX)
|
||||||
generic_handle_irq(irq_find_mapping(port->intx_domain, i));
|
generic_handle_domain_irq(port->intx_domain, i);
|
||||||
|
|
||||||
chained_irq_exit(chip, desc);
|
chained_irq_exit(chip, desc);
|
||||||
}
|
}
|
||||||
@ -282,7 +282,7 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
|
|||||||
val = pcie_read(port, XILINX_CPM_PCIE_REG_IDR);
|
val = pcie_read(port, XILINX_CPM_PCIE_REG_IDR);
|
||||||
val &= pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
|
val &= pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
|
||||||
for_each_set_bit(i, &val, 32)
|
for_each_set_bit(i, &val, 32)
|
||||||
generic_handle_irq(irq_find_mapping(port->cpm_domain, i));
|
generic_handle_domain_irq(port->cpm_domain, i);
|
||||||
pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
|
pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -318,18 +318,14 @@ static void nwl_pcie_leg_handler(struct irq_desc *desc)
|
|||||||
struct nwl_pcie *pcie;
|
struct nwl_pcie *pcie;
|
||||||
unsigned long status;
|
unsigned long status;
|
||||||
u32 bit;
|
u32 bit;
|
||||||
u32 virq;
|
|
||||||
|
|
||||||
chained_irq_enter(chip, desc);
|
chained_irq_enter(chip, desc);
|
||||||
pcie = irq_desc_get_handler_data(desc);
|
pcie = irq_desc_get_handler_data(desc);
|
||||||
|
|
||||||
while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
|
while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
|
||||||
MSGF_LEG_SR_MASKALL) != 0) {
|
MSGF_LEG_SR_MASKALL) != 0) {
|
||||||
for_each_set_bit(bit, &status, PCI_NUM_INTX) {
|
for_each_set_bit(bit, &status, PCI_NUM_INTX)
|
||||||
virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
|
generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
|
||||||
if (virq)
|
|
||||||
generic_handle_irq(virq);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
chained_irq_exit(chip, desc);
|
chained_irq_exit(chip, desc);
|
||||||
@ -340,16 +336,13 @@ static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
|
|||||||
struct nwl_msi *msi;
|
struct nwl_msi *msi;
|
||||||
unsigned long status;
|
unsigned long status;
|
||||||
u32 bit;
|
u32 bit;
|
||||||
u32 virq;
|
|
||||||
|
|
||||||
msi = &pcie->msi;
|
msi = &pcie->msi;
|
||||||
|
|
||||||
while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
|
while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
|
||||||
for_each_set_bit(bit, &status, 32) {
|
for_each_set_bit(bit, &status, 32) {
|
||||||
nwl_bridge_writel(pcie, 1 << bit, status_reg);
|
nwl_bridge_writel(pcie, 1 << bit, status_reg);
|
||||||
virq = irq_find_mapping(msi->dev_domain, bit);
|
generic_handle_domain_irq(msi->dev_domain, bit);
|
||||||
if (virq)
|
|
||||||
generic_handle_irq(virq);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -385,7 +385,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {
|
if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {
|
||||||
unsigned int irq;
|
struct irq_domain *domain;
|
||||||
|
|
||||||
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
|
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
|
||||||
|
|
||||||
@ -399,19 +399,18 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
|
|||||||
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
|
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
|
||||||
val = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
|
val = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
|
||||||
XILINX_PCIE_RPIFR2_MSG_DATA;
|
XILINX_PCIE_RPIFR2_MSG_DATA;
|
||||||
irq = irq_find_mapping(port->msi_domain->parent, val);
|
domain = port->msi_domain->parent;
|
||||||
} else {
|
} else {
|
||||||
val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
|
val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
|
||||||
XILINX_PCIE_RPIFR1_INTR_SHIFT;
|
XILINX_PCIE_RPIFR1_INTR_SHIFT;
|
||||||
irq = irq_find_mapping(port->leg_domain, val);
|
domain = port->leg_domain;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Clear interrupt FIFO register 1 */
|
/* Clear interrupt FIFO register 1 */
|
||||||
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
|
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
|
||||||
XILINX_PCIE_REG_RPIFR1);
|
XILINX_PCIE_REG_RPIFR1);
|
||||||
|
|
||||||
if (irq)
|
generic_handle_domain_irq(domain, val);
|
||||||
generic_handle_irq(irq);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
|
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
|
||||||
|
Loading…
Reference in New Issue
Block a user