mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-25 05:04:09 +08:00
Merge branch 'pci/pm'
- Cache the PTM capability offset instead of searching for it every time (Bjorn Helgaas) - Separate PTM configuration from PTM enable (Bjorn Helgaas) - Add pci_suspend_ptm() and pci_resume_ptm() to disable and re-enable PTM on suspend/resume so some Root Ports can safely enter a lower-power PM state (Bjorn Helgaas) - Disable PTM for all devices during suspend; previously we only did this for Root Ports and even then only in certain cases (Bjorn Helgaas) - Simplify pci_pm_suspend_noirq() (Rajvi Jingar) - Reduce the delay after transitions to/from D3hot by using usleep_range() instead of msleep(), which reduces the typical delay from 19ms to 10ms (Sajid Dalvi, Will McVicker) * pci/pm: PCI/PM: Reduce D3hot delay with usleep_range() PCI/PM: Simplify pci_pm_suspend_noirq() PCI/PM: Always disable PTM for all devices during suspend PCI/PTM: Consolidate PTM interface declarations PCI/PTM: Reorder functions in logical order PCI/PTM: Preserve RsvdP bits in PTM Control register PCI/PTM: Move pci_ptm_info() body into its only caller PCI/PTM: Add pci_suspend_ptm() and pci_resume_ptm() PCI/PTM: Separate configuration and enable PCI/PTM: Add pci_upstream_ptm() helper PCI/PTM: Cache PTM Capability offset
This commit is contained in:
Bjorn Helgaas
commit
034f93fcb1
@ -774,6 +774,12 @@ static int pci_pm_suspend(struct device *dev)
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pci_dev->skip_bus_pm = false;
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/*
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* Disabling PTM allows some systems, e.g., Intel mobile chips
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* since Coffee Lake, to enter a lower-power PM state.
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*/
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pci_suspend_ptm(pci_dev);
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_suspend(dev, PMSG_SUSPEND);
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@ -867,20 +873,15 @@ static int pci_pm_suspend_noirq(struct device *dev)
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}
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}
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if (pci_dev->skip_bus_pm) {
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/*
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* Either the device is a bridge with a child in D0 below it, or
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* the function is running for the second time in a row without
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* going through full resume, which is possible only during
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* suspend-to-idle in a spurious wakeup case. The device should
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* be in D0 at this point, but if it is a bridge, it may be
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* necessary to save its state.
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*/
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if (!pci_dev->state_saved)
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pci_save_state(pci_dev);
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} else if (!pci_dev->state_saved) {
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if (!pci_dev->state_saved) {
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pci_save_state(pci_dev);
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if (pci_power_manageable(pci_dev))
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/*
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* If the device is a bridge with a child in D0 below it,
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* it needs to stay in D0, so check skip_bus_pm to avoid
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* putting it into a low-power state in that case.
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*/
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if (!pci_dev->skip_bus_pm && pci_power_manageable(pci_dev))
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pci_prepare_to_sleep(pci_dev);
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}
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@ -987,6 +988,8 @@ static int pci_pm_resume(struct device *dev)
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if (pci_dev->state_saved)
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pci_restore_standard_config(pci_dev);
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pci_resume_ptm(pci_dev);
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_resume(dev);
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@ -1274,6 +1277,8 @@ static int pci_pm_runtime_suspend(struct device *dev)
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pci_power_t prev = pci_dev->current_state;
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int error;
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pci_suspend_ptm(pci_dev);
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/*
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* If pci_dev->driver is not set (unbound), we leave the device in D0,
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* but it may go to D3cold when the bridge above it runtime suspends.
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@ -1335,6 +1340,7 @@ static int pci_pm_runtime_resume(struct device *dev)
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* D3cold when the bridge above it runtime suspended.
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*/
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pci_pm_default_resume_early(pci_dev);
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pci_resume_ptm(pci_dev);
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if (!pci_dev->driver)
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return 0;
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@ -66,13 +66,15 @@ struct pci_pme_device {
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static void pci_dev_d3_sleep(struct pci_dev *dev)
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{
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unsigned int delay = dev->d3hot_delay;
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unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
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unsigned int upper;
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if (delay < pci_pm_d3hot_delay)
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delay = pci_pm_d3hot_delay;
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if (delay)
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msleep(delay);
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if (delay_ms) {
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/* Use a 20% upper bound, 1ms minimum */
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upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
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usleep_range(delay_ms * USEC_PER_MSEC,
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(delay_ms + upper) * USEC_PER_MSEC);
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}
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}
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bool pci_reset_supported(struct pci_dev *dev)
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@ -2708,24 +2710,12 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
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if (target_state == PCI_POWER_ERROR)
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return -EIO;
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/*
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* There are systems (for example, Intel mobile chips since Coffee
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* Lake) where the power drawn while suspended can be significantly
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* reduced by disabling PTM on PCIe root ports as this allows the
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* port to enter a lower-power PM state and the SoC to reach a
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* lower-power idle state as a whole.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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pci_disable_ptm(dev);
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pci_enable_wake(dev, target_state, wakeup);
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error = pci_set_power_state(dev, target_state);
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if (error) {
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if (error)
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pci_enable_wake(dev, target_state, false);
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pci_restore_ptm_state(dev);
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}
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return error;
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}
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@ -2766,24 +2756,12 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
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if (target_state == PCI_POWER_ERROR)
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return -EIO;
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/*
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* There are systems (for example, Intel mobile chips since Coffee
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* Lake) where the power drawn while suspended can be significantly
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* reduced by disabling PTM on PCIe root ports as this allows the
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* port to enter a lower-power PM state and the SoC to reach a
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* lower-power idle state as a whole.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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pci_disable_ptm(dev);
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__pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
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error = pci_set_power_state(dev, target_state);
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if (error) {
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if (error)
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pci_enable_wake(dev, target_state, false);
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pci_restore_ptm_state(dev);
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}
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return error;
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}
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@ -505,13 +505,17 @@ static inline int pci_iov_bus_range(struct pci_bus *bus)
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#endif /* CONFIG_PCI_IOV */
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#ifdef CONFIG_PCIE_PTM
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void pci_ptm_init(struct pci_dev *dev);
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void pci_save_ptm_state(struct pci_dev *dev);
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void pci_restore_ptm_state(struct pci_dev *dev);
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void pci_disable_ptm(struct pci_dev *dev);
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void pci_suspend_ptm(struct pci_dev *dev);
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void pci_resume_ptm(struct pci_dev *dev);
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#else
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static inline void pci_ptm_init(struct pci_dev *dev) { }
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static inline void pci_save_ptm_state(struct pci_dev *dev) { }
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static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
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static inline void pci_disable_ptm(struct pci_dev *dev) { }
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static inline void pci_suspend_ptm(struct pci_dev *dev) { }
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static inline void pci_resume_ptm(struct pci_dev *dev) { }
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#endif
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unsigned long pci_cardbus_resource_alignment(struct resource *);
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@ -579,12 +583,6 @@ static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
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static inline void pcie_ecrc_get_policy(char *str) { }
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#endif
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#ifdef CONFIG_PCIE_PTM
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void pci_ptm_init(struct pci_dev *dev);
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#else
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static inline void pci_ptm_init(struct pci_dev *dev) { }
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#endif
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struct pci_dev_reset_methods {
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u16 vendor;
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u16 device;
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@ -9,10 +9,176 @@
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#include <linux/pci.h>
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#include "../pci.h"
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static void pci_ptm_info(struct pci_dev *dev)
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/*
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* If the next upstream device supports PTM, return it; otherwise return
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* NULL. PTM Messages are local, so both link partners must support it.
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*/
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static struct pci_dev *pci_upstream_ptm(struct pci_dev *dev)
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{
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struct pci_dev *ups = pci_upstream_bridge(dev);
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/*
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* Switch Downstream Ports are not permitted to have a PTM
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* capability; their PTM behavior is controlled by the Upstream
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* Port (PCIe r5.0, sec 7.9.16), so if the upstream bridge is a
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* Switch Downstream Port, look up one more level.
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*/
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if (ups && pci_pcie_type(ups) == PCI_EXP_TYPE_DOWNSTREAM)
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ups = pci_upstream_bridge(ups);
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if (ups && ups->ptm_cap)
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return ups;
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return NULL;
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}
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/*
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* Find the PTM Capability (if present) and extract the information we need
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* to use it.
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*/
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void pci_ptm_init(struct pci_dev *dev)
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{
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u16 ptm;
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u32 cap;
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struct pci_dev *ups;
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if (!pci_is_pcie(dev))
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return;
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ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
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if (!ptm)
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return;
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dev->ptm_cap = ptm;
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pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32));
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pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap);
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dev->ptm_granularity = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
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/*
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* Per the spec recommendation (PCIe r6.0, sec 7.9.15.3), select the
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* furthest upstream Time Source as the PTM Root. For Endpoints,
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* "the Effective Granularity is the maximum Local Clock Granularity
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* reported by the PTM Root and all intervening PTM Time Sources."
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*/
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ups = pci_upstream_ptm(dev);
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if (ups) {
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if (ups->ptm_granularity == 0)
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dev->ptm_granularity = 0;
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else if (ups->ptm_granularity > dev->ptm_granularity)
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dev->ptm_granularity = ups->ptm_granularity;
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} else if (cap & PCI_PTM_CAP_ROOT) {
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dev->ptm_root = 1;
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} else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
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/*
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* Per sec 7.9.15.3, this should be the Local Clock
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* Granularity of the associated Time Source. But it
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* doesn't say how to find that Time Source.
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*/
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dev->ptm_granularity = 0;
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}
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
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pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)
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pci_enable_ptm(dev, NULL);
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}
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void pci_save_ptm_state(struct pci_dev *dev)
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{
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u16 ptm = dev->ptm_cap;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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if (!ptm)
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
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if (!save_state)
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return;
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cap = (u32 *)&save_state->cap.data[0];
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pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, cap);
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}
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void pci_restore_ptm_state(struct pci_dev *dev)
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{
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u16 ptm = dev->ptm_cap;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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if (!ptm)
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
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if (!save_state)
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return;
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cap = (u32 *)&save_state->cap.data[0];
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pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, *cap);
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}
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/* Enable PTM in the Control register if possible */
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static int __pci_enable_ptm(struct pci_dev *dev)
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{
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u16 ptm = dev->ptm_cap;
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struct pci_dev *ups;
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u32 ctrl;
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if (!ptm)
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return -EINVAL;
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/*
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* A device uses local PTM Messages to request time information
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* from a PTM Root that's farther upstream. Every device along the
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* path must support PTM and have it enabled so it can handle the
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* messages. Therefore, if this device is not a PTM Root, the
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* upstream link partner must have PTM enabled before we can enable
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* PTM.
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*/
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if (!dev->ptm_root) {
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ups = pci_upstream_ptm(dev);
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if (!ups || !ups->ptm_enabled)
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return -EINVAL;
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}
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pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
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ctrl |= PCI_PTM_CTRL_ENABLE;
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ctrl &= ~PCI_PTM_GRANULARITY_MASK;
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ctrl |= dev->ptm_granularity << 8;
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if (dev->ptm_root)
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ctrl |= PCI_PTM_CTRL_ROOT;
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pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl);
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return 0;
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}
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/**
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* pci_enable_ptm() - Enable Precision Time Measurement
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* @dev: PCI device
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* @granularity: pointer to return granularity
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*
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* Enable Precision Time Measurement for @dev. If successful and
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* @granularity is non-NULL, return the Effective Granularity.
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*
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* Return: zero if successful, or -EINVAL if @dev lacks a PTM Capability or
|
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* is not a PTM Root and lacks an upstream path of PTM-enabled devices.
|
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*/
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int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
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{
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int rc;
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char clock_desc[8];
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rc = __pci_enable_ptm(dev);
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if (rc)
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return rc;
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dev->ptm_enabled = 1;
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if (granularity)
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*granularity = dev->ptm_granularity;
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switch (dev->ptm_granularity) {
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case 0:
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snprintf(clock_desc, sizeof(clock_desc), "unknown");
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@ -27,182 +193,56 @@ static void pci_ptm_info(struct pci_dev *dev)
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}
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pci_info(dev, "PTM enabled%s, %s granularity\n",
|
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dev->ptm_root ? " (root)" : "", clock_desc);
|
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}
|
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|
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void pci_disable_ptm(struct pci_dev *dev)
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{
|
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int ptm;
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u16 ctrl;
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if (!pci_is_pcie(dev))
|
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return;
|
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|
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ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
|
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if (!ptm)
|
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return;
|
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|
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pci_read_config_word(dev, ptm + PCI_PTM_CTRL, &ctrl);
|
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ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT);
|
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pci_write_config_word(dev, ptm + PCI_PTM_CTRL, ctrl);
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}
|
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|
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void pci_save_ptm_state(struct pci_dev *dev)
|
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{
|
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int ptm;
|
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struct pci_cap_saved_state *save_state;
|
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u16 *cap;
|
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|
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if (!pci_is_pcie(dev))
|
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return;
|
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|
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ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
|
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if (!ptm)
|
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return;
|
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|
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
|
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if (!save_state)
|
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return;
|
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|
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cap = (u16 *)&save_state->cap.data[0];
|
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pci_read_config_word(dev, ptm + PCI_PTM_CTRL, cap);
|
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}
|
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|
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void pci_restore_ptm_state(struct pci_dev *dev)
|
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{
|
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struct pci_cap_saved_state *save_state;
|
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int ptm;
|
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u16 *cap;
|
||||
|
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if (!pci_is_pcie(dev))
|
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return;
|
||||
|
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
|
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ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
|
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if (!save_state || !ptm)
|
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return;
|
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|
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cap = (u16 *)&save_state->cap.data[0];
|
||||
pci_write_config_word(dev, ptm + PCI_PTM_CTRL, *cap);
|
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}
|
||||
|
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void pci_ptm_init(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u32 cap, ctrl;
|
||||
u8 local_clock;
|
||||
struct pci_dev *ups;
|
||||
|
||||
if (!pci_is_pcie(dev))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Enable PTM only on interior devices (root ports, switch ports,
|
||||
* etc.) on the assumption that it causes no link traffic until an
|
||||
* endpoint enables it.
|
||||
*/
|
||||
if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
|
||||
pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Switch Downstream Ports are not permitted to have a PTM
|
||||
* capability; their PTM behavior is controlled by the Upstream
|
||||
* Port (PCIe r5.0, sec 7.9.16).
|
||||
*/
|
||||
ups = pci_upstream_bridge(dev);
|
||||
if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
|
||||
ups && ups->ptm_enabled) {
|
||||
dev->ptm_granularity = ups->ptm_granularity;
|
||||
dev->ptm_enabled = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u16));
|
||||
|
||||
pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
|
||||
local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
|
||||
|
||||
/*
|
||||
* There's no point in enabling PTM unless it's enabled in the
|
||||
* upstream device or this device can be a PTM Root itself. Per
|
||||
* the spec recommendation (PCIe r3.1, sec 7.32.3), select the
|
||||
* furthest upstream Time Source as the PTM Root.
|
||||
*/
|
||||
if (ups && ups->ptm_enabled) {
|
||||
ctrl = PCI_PTM_CTRL_ENABLE;
|
||||
if (ups->ptm_granularity == 0)
|
||||
dev->ptm_granularity = 0;
|
||||
else if (ups->ptm_granularity > local_clock)
|
||||
dev->ptm_granularity = ups->ptm_granularity;
|
||||
} else {
|
||||
if (cap & PCI_PTM_CAP_ROOT) {
|
||||
ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
|
||||
dev->ptm_root = 1;
|
||||
dev->ptm_granularity = local_clock;
|
||||
} else
|
||||
return;
|
||||
}
|
||||
|
||||
ctrl |= dev->ptm_granularity << 8;
|
||||
pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
|
||||
dev->ptm_enabled = 1;
|
||||
|
||||
pci_ptm_info(dev);
|
||||
}
|
||||
|
||||
int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
|
||||
{
|
||||
int pos;
|
||||
u32 cap, ctrl;
|
||||
struct pci_dev *ups;
|
||||
|
||||
if (!pci_is_pcie(dev))
|
||||
return -EINVAL;
|
||||
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
|
||||
if (!pos)
|
||||
return -EINVAL;
|
||||
|
||||
pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
|
||||
if (!(cap & PCI_PTM_CAP_REQ))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* For a PCIe Endpoint, PTM is only useful if the endpoint can
|
||||
* issue PTM requests to upstream devices that have PTM enabled.
|
||||
*
|
||||
* For Root Complex Integrated Endpoints, there is no upstream
|
||||
* device, so there must be some implementation-specific way to
|
||||
* associate the endpoint with a time source.
|
||||
*/
|
||||
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
|
||||
ups = pci_upstream_bridge(dev);
|
||||
if (!ups || !ups->ptm_enabled)
|
||||
return -EINVAL;
|
||||
|
||||
dev->ptm_granularity = ups->ptm_granularity;
|
||||
} else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
|
||||
dev->ptm_granularity = 0;
|
||||
} else
|
||||
return -EINVAL;
|
||||
|
||||
ctrl = PCI_PTM_CTRL_ENABLE;
|
||||
ctrl |= dev->ptm_granularity << 8;
|
||||
pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
|
||||
dev->ptm_enabled = 1;
|
||||
|
||||
pci_ptm_info(dev);
|
||||
|
||||
if (granularity)
|
||||
*granularity = dev->ptm_granularity;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_enable_ptm);
|
||||
|
||||
static void __pci_disable_ptm(struct pci_dev *dev)
|
||||
{
|
||||
u16 ptm = dev->ptm_cap;
|
||||
u32 ctrl;
|
||||
|
||||
if (!ptm)
|
||||
return;
|
||||
|
||||
pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
|
||||
ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT);
|
||||
pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_disable_ptm() - Disable Precision Time Measurement
|
||||
* @dev: PCI device
|
||||
*
|
||||
* Disable Precision Time Measurement for @dev.
|
||||
*/
|
||||
void pci_disable_ptm(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->ptm_enabled) {
|
||||
__pci_disable_ptm(dev);
|
||||
dev->ptm_enabled = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_ptm);
|
||||
|
||||
/*
|
||||
* Disable PTM, but preserve dev->ptm_enabled so we silently re-enable it on
|
||||
* resume if necessary.
|
||||
*/
|
||||
void pci_suspend_ptm(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->ptm_enabled)
|
||||
__pci_disable_ptm(dev);
|
||||
}
|
||||
|
||||
/* If PTM was enabled before suspend, re-enable it when resuming */
|
||||
void pci_resume_ptm(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->ptm_enabled)
|
||||
__pci_enable_ptm(dev);
|
||||
}
|
||||
|
||||
bool pcie_ptm_enabled(struct pci_dev *dev)
|
||||
{
|
||||
if (!dev)
|
||||
|
||||
@ -475,6 +475,7 @@ struct pci_dev {
|
||||
unsigned int broken_cmd_compl:1; /* No compl for some cmds */
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE_PTM
|
||||
u16 ptm_cap; /* PTM Capability */
|
||||
unsigned int ptm_root:1;
|
||||
unsigned int ptm_enabled:1;
|
||||
u8 ptm_granularity;
|
||||
@ -1677,10 +1678,12 @@ bool pci_ats_disabled(void);
|
||||
|
||||
#ifdef CONFIG_PCIE_PTM
|
||||
int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
|
||||
void pci_disable_ptm(struct pci_dev *dev);
|
||||
bool pcie_ptm_enabled(struct pci_dev *dev);
|
||||
#else
|
||||
static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
|
||||
{ return -EINVAL; }
|
||||
static inline void pci_disable_ptm(struct pci_dev *dev) { }
|
||||
static inline bool pcie_ptm_enabled(struct pci_dev *dev)
|
||||
{ return false; }
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user