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drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650
Update the gmu_pdc registers for A640 and A650. Some of the RSCC registers on A650 are in a separate region. Note this also changes the address of these registers: RSCC_TCS1_DRV0_STATUS RSCC_TCS2_DRV0_STATUS RSCC_TCS3_DRV0_STATUS Based on the values in msm-4.14 and msm-4.19 kernels. v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Jonathan Marek
Rob Clark
parent
c6ed04f856
commit
02ef80c54e
@ -429,7 +429,7 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
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return ret;
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}
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ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
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ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
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!val, 100, 10000);
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if (ret) {
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@ -455,7 +455,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
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gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
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ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
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ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
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val, val & (1 << 16), 100, 10000);
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if (ret)
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DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
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@ -478,32 +478,48 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
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struct platform_device *pdev = to_platform_device(gmu->dev);
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void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
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void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
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uint32_t pdc_address_offset;
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if (!pdcptr || !seqptr)
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goto err;
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if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
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pdc_address_offset = 0x30090;
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else if (adreno_is_a650(adreno_gpu))
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pdc_address_offset = 0x300a0;
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else
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pdc_address_offset = 0x30080;
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/* Disable SDE clock gating */
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gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
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gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
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/* Setup RSC PDC handshake for sleep and wakeup */
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gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
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gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
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gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
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gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
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gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
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gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
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gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
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gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
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gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
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gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
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gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
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/* Load RSC sequencer uCode for sleep and wakeup */
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gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
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gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
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gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
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gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
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gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
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if (adreno_is_a650(adreno_gpu)) {
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
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} else {
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
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gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
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}
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/* Load PDC sequencer uCode for power up and power down sequence */
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pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
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@ -524,10 +540,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
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if (adreno_is_a618(adreno_gpu))
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090);
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else
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
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@ -539,17 +552,12 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
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if (adreno_is_a618(adreno_gpu))
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if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
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else
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
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if (adreno_is_a618(adreno_gpu))
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090);
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else
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
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/* Setup GPU PDC */
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@ -796,13 +804,13 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
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u32 val;
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/* Make sure there are no outstanding RPMh votes */
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gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
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gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
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(val & 1), 100, 10000);
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gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
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gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
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(val & 1), 100, 10000);
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gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
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gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
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(val & 1), 100, 10000);
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gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
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gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
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(val & 1), 100, 1000);
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}
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@ -1361,6 +1369,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
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void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
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{
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struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
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struct platform_device *pdev = to_platform_device(gmu->dev);
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if (!gmu->initialized)
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return;
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@ -1373,7 +1382,10 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
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}
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iounmap(gmu->mmio);
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if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
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iounmap(gmu->rscc);
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gmu->mmio = NULL;
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gmu->rscc = NULL;
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a6xx_gmu_memory_free(gmu);
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@ -1456,6 +1468,14 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
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goto err_memory;
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}
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if (adreno_is_a650(adreno_gpu)) {
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gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
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if (IS_ERR(gmu->rscc))
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goto err_mmio;
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} else {
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gmu->rscc = gmu->mmio + 0x23000;
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}
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/* Get the HFI and GMU interrupts */
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gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
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gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
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@ -1481,6 +1501,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
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err_mmio:
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iounmap(gmu->mmio);
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if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
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iounmap(gmu->rscc);
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free_irq(gmu->gmu_irq, gmu);
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free_irq(gmu->hfi_irq, gmu);
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@ -47,6 +47,7 @@ struct a6xx_gmu {
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struct msm_gem_address_space *aspace;
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void * __iomem mmio;
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void * __iomem rscc;
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int hfi_irq;
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int gmu_irq;
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@ -125,6 +126,15 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
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readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
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interval, timeout)
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static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
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{
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return msm_writel(value, gmu->rscc + (offset << 2));
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}
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#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
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readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
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interval, timeout)
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/*
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* These are the available OOB (out of band requests) to the GMU where "out of
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* band" means that the CPU talks to the GMU directly and not through HFI.
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@ -336,8 +336,6 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
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#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
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#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04
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#define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
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#define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
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@ -350,39 +348,41 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
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#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
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#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00008c08
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#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
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#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00008c09
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#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
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#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x00008c0a
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#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009
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#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x00008c0b
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#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a
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#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x00008c0d
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#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b
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#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x00008c0e
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#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00008c82
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#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00008c83
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00008c89
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x00008c8c
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089
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#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00008d00
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c
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#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00008d01
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#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100
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#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00008d80
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#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
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#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00008f46
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#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
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#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000090ae
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#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
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#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00009216
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#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee
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#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000937e
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#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496
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#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e
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#endif /* A6XX_GMU_XML */
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