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RDMA/rxe: Extend rxe packet format to support flush

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Extend rxe opcode tables, headers, helper and constants to support
flush operations.

Refer to the IBA A19.4.1 for more FETH definition details

Link: https://lore.kernel.org/r/20221206130201.30986-6-lizhijian@fujitsu.com
Reviewed-by: Zhu Yanjun <zyjzyj2000@gmail.com>
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Li Zhijian 2022-12-06 21:01:56 +08:00 committed by Jason Gunthorpe
parent 02ea0a5115
commit 02e9a31c89
3 changed files with 73 additions and 5 deletions
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47
drivers/infiniband/sw/rxe/rxe_hdr.h
View File

@ -607,6 +607,52 @@ static inline void reth_set_len(struct rxe_pkt_info *pkt, u32 len)
rxe_opcode[pkt->opcode].offset[RXE_RETH], len);
}
/******************************************************************************
* FLUSH Extended Transport Header
******************************************************************************/
struct rxe_feth {
__be32 bits;
};
#define FETH_PLT_MASK (0x0000000f) /* bits 3-0 */
#define FETH_SEL_MASK (0x00000030) /* bits 5-4 */
#define FETH_SEL_SHIFT (4U)
static inline u32 __feth_plt(void *arg)
{
struct rxe_feth *feth = arg;
return be32_to_cpu(feth->bits) & FETH_PLT_MASK;
}
static inline u32 __feth_sel(void *arg)
{
struct rxe_feth *feth = arg;
return (be32_to_cpu(feth->bits) & FETH_SEL_MASK) >> FETH_SEL_SHIFT;
}
static inline u32 feth_plt(struct rxe_pkt_info *pkt)
{
return __feth_plt(pkt->hdr + rxe_opcode[pkt->opcode].offset[RXE_FETH]);
}
static inline u32 feth_sel(struct rxe_pkt_info *pkt)
{
return __feth_sel(pkt->hdr + rxe_opcode[pkt->opcode].offset[RXE_FETH]);
}
static inline void feth_init(struct rxe_pkt_info *pkt, u8 type, u8 level)
{
struct rxe_feth *feth = (struct rxe_feth *)
(pkt->hdr + rxe_opcode[pkt->opcode].offset[RXE_FETH]);
u32 bits = ((level << FETH_SEL_SHIFT) & FETH_SEL_MASK) |
(type & FETH_PLT_MASK);
feth->bits = cpu_to_be32(bits);
}
/******************************************************************************
* Atomic Extended Transport Header
******************************************************************************/
@ -909,6 +955,7 @@ enum rxe_hdr_length {
RXE_ATMETH_BYTES = sizeof(struct rxe_atmeth),
RXE_IETH_BYTES = sizeof(struct rxe_ieth),
RXE_RDETH_BYTES = sizeof(struct rxe_rdeth),
RXE_FETH_BYTES = sizeof(struct rxe_feth),
};
static inline size_t header_size(struct rxe_pkt_info *pkt)

17
drivers/infiniband/sw/rxe/rxe_opcode.c
View File

@ -101,6 +101,12 @@ struct rxe_wr_opcode_info rxe_wr_opcode_info[] = {
[IB_QPT_UC] = WR_LOCAL_OP_MASK,
},
},
[IB_WR_FLUSH] = {
.name = "IB_WR_FLUSH",
.mask = {
[IB_QPT_RC] = WR_FLUSH_MASK,
},
},
[IB_WR_ATOMIC_WRITE] = {
.name = "IB_WR_ATOMIC_WRITE",
.mask = {
@ -384,6 +390,17 @@ struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE] = {
RXE_IETH_BYTES,
}
},
[IB_OPCODE_RC_FLUSH] = {
.name = "IB_OPCODE_RC_FLUSH",
.mask = RXE_FETH_MASK | RXE_RETH_MASK | RXE_FLUSH_MASK |
RXE_START_MASK | RXE_END_MASK | RXE_REQ_MASK,
.length = RXE_BTH_BYTES + RXE_FETH_BYTES + RXE_RETH_BYTES,
.offset = {
[RXE_BTH] = 0,
[RXE_FETH] = RXE_BTH_BYTES,
[RXE_RETH] = RXE_BTH_BYTES + RXE_FETH_BYTES,
}
},
[IB_OPCODE_RC_ATOMIC_WRITE] = {
.name = "IB_OPCODE_RC_ATOMIC_WRITE",
.mask = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK |

14
drivers/infiniband/sw/rxe/rxe_opcode.h
View File

@ -20,6 +20,7 @@ enum rxe_wr_mask {
WR_READ_MASK = BIT(3),
WR_WRITE_MASK = BIT(4),
WR_LOCAL_OP_MASK = BIT(5),
WR_FLUSH_MASK = BIT(6),
WR_ATOMIC_WRITE_MASK = BIT(7),
WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK,
@ -48,6 +49,7 @@ enum rxe_hdr_type {
RXE_RDETH,
RXE_DETH,
RXE_IMMDT,
RXE_FETH,
RXE_PAYLOAD,
NUM_HDR_TYPES
};
@ -64,6 +66,7 @@ enum rxe_hdr_mask {
RXE_IETH_MASK = BIT(RXE_IETH),
RXE_RDETH_MASK = BIT(RXE_RDETH),
RXE_DETH_MASK = BIT(RXE_DETH),
RXE_FETH_MASK = BIT(RXE_FETH),
RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD),
RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0),
@ -72,13 +75,14 @@ enum rxe_hdr_mask {
RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3),
RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4),
RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5),
RXE_FLUSH_MASK = BIT(NUM_HDR_TYPES + 6),
RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6),
RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7),
RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 7),
RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 8),
RXE_START_MASK = BIT(NUM_HDR_TYPES + 8),
RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9),
RXE_END_MASK = BIT(NUM_HDR_TYPES + 10),
RXE_START_MASK = BIT(NUM_HDR_TYPES + 9),
RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 10),
RXE_END_MASK = BIT(NUM_HDR_TYPES + 11),
RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12),