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gpio: xilinx: Switch to use bitmap APIs
It seems that Xilinx GPIO driver operates with bit arrays longer than 32 and thus can leverage bitmap APIs for that. It makes code better to understand. The ->probe() function is modified to try read properties for both channels since is_dual check makes only sense for the amount of pins used for the second channel. On top of that kzalloc() guarantees zero initial values for the fields in the private data structure, hence drop unneeded conditionals and assignments. The change is inspired by Syed Nayyar Waris' ideas about bitmap API extension. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Neeli Srinivas <sneeli@xilinx.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Andy Shevchenko
Bartosz Golaszewski
parent
043aa3db1c
commit
02b3f84d90
@ -5,6 +5,7 @@
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* Copyright 2008 - 2013 Xilinx, Inc.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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@ -44,40 +45,61 @@
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* struct xgpio_instance - Stores information about GPIO device
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* @gc: GPIO chip
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* @regs: register block
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* @gpio_width: GPIO width for every channel
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* @gpio_state: GPIO write state shadow register
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* @gpio_last_irq_read: GPIO read state register from last interrupt
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* @gpio_dir: GPIO direction shadow register
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* @hw_map: GPIO pin mapping on hardware side
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* @sw_map: GPIO pin mapping on software side
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* @state: GPIO write state shadow register
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* @last_irq_read: GPIO read state register from last interrupt
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* @dir: GPIO direction shadow register
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* @gpio_lock: Lock used for synchronization
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* @irq: IRQ used by GPIO device
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* @irqchip: IRQ chip
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* @irq_enable: GPIO IRQ enable/disable bitfield
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* @irq_rising_edge: GPIO IRQ rising edge enable/disable bitfield
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* @irq_falling_edge: GPIO IRQ falling edge enable/disable bitfield
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* @enable: GPIO IRQ enable/disable bitfield
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* @rising_edge: GPIO IRQ rising edge enable/disable bitfield
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* @falling_edge: GPIO IRQ falling edge enable/disable bitfield
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* @clk: clock resource for this driver
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*/
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struct xgpio_instance {
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struct gpio_chip gc;
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void __iomem *regs;
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unsigned int gpio_width[2];
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u32 gpio_state[2];
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u32 gpio_last_irq_read[2];
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u32 gpio_dir[2];
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DECLARE_BITMAP(hw_map, 64);
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DECLARE_BITMAP(sw_map, 64);
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DECLARE_BITMAP(state, 64);
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DECLARE_BITMAP(last_irq_read, 64);
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DECLARE_BITMAP(dir, 64);
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spinlock_t gpio_lock; /* For serializing operations */
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int irq;
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struct irq_chip irqchip;
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u32 irq_enable[2];
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u32 irq_rising_edge[2];
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u32 irq_falling_edge[2];
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DECLARE_BITMAP(enable, 64);
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DECLARE_BITMAP(rising_edge, 64);
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DECLARE_BITMAP(falling_edge, 64);
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struct clk *clk;
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};
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static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
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static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
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{
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if (gpio >= chip->gpio_width[0])
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return 1;
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return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
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}
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return 0;
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static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
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{
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return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
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}
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static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
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{
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const size_t index = BIT_WORD(bit);
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const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
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return (map[index] >> offset) & 0xFFFFFFFFul;
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}
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static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
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{
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const size_t index = BIT_WORD(bit);
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const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
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map[index] &= ~(0xFFFFFFFFul << offset);
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map[index] |= v << offset;
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}
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static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
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@ -92,22 +114,32 @@ static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
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}
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}
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static inline u32 xgpio_read_chan(struct xgpio_instance *chip, int reg, int ch)
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static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
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{
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return xgpio_readreg(chip->regs + reg + xgpio_regoffset(chip, ch));
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void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
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xgpio_set_value32(a, bit, xgpio_readreg(addr));
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}
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static inline void xgpio_write_chan(struct xgpio_instance *chip, int reg, int ch, u32 v)
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static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
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{
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xgpio_writereg(chip->regs + reg + xgpio_regoffset(chip, ch), v);
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void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
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xgpio_writereg(addr, xgpio_get_value32(a, bit));
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}
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static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
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static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
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{
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if (xgpio_index(chip, gpio))
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return gpio - chip->gpio_width[0];
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int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
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return gpio;
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for (bit = 0; bit <= lastbit ; bit += 32)
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xgpio_read_ch(chip, reg, bit, a);
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}
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static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
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{
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int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
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for (bit = 0; bit <= lastbit ; bit += 32)
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xgpio_write_ch(chip, reg, bit, a);
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}
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/**
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@ -124,13 +156,12 @@ static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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u32 val;
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int bit = xgpio_to_bit(chip, gpio);
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DECLARE_BITMAP(state, 64);
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val = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index);
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xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
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return !!(val & BIT(offset));
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return test_bit(bit, state);
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}
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/**
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@ -146,18 +177,14 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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int bit = xgpio_to_bit(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write to GPIO signal and set its direction to output */
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if (val)
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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__assign_bit(bit, chip->state, val);
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xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]);
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xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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@ -174,35 +201,22 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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DECLARE_BITMAP(hw_mask, 64);
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DECLARE_BITMAP(hw_bits, 64);
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DECLARE_BITMAP(state, 64);
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, 0);
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int offset, i;
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bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
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bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write to GPIO signals */
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for (i = 0; i < gc->ngpio; i++) {
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if (*mask == 0)
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break;
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/* Once finished with an index write it out to the register */
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if (index != xgpio_index(chip, i)) {
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xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index,
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chip->gpio_state[index]);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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index = xgpio_index(chip, i);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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}
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if (__test_and_clear_bit(i, mask)) {
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offset = xgpio_offset(chip, i);
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if (test_bit(i, bits))
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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}
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}
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bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
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xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]);
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xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
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bitmap_copy(chip->state, state, 64);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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@ -220,14 +234,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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int bit = xgpio_to_bit(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Set the GPIO bit in shadow register and set direction as input */
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chip->gpio_dir[index] |= BIT(offset);
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xgpio_write_chan(chip, XGPIO_TRI_OFFSET, index, chip->gpio_dir[index]);
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__set_bit(bit, chip->dir);
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xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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@ -250,21 +263,17 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int index = xgpio_index(chip, gpio);
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int offset = xgpio_offset(chip, gpio);
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int bit = xgpio_to_bit(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write state of GPIO signal */
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if (val)
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chip->gpio_state[index] |= BIT(offset);
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else
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chip->gpio_state[index] &= ~BIT(offset);
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xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]);
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__assign_bit(bit, chip->state, val);
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xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
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/* Clear the GPIO bit in shadow register and set direction as output */
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chip->gpio_dir[index] &= ~BIT(offset);
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xgpio_write_chan(chip, XGPIO_TRI_OFFSET, index, chip->gpio_dir[index]);
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__clear_bit(bit, chip->dir);
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xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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@ -277,14 +286,8 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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*/
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static void xgpio_save_regs(struct xgpio_instance *chip)
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{
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xgpio_write_chan(chip, XGPIO_DATA_OFFSET, 0, chip->gpio_state[0]);
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xgpio_write_chan(chip, XGPIO_TRI_OFFSET, 0, chip->gpio_dir[0]);
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if (!chip->gpio_width[1])
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return;
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xgpio_write_chan(chip, XGPIO_DATA_OFFSET, 1, chip->gpio_state[1]);
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xgpio_write_chan(chip, XGPIO_TRI_OFFSET, 1, chip->gpio_dir[1]);
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xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
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xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
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}
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static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
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@ -399,18 +402,17 @@ static void xgpio_irq_mask(struct irq_data *irq_data)
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unsigned long flags;
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
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int irq_offset = irqd_to_hwirq(irq_data);
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int index = xgpio_index(chip, irq_offset);
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int offset = xgpio_offset(chip, irq_offset);
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int bit = xgpio_to_bit(chip, irq_offset);
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u32 mask = BIT(bit / 32), temp;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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chip->irq_enable[index] &= ~BIT(offset);
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__clear_bit(bit, chip->enable);
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if (!chip->irq_enable[index]) {
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if (xgpio_get_value32(chip->enable, bit) == 0) {
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/* Disable per channel interrupt */
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u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
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temp &= ~BIT(index);
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temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
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temp &= ~mask;
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xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
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}
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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@ -425,29 +427,26 @@ static void xgpio_irq_unmask(struct irq_data *irq_data)
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unsigned long flags;
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
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int irq_offset = irqd_to_hwirq(irq_data);
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int index = xgpio_index(chip, irq_offset);
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int offset = xgpio_offset(chip, irq_offset);
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u32 old_enable = chip->irq_enable[index];
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int bit = xgpio_to_bit(chip, irq_offset);
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u32 old_enable = xgpio_get_value32(chip->enable, bit);
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u32 mask = BIT(bit / 32), val;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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chip->irq_enable[index] |= BIT(offset);
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__set_bit(bit, chip->enable);
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if (!old_enable) {
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if (old_enable == 0) {
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/* Clear any existing per-channel interrupts */
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u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) &
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BIT(index);
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if (val)
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xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
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val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
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val &= mask;
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xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
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/* Update GPIO IRQ read data before enabling interrupt*/
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val = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index);
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chip->gpio_last_irq_read[index] = val;
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xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
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/* Enable per channel interrupt */
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val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
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val |= BIT(index);
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val |= mask;
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xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
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}
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@ -466,8 +465,7 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
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{
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
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int irq_offset = irqd_to_hwirq(irq_data);
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int index = xgpio_index(chip, irq_offset);
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int offset = xgpio_offset(chip, irq_offset);
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int bit = xgpio_to_bit(chip, irq_offset);
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/*
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* The Xilinx GPIO hardware provides a single interrupt status
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@ -477,16 +475,16 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
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*/
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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chip->irq_rising_edge[index] |= BIT(offset);
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chip->irq_falling_edge[index] |= BIT(offset);
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__set_bit(bit, chip->rising_edge);
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__set_bit(bit, chip->falling_edge);
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break;
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case IRQ_TYPE_EDGE_RISING:
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chip->irq_rising_edge[index] |= BIT(offset);
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chip->irq_falling_edge[index] &= ~BIT(offset);
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__set_bit(bit, chip->rising_edge);
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__clear_bit(bit, chip->falling_edge);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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chip->irq_rising_edge[index] &= ~BIT(offset);
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chip->irq_falling_edge[index] |= BIT(offset);
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__clear_bit(bit, chip->rising_edge);
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__set_bit(bit, chip->falling_edge);
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break;
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default:
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return -EINVAL;
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@ -503,45 +501,45 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
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static void xgpio_irqhandler(struct irq_desc *desc)
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{
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struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
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struct gpio_chip *gc = &chip->gc;
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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u32 num_channels = chip->gpio_width[1] ? 2 : 1;
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u32 offset = 0, index;
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u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
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DECLARE_BITMAP(rising, 64);
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DECLARE_BITMAP(falling, 64);
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DECLARE_BITMAP(all, 64);
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int irq_offset;
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u32 status;
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u32 bit;
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unsigned long flags;
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status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
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xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
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||||
|
||||
chained_irq_enter(irqchip, desc);
|
||||
for (index = 0; index < num_channels; index++) {
|
||||
if ((status & BIT(index))) {
|
||||
unsigned long rising_events, falling_events, all_events;
|
||||
unsigned long flags;
|
||||
u32 data, bit;
|
||||
unsigned int irq;
|
||||
|
||||
spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
data = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index);
|
||||
rising_events = data &
|
||||
~chip->gpio_last_irq_read[index] &
|
||||
chip->irq_enable[index] &
|
||||
chip->irq_rising_edge[index];
|
||||
falling_events = ~data &
|
||||
chip->gpio_last_irq_read[index] &
|
||||
chip->irq_enable[index] &
|
||||
chip->irq_falling_edge[index];
|
||||
dev_dbg(chip->gc.parent,
|
||||
"IRQ chan %u rising 0x%lx falling 0x%lx\n",
|
||||
index, rising_events, falling_events);
|
||||
all_events = rising_events | falling_events;
|
||||
chip->gpio_last_irq_read[index] = data;
|
||||
spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
|
||||
for_each_set_bit(bit, &all_events, 32) {
|
||||
irq = irq_find_mapping(chip->gc.irq.domain,
|
||||
offset + bit);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
offset += chip->gpio_width[index];
|
||||
xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
|
||||
|
||||
bitmap_complement(rising, chip->last_irq_read, 64);
|
||||
bitmap_and(rising, rising, all, 64);
|
||||
bitmap_and(rising, rising, chip->enable, 64);
|
||||
bitmap_and(rising, rising, chip->rising_edge, 64);
|
||||
|
||||
bitmap_complement(falling, all, 64);
|
||||
bitmap_and(falling, falling, chip->last_irq_read, 64);
|
||||
bitmap_and(falling, falling, chip->enable, 64);
|
||||
bitmap_and(falling, falling, chip->falling_edge, 64);
|
||||
|
||||
bitmap_copy(chip->last_irq_read, all, 64);
|
||||
bitmap_or(all, rising, falling, 64);
|
||||
|
||||
spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
|
||||
dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
|
||||
|
||||
for_each_set_bit(bit, all, 64) {
|
||||
irq_offset = xgpio_from_bit(chip, bit);
|
||||
generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset));
|
||||
}
|
||||
|
||||
chained_irq_exit(irqchip, desc);
|
||||
@ -562,6 +560,9 @@ static int xgpio_probe(struct platform_device *pdev)
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
u32 is_dual = 0;
|
||||
u32 cells = 2;
|
||||
u32 width[2];
|
||||
u32 state[2];
|
||||
u32 dir[2];
|
||||
struct gpio_irq_chip *girq;
|
||||
u32 temp;
|
||||
|
||||
@ -571,13 +572,25 @@ static int xgpio_probe(struct platform_device *pdev)
|
||||
|
||||
platform_set_drvdata(pdev, chip);
|
||||
|
||||
/* First, check if the device is dual-channel */
|
||||
of_property_read_u32(np, "xlnx,is-dual", &is_dual);
|
||||
|
||||
/* Setup defaults */
|
||||
memset32(width, 0, ARRAY_SIZE(width));
|
||||
memset32(state, 0, ARRAY_SIZE(state));
|
||||
memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
|
||||
|
||||
/* Update GPIO state shadow register with default value */
|
||||
if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]))
|
||||
chip->gpio_state[0] = 0x0;
|
||||
of_property_read_u32(np, "xlnx,dout-default", &state[0]);
|
||||
of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
|
||||
|
||||
bitmap_from_arr32(chip->state, state, 64);
|
||||
|
||||
/* Update GPIO direction shadow register with default value */
|
||||
if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
|
||||
chip->gpio_dir[0] = 0xFFFFFFFF;
|
||||
of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
|
||||
of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
|
||||
|
||||
bitmap_from_arr32(chip->dir, dir, 64);
|
||||
|
||||
/* Update cells with gpio-cells value */
|
||||
if (of_property_read_u32(np, "#gpio-cells", &cells))
|
||||
@ -592,42 +605,29 @@ static int xgpio_probe(struct platform_device *pdev)
|
||||
* Check device node and parent device node for device width
|
||||
* and assume default width of 32
|
||||
*/
|
||||
if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
|
||||
chip->gpio_width[0] = 32;
|
||||
if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
|
||||
width[0] = 32;
|
||||
|
||||
if (chip->gpio_width[0] > 32)
|
||||
if (width[0] > 32)
|
||||
return -EINVAL;
|
||||
|
||||
if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
|
||||
width[1] = 32;
|
||||
|
||||
if (width[1] > 32)
|
||||
return -EINVAL;
|
||||
|
||||
/* Setup software pin mapping */
|
||||
bitmap_set(chip->sw_map, 0, width[0] + width[1]);
|
||||
|
||||
/* Setup hardware pin mapping */
|
||||
bitmap_set(chip->hw_map, 0, width[0]);
|
||||
bitmap_set(chip->hw_map, 32, width[1]);
|
||||
|
||||
spin_lock_init(&chip->gpio_lock);
|
||||
|
||||
if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
|
||||
is_dual = 0;
|
||||
|
||||
if (is_dual) {
|
||||
/* Update GPIO state shadow register with default value */
|
||||
if (of_property_read_u32(np, "xlnx,dout-default-2",
|
||||
&chip->gpio_state[1]))
|
||||
chip->gpio_state[1] = 0x0;
|
||||
|
||||
/* Update GPIO direction shadow register with default value */
|
||||
if (of_property_read_u32(np, "xlnx,tri-default-2",
|
||||
&chip->gpio_dir[1]))
|
||||
chip->gpio_dir[1] = 0xFFFFFFFF;
|
||||
|
||||
/*
|
||||
* Check device node and parent device node for device width
|
||||
* and assume default width of 32
|
||||
*/
|
||||
if (of_property_read_u32(np, "xlnx,gpio2-width",
|
||||
&chip->gpio_width[1]))
|
||||
chip->gpio_width[1] = 32;
|
||||
|
||||
if (chip->gpio_width[1] > 32)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
chip->gc.base = -1;
|
||||
chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
|
||||
chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
|
||||
chip->gc.parent = &pdev->dev;
|
||||
chip->gc.direction_input = xgpio_dir_in;
|
||||
chip->gc.direction_output = xgpio_dir_out;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user