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Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci

Browse Source 
* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (48 commits)
  Revert "rtc: omap: let device wakeup capability be configured from chip init logic"
  DM365: Added more PINMUX configurations for AEMIF
  DM365: Make CLKOUTx available
  DM365: Added PINMUX definitions for GPIO30..32
  Davinci: iotable based ioremap() interception
  Davinci: pinmux - use ioremap()
  Davinci: aintc/cpintc - use ioremap()
  Davinci: psc - use ioremap()
  Davinci: timer - use ioremap()
  Davinci: jtag_id - use ioremap()
  Davinci: da8xx: rtc - use ioremap
  Davinci: gpio - use ioremap()
  davinci: edma: fix coding style issue related to breaking lines
  davinci: edma: use BIT() wherever possible
  davinci: edma: fix coding style issue related to usage of braces
  davinci: edma: use a more intuitive name for edma_info
  Davinci: serial - conditional reset via pwremu
  Davinci: serial - use ioremap()
  Davinci: serial - remove unnecessary define
  Davinci: watchdog reset separation across socs
  ...

Fix up trivial conflict in arch/arm/Kconfig due to removal of "select
GENERIC_TIME"
This commit is contained in:
Linus Torvalds 2010-05-19 12:08:50 -07:00
commit 024a6b9518
50 changed files with 1814 additions and 665 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -760,7 +760,6 @@ config ARCH_NOMADIK
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select ZONE_DMA

2
arch/arm/mach-davinci/Kconfig
View File

@ -7,6 +7,7 @@ config CP_INTC
bool
config ARCH_DAVINCI_DMx
select CPU_ARM926T
bool
menu "TI DaVinci Implementations"
@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
select ARCH_HAS_CPUFREQ
config ARCH_DAVINCI_DA8XX
select CPU_ARM926T
bool
config ARCH_DAVINCI_DM365

52
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -33,9 +33,6 @@
#define DA830_EVM_PHY_MASK 0x0
#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000
#define DA830_EMIF25_CONTROL_BASE 0x68000000
/*
* USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
*/
@ -157,7 +154,7 @@ static __init void da830_evm_usb_init(void)
__func__, ret);
}
ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
if (ret) {
pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
__func__, ret);
@ -229,15 +226,22 @@ static const short da830_evm_mmc_sd_pins[] = {
};
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
static int da830_evm_mmc_get_ro(int index)
{
return gpio_get_value(DA830_MMCSD_WP_PIN);
}
static int da830_evm_mmc_get_cd(int index)
{
return !gpio_get_value(DA830_MMCSD_CD_PIN);
}
static struct davinci_mmc_config da830_evm_mmc_config = {
.get_ro = da830_evm_mmc_get_ro,
.wires = 4,
.get_cd = da830_evm_mmc_get_cd,
.wires = 8,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.version = MMC_CTLR_VERSION_2,
@ -247,7 +251,7 @@ static inline void da830_evm_init_mmc(void)
{
int ret;
ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
if (ret) {
pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
ret);
@ -262,6 +266,14 @@ static inline void da830_evm_init_mmc(void)
}
gpio_direction_input(DA830_MMCSD_WP_PIN);
ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
if (ret) {
pr_warning("da830_evm_init: can not open GPIO %d\n",
DA830_MMCSD_CD_PIN);
return;
}
gpio_direction_input(DA830_MMCSD_CD_PIN);
ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
if (ret) {
pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
@ -360,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
static struct resource da830_evm_nand_resources[] = {
[0] = { /* First memory resource is NAND I/O window */
.start = DA830_EMIF25_ASYNC_DATA_CE3_BASE,
.end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1,
.start = DA8XX_AEMIF_CS3_BASE,
.end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = { /* Second memory resource is AEMIF control registers */
.start = DA830_EMIF25_CONTROL_BASE,
.end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1,
.start = DA8XX_AEMIF_CTL_BASE,
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -392,7 +404,7 @@ static inline void da830_evm_init_nand(int mux_mode)
return;
}
ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
if (ret)
pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
ret);
@ -412,7 +424,7 @@ static inline void da830_evm_init_lcdc(int mux_mode)
{
int ret;
ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
if (ret)
pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
ret);
@ -492,7 +504,7 @@ static __init void da830_evm_init(void)
pr_warning("da830_evm_init: edma registration failed: %d\n",
ret);
ret = da8xx_pinmux_setup(da830_i2c0_pins);
ret = davinci_cfg_reg_list(da830_i2c0_pins);
if (ret)
pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
ret);
@ -508,7 +520,7 @@ static __init void da830_evm_init(void)
soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
soc_info->emac_pdata->rmii_en = 1;
ret = da8xx_pinmux_setup(da830_cpgmac_pins);
ret = davinci_cfg_reg_list(da830_cpgmac_pins);
if (ret)
pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
ret);
@ -527,7 +539,7 @@ static __init void da830_evm_init(void)
i2c_register_board_info(1, da830_evm_i2c_devices,
ARRAY_SIZE(da830_evm_i2c_devices));
ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
if (ret)
pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
ret);
@ -549,14 +561,6 @@ static int __init da830_evm_console_init(void)
console_initcall(da830_evm_console_init);
#endif
static __init void da830_evm_irq_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
soc_info->intc_irq_prios);
}
static void __init da830_evm_map_io(void)
{
da830_init();
@ -567,7 +571,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DA8XX_DDR_BASE + 0x100),
.map_io = da830_evm_map_io,
.init_irq = da830_evm_irq_init,
.init_irq = cp_intc_init,
.timer = &davinci_timer,
.init_machine = da830_evm_init,
MACHINE_END

28
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void)
int ret = 0;
if (ui_card_detected & !HAS_MMC) {
ret = da8xx_pinmux_setup(da850_nand_pins);
ret = davinci_cfg_reg_list(da850_nand_pins);
if (ret)
pr_warning("da850_evm_init: nand mux setup failed: "
"%d\n", ret);
ret = da8xx_pinmux_setup(da850_nor_pins);
ret = davinci_cfg_reg_list(da850_nor_pins);
if (ret)
pr_warning("da850_evm_init: nor mux setup failed: %d\n",
ret);
@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void)
if (rmii_en) {
val |= BIT(8);
ret = da8xx_pinmux_setup(da850_rmii_pins);
ret = davinci_cfg_reg_list(da850_rmii_pins);
pr_info("EMAC: RMII PHY configured, MII PHY will not be"
" functional\n");
} else {
val &= ~BIT(8);
ret = da8xx_pinmux_setup(da850_cpgmac_pins);
ret = davinci_cfg_reg_list(da850_cpgmac_pins);
pr_info("EMAC: MII PHY configured, RMII PHY will not be"
" functional\n");
}
@ -626,7 +626,7 @@ static __init void da850_evm_init(void)
pr_warning("da850_evm_init: edma registration failed: %d\n",
ret);
ret = da8xx_pinmux_setup(da850_i2c0_pins);
ret = davinci_cfg_reg_list(da850_i2c0_pins);
if (ret)
pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
ret);
@ -643,7 +643,7 @@ static __init void da850_evm_init(void)
ret);
if (HAS_MMC) {
ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
if (ret)
pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
" %d\n", ret);
@ -679,20 +679,20 @@ static __init void da850_evm_init(void)
__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
ret = da8xx_pinmux_setup(da850_mcasp_pins);
ret = davinci_cfg_reg_list(da850_mcasp_pins);
if (ret)
pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
ret);
da8xx_register_mcasp(0, &da850_evm_snd_data);
ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
if (ret)
pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
ret);
/* Handle board specific muxing for LCD here */
ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
if (ret)
pr_warning("da850_evm_init: evm specific lcd mux setup "
"failed: %d\n", ret);
@ -736,14 +736,6 @@ static int __init da850_evm_console_init(void)
console_initcall(da850_evm_console_init);
#endif
static __init void da850_evm_irq_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
soc_info->intc_irq_prios);
}
static void __init da850_evm_map_io(void)
{
da850_init();
@ -754,7 +746,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DA8XX_DDR_BASE + 0x100),
.map_io = da850_evm_map_io,
.init_irq = da850_evm_irq_init,
.init_irq = cp_intc_init,
.timer = &davinci_timer,
.init_machine = da850_evm_init,
MACHINE_END

18
arch/arm/mach-davinci/board-dm355-evm.c
View File

@ -33,9 +33,6 @@
#include <mach/mmc.h>
#include <mach/usb.h>
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
static struct resource davinci_nand_resources[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM355_ASYNC_EMIF_CONTROL_BASE,
.end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -353,17 +350,12 @@ static __init void dm355_evm_init(void)
dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data);
}
static __init void dm355_evm_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = dm355_evm_map_io,
.init_irq = dm355_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = dm355_evm_init,
MACHINE_END

18
arch/arm/mach-davinci/board-dm355-leopard.c
View File

@ -30,9 +30,6 @@
#include <mach/mmc.h>
#include <mach/usb.h>
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
static struct resource davinci_nand_resources[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM355_ASYNC_EMIF_CONTROL_BASE,
.end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -272,17 +269,12 @@ static __init void dm355_leopard_init(void)
ARRAY_SIZE(dm355_leopard_spi_info));
}
static __init void dm355_leopard_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = dm355_leopard_map_io,
.init_irq = dm355_leopard_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = dm355_leopard_init,
MACHINE_END

12
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -54,11 +54,6 @@ static inline int have_tvp7002(void)
return 0;
}
#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DM365_EVM_PHY_MASK (0x2)
#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
@ -613,17 +608,12 @@ static __init void dm365_evm_init(void)
ARRAY_SIZE(dm365_evm_spi_info));
}
static __init void dm365_evm_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = dm365_evm_map_io,
.init_irq = dm365_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = dm365_evm_init,
MACHINE_END

60
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -41,14 +41,6 @@
#define DM644X_EVM_PHY_MASK (0x2)
#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
#define DAVINCI_CFC_ATA_BASE 0x01C66000
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
@ -92,8 +84,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = {
/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
* limits addresses to 16M, so using addresses past 16M will wrap */
static struct resource davinci_evm_norflash_resource = {
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
};
@ -111,7 +103,7 @@ static struct platform_device davinci_evm_norflash_device = {
* It may used instead of the (default) NOR chip to boot, using TI's
* tools to install the secondary boot loader (UBL) and U-Boot.
*/
struct mtd_partition davinci_evm_nandflash_partition[] = {
static struct mtd_partition davinci_evm_nandflash_partition[] = {
/* Bootloader layout depends on whose u-boot is installed, but we
* can hide all the details.
* - block 0 for u-boot environment ... in mainline u-boot
@ -154,12 +146,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
static struct resource davinci_evm_nandflash_resource[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -258,32 +250,6 @@ static struct platform_device rtc_dev = {
.id = -1,
};
static struct resource ide_resources[] = {
{
.start = DAVINCI_CFC_ATA_BASE,
.end = DAVINCI_CFC_ATA_BASE + 0x7ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IDE,
.end = IRQ_IDE,
.flags = IORESOURCE_IRQ,
},
};
static u64 ide_dma_mask = DMA_BIT_MASK(32);
static struct platform_device ide_dev = {
.name = "palm_bk3710",
.id = -1,
.resource = ide_resources,
.num_resources = ARRAY_SIZE(ide_resources),
.dev = {
.dma_mask = &ide_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct snd_platform_data dm644x_evm_snd_data;
/*----------------------------------------------------------------------*/
@ -704,10 +670,7 @@ static __init void davinci_evm_init(void)
pr_warning("WARNING: both IDE and Flash are "
"enabled, but they share AEMIF pins.\n"
"\tDisable IDE for NAND/NOR support.\n");
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN);
davinci_cfg_reg(DM644X_HDIREN);
platform_device_register(&ide_dev);
davinci_init_ide();
} else if (HAS_NAND || HAS_NOR) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
@ -741,18 +704,13 @@ static __init void davinci_evm_init(void)
}
static __init void davinci_evm_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
/* Maintainer: MontaVista Software <source@mvista.com> */
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DAVINCI_DDR_BASE + 0x100),
.map_io = davinci_evm_map_io,
.init_irq = davinci_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = davinci_evm_init,
MACHINE_END

22
arch/arm/mach-davinci/board-dm646x-evm.c
View File

@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = {
.options = 0,
};
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
static struct resource davinci_nand_resources[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
.end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -736,17 +733,12 @@ static __init void evm_init(void)
platform_device_register(&davinci_nand_device);
if (HAS_ATA)
dm646x_init_ide();
davinci_init_ide();
soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
}
static __init void davinci_dm646x_evm_irq_init(void)
{
davinci_irq_init();
}
#define DM646X_EVM_REF_FREQ 27000000
#define DM6467T_EVM_REF_FREQ 33000000
@ -763,7 +755,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = davinci_map_io,
.init_irq = davinci_dm646x_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = evm_init,
MACHINE_END
@ -773,7 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = davinci_map_io,
.init_irq = davinci_dm646x_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = evm_init,
MACHINE_END

54
arch/arm/mach-davinci/board-neuros-osd2.c
View File

@ -31,6 +31,7 @@
#include <asm/mach/arch.h>
#include <mach/dm644x.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mux.h>
@ -41,11 +42,6 @@
#define NEUROS_OSD2_PHY_MASK 0x2
#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
#define DAVINCI_CFC_ATA_BASE 0x01C66000
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
@ -60,7 +56,7 @@
#define NAND_BLOCK_SIZE SZ_128K
struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
{
/* UBL (a few copies) plus U-Boot */
.name = "bootloader",
@ -98,12 +94,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
static struct resource davinci_ntosd2_nandflash_resource[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -130,32 +126,6 @@ static struct platform_device davinci_fb_device = {
.num_resources = 0,
};
static struct resource ide_resources[] = {
{
.start = DAVINCI_CFC_ATA_BASE,
.end = DAVINCI_CFC_ATA_BASE + 0x7ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IDE,
.end = IRQ_IDE,
.flags = IORESOURCE_IRQ,
},
};
static u64 ide_dma_mask = DMA_BIT_MASK(32);
static struct platform_device ide_dev = {
.name = "palm_bk3710",
.id = -1,
.resource = ide_resources,
.num_resources = ARRAY_SIZE(ide_resources),
.dev = {
.dma_mask = &ide_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct snd_platform_data dm644x_ntosd2_snd_data;
static struct gpio_led ntosd2_leds[] = {
@ -259,10 +229,7 @@ static __init void davinci_ntosd2_init(void)
pr_warning("WARNING: both IDE and Flash are "
"enabled, but they share AEMIF pins.\n"
"\tDisable IDE for NAND/NOR support.\n");
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN);
davinci_cfg_reg(DM644X_HDIREN);
platform_device_register(&ide_dev);
davinci_init_ide();
} else if (HAS_NAND) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
@ -306,18 +273,13 @@ static __init void davinci_ntosd2_init(void)
davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
}
static __init void davinci_ntosd2_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
/* Maintainer: Neuros Technologies <neuros@groups.google.com> */
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DAVINCI_DDR_BASE + 0x100),
.map_io = davinci_ntosd2_map_io,
.init_irq = davinci_ntosd2_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = davinci_ntosd2_init,
MACHINE_END

20
arch/arm/mach-davinci/board-sffsdr.c
View File

@ -45,10 +45,7 @@
#define SFFSDR_PHY_MASK (0x2)
#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
* UBL: Block 1
* U-Boot: Blocks 6-7 (256 kb)
@ -76,12 +73,12 @@ static struct flash_platform_data davinci_sffsdr_nandflash_data = {
static struct resource davinci_sffsdr_nandflash_resource[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
@ -155,18 +152,13 @@ static __init void davinci_sffsdr_init(void)
davinci_cfg_reg(DM644X_VLYNQWD);
}
static __init void davinci_sffsdr_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
/* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DAVINCI_DDR_BASE + 0x100),
.map_io = davinci_sffsdr_map_io,
.init_irq = davinci_sffsdr_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = davinci_sffsdr_init,
MACHINE_END

1
arch/arm/mach-davinci/cdce949.c
View File

@ -19,6 +19,7 @@
#include <linux/i2c.h>
#include <mach/clock.h>
#include <mach/cdce949.h>
#include "clock.h"

32
arch/arm/mach-davinci/clock.c
View File

@ -22,6 +22,7 @@
#include <mach/hardware.h>
#include <mach/clock.h>
#include <mach/psc.h>
#include <mach/cputype.h>
#include "clock.h"
@ -42,7 +43,8 @@ static void __clk_enable(struct clk *clk)
if (clk->parent)
__clk_enable(clk->parent);
if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
PSC_STATE_ENABLE);
}
static void __clk_disable(struct clk *clk)
@ -51,7 +53,9 @@ static void __clk_disable(struct clk *clk)
return;
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
(clk->flags & CLK_PSC))
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
(clk->flags & PSC_SWRSTDISABLE) ?
PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
if (clk->parent)
__clk_disable(clk->parent);
}
@ -233,7 +237,10 @@ static int __init clk_disable_unused(void)
continue;
pr_info("Clocks: disable unused %s\n", ck->name);
davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
(ck->flags & PSC_SWRSTDISABLE) ?
PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
}
spin_unlock_irq(&clockfw_lock);
@ -272,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
v = __raw_readl(pll->base + clk->div_reg);
if (v & PLLDIV_EN) {
plldiv = (v & PLLDIV_RATIO_MASK) + 1;
plldiv = (v & pll->div_ratio_mask) + 1;
if (plldiv)
rate /= plldiv;
}
@ -295,7 +302,6 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
struct pll_data *pll = clk->pll_data;
unsigned long rate = clk->rate;
pll->base = IO_ADDRESS(pll->phys_base);
ctrl = __raw_readl(pll->base + PLLCTL);
rate = pll->input_rate = clk->parent->rate;
@ -312,7 +318,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
if (pll->flags & PLL_HAS_PREDIV) {
prediv = __raw_readl(pll->base + PREDIV);
if (prediv & PLLDIV_EN)
prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
prediv = (prediv & pll->div_ratio_mask) + 1;
else
prediv = 1;
}
@ -324,7 +330,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
if (pll->flags & PLL_HAS_POSTDIV) {
postdiv = __raw_readl(pll->base + POSTDIV);
if (postdiv & PLLDIV_EN)
postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
postdiv = (postdiv & pll->div_ratio_mask) + 1;
else
postdiv = 1;
}
@ -451,6 +457,18 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
clk->recalc = clk_leafclk_recalc;
}
if (clk->pll_data) {
struct pll_data *pll = clk->pll_data;
if (!pll->div_ratio_mask)
pll->div_ratio_mask = PLLDIV_RATIO_MASK;
if (pll->phys_base && !pll->base) {
pll->base = ioremap(pll->phys_base, SZ_4K);
WARN_ON(!pll->base);
}
}
if (clk->recalc)
clk->rate = clk->recalc(clk);

9
arch/arm/mach-davinci/clock.h
View File

@ -76,6 +76,7 @@ struct pll_data {
u32 num;
u32 flags;
u32 input_rate;
u32 div_ratio_mask;
};
#define PLL_HAS_PREDIV 0x01
#define PLL_HAS_POSTDIV 0x02
@ -101,10 +102,11 @@ struct clk {
/* Clock flags: SoC-specific flags start at BIT(16) */
#define ALWAYS_ENABLED BIT(1)
#define CLK_PSC BIT(2)
#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
#define CLK_PSC BIT(2)
#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
#define CLK_PLL BIT(4) /* PLL-derived clock */
#define PRE_PLL BIT(5) /* source is before PLL mult/div */
#define PRE_PLL BIT(5) /* source is before PLL mult/div */
#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
#define CLK(dev, con, ck) \
{ \
@ -118,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv);
extern struct platform_device davinci_wdt_device;
extern void davinci_watchdog_reset(struct platform_device *);
#endif

55
arch/arm/mach-davinci/common.c
View File

@ -37,26 +37,43 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
}
static struct davinci_id * __init davinci_get_id(u32 jtag_id)
static int __init davinci_init_id(struct davinci_soc_info *soc_info)
{
int i;
struct davinci_id *dip;
u8 variant = (jtag_id & 0xf0000000) >> 28;
u16 part_no = (jtag_id & 0x0ffff000) >> 12;
int i;
struct davinci_id *dip;
u8 variant;
u16 part_no;
void __iomem *base;
for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num;
base = ioremap(soc_info->jtag_id_reg, SZ_4K);
if (!base) {
pr_err("Unable to map JTAG ID register\n");
return -ENOMEM;
}
soc_info->jtag_id = __raw_readl(base);
iounmap(base);
variant = (soc_info->jtag_id & 0xf0000000) >> 28;
part_no = (soc_info->jtag_id & 0x0ffff000) >> 12;
for (i = 0, dip = soc_info->ids; i < soc_info->ids_num;
i++, dip++)
/* Don't care about the manufacturer right now */
if ((dip->part_no == part_no) && (dip->variant == variant))
return dip;
if ((dip->part_no == part_no) && (dip->variant == variant)) {
soc_info->cpu_id = dip->cpu_id;
pr_info("DaVinci %s variant 0x%x\n", dip->name,
dip->variant);
return 0;
}
return NULL;
pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id);
return -EINVAL;
}
void __init davinci_common_init(struct davinci_soc_info *soc_info)
{
int ret;
struct davinci_id *dip;
if (!soc_info) {
ret = -EINVAL;
@ -77,22 +94,16 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
local_flush_tlb_all();
flush_cache_all();
if (!davinci_soc_info.reset)
davinci_soc_info.reset = davinci_watchdog_reset;
/*
* We want to check CPU revision early for cpu_is_xxxx() macros.
* IO space mapping must be initialized before we can do that.
*/
davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base);
dip = davinci_get_id(davinci_soc_info.jtag_id);
if (!dip) {
ret = -EINVAL;
pr_err("Unknown DaVinci JTAG ID 0x%x\n",
davinci_soc_info.jtag_id);
ret = davinci_init_id(&davinci_soc_info);
if (ret < 0)
goto err;
}
davinci_soc_info.cpu_id = dip->cpu_id;
pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
if (davinci_soc_info.cpu_clks) {
ret = davinci_clk_init(davinci_soc_info.cpu_clks);
@ -101,8 +112,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
goto err;
}
davinci_intc_base = davinci_soc_info.intc_base;
davinci_intc_type = davinci_soc_info.intc_type;
return;
err:

22
arch/arm/mach-davinci/cp_intc.c
View File

@ -13,18 +13,17 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
static void __iomem *cp_intc_base;
static inline unsigned int cp_intc_read(unsigned offset)
{
return __raw_readl(cp_intc_base + offset);
return __raw_readl(davinci_intc_base + offset);
}
static inline void cp_intc_write(unsigned long value, unsigned offset)
{
__raw_writel(value, cp_intc_base + offset);
__raw_writel(value, davinci_intc_base + offset);
}
static void cp_intc_ack_irq(unsigned int irq)
@ -100,13 +99,18 @@ static struct irq_chip cp_intc_irq_chip = {
.set_wake = cp_intc_set_wake,
};
void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
u8 *irq_prio)
void __init cp_intc_init(void)
{
unsigned long num_irq = davinci_soc_info.intc_irq_num;
u8 *irq_prio = davinci_soc_info.intc_irq_prios;
u32 *host_map = davinci_soc_info.intc_host_map;
unsigned num_reg = BITS_TO_LONGS(num_irq);
int i;
cp_intc_base = base;
davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
if (WARN_ON(!davinci_intc_base))
return;
cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
@ -157,6 +161,10 @@ void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
}
if (host_map)
for (i = 0; host_map[i] != -1; i++)
cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
/* Set up genirq dispatching for cp_intc */
for (i = 0; i < num_irq; i++) {
set_irq_chip(i, &cp_intc_irq_chip);

29
arch/arm/mach-davinci/da830.c
View File

@ -19,6 +19,7 @@
#include <mach/common.h>
#include <mach/time.h>
#include <mach/da8xx.h>
#include <mach/gpio.h>
#include "clock.h"
#include "mux.h"
@ -1126,10 +1127,7 @@ static struct map_desc da830_io_desc[] = {
},
};
static void __iomem *da830_psc_bases[] = {
IO_ADDRESS(DA8XX_PSC0_BASE),
IO_ADDRESS(DA8XX_PSC1_BASE),
};
static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id da830_ids[] = {
@ -1158,14 +1156,14 @@ static struct davinci_id da830_ids[] = {
static struct davinci_timer_instance da830_timer_instance[2] = {
{
.base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_0,
.top_irq = IRQ_DA8XX_TINT34_0,
.cmp_off = DA830_CMP12_0,
.cmp_irq = IRQ_DA830_T12CMPINT0_0,
},
{
.base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_1,
.top_irq = IRQ_DA8XX_TINT34_1,
.cmp_off = DA830_CMP12_0,
@ -1187,34 +1185,33 @@ static struct davinci_timer_info da830_timer_info = {
static struct davinci_soc_info davinci_soc_info_da830 = {
.io_desc = da830_io_desc,
.io_desc_num = ARRAY_SIZE(da830_io_desc),
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da830_ids,
.ids_num = ARRAY_SIZE(da830_ids),
.cpu_clks = da830_clks,
.psc_bases = da830_psc_bases,
.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da830_pins,
.pinmux_pins_num = ARRAY_SIZE(da830_pins),
.intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
.intc_base = DA8XX_CP_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_CP_INTC,
.intc_irq_prios = da830_default_priorities,
.intc_irq_num = DA830_N_CP_INTC_IRQ,
.timer_info = &da830_timer_info,
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
.gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = DA8XX_GPIO_BASE,
.gpio_num = 128,
.gpio_irq = IRQ_DA8XX_GPIO0,
.serial_dev = &da8xx_serial_device,
.emac_pdata = &da8xx_emac_pdata,
.reset_device = &da8xx_wdt_device,
};
void __init da830_init(void)
{
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
return;
davinci_soc_info_da830.jtag_id_base =
DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
davinci_common_init(&davinci_soc_info_da830);
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
}

30
arch/arm/mach-davinci/da850.c
View File

@ -27,6 +27,7 @@
#include <mach/da8xx.h>
#include <mach/cpufreq.h>
#include <mach/pm.h>
#include <mach/gpio.h>
#include "clock.h"
#include "mux.h"
@ -781,10 +782,7 @@ static struct map_desc da850_io_desc[] = {
},
};
static void __iomem *da850_psc_bases[] = {
IO_ADDRESS(DA8XX_PSC0_BASE),
IO_ADDRESS(DA8XX_PSC1_BASE),
};
static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id da850_ids[] = {
@ -799,22 +797,22 @@ static struct davinci_id da850_ids[] = {
static struct davinci_timer_instance da850_timer_instance[4] = {
{
.base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_0,
.top_irq = IRQ_DA8XX_TINT34_0,
},
{
.base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_1,
.top_irq = IRQ_DA8XX_TINT34_1,
},
{
.base = IO_ADDRESS(DA850_TIMER64P2_BASE),
.base = DA850_TIMER64P2_BASE,
.bottom_irq = IRQ_DA850_TINT12_2,
.top_irq = IRQ_DA850_TINT34_2,
},
{
.base = IO_ADDRESS(DA850_TIMER64P3_BASE),
.base = DA850_TIMER64P3_BASE,
.bottom_irq = IRQ_DA850_TINT12_3,
.top_irq = IRQ_DA850_TINT34_3,
},
@ -1072,31 +1070,37 @@ no_ddrpll_mem:
static struct davinci_soc_info davinci_soc_info_da850 = {
.io_desc = da850_io_desc,
.io_desc_num = ARRAY_SIZE(da850_io_desc),
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da850_ids,
.ids_num = ARRAY_SIZE(da850_ids),
.cpu_clks = da850_clks,
.psc_bases = da850_psc_bases,
.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
.intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
.intc_base = DA8XX_CP_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_CP_INTC,
.intc_irq_prios = da850_default_priorities,
.intc_irq_num = DA850_N_CP_INTC_IRQ,
.timer_info = &da850_timer_info,
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
.gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = DA8XX_GPIO_BASE,
.gpio_num = 144,
.gpio_irq = IRQ_DA8XX_GPIO0,
.serial_dev = &da8xx_serial_device,
.emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_ARM_RAM_BASE,
.sram_len = SZ_8K,
.reset_device = &da8xx_wdt_device,
};
void __init da850_init(void)
{
unsigned int v;
davinci_common_init(&davinci_soc_info_da850);
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
return;
@ -1105,12 +1109,6 @@ void __init da850_init(void)
if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
return;
davinci_soc_info_da850.jtag_id_base =
DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
davinci_common_init(&davinci_soc_info_da850);
/*
* Move the clock source of Async3 domain to PLL1 SYSCLK2.
* This helps keeping the peripherals on this domain insulated

15
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -326,7 +326,7 @@ static struct resource da8xx_watchdog_resources[] = {
},
};
struct platform_device davinci_wdt_device = {
struct platform_device da8xx_wdt_device = {
.name = "watchdog",
.id = -1,
.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
@ -335,7 +335,7 @@ struct platform_device davinci_wdt_device = {
int __init da8xx_register_watchdog(void)
{
return platform_device_register(&davinci_wdt_device);
return platform_device_register(&da8xx_wdt_device);
}
static struct resource da8xx_emac_resources[] = {
@ -584,10 +584,17 @@ static struct platform_device da8xx_rtc_device = {
int da8xx_register_rtc(void)
{
int ret;
void __iomem *base;
base = ioremap(DA8XX_RTC_BASE, SZ_4K);
if (WARN_ON(!base))
return -ENOMEM;
/* Unlock the rtc's registers */
__raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
__raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
__raw_writel(0x83e70b13, base + 0x6c);
__raw_writel(0x95a4f1e0, base + 0x70);
iounmap(base);
ret = platform_device_register(&da8xx_rtc_device);
if (!ret)

50
arch/arm/mach-davinci/devices.c
View File

@ -23,7 +23,10 @@
#include <mach/mmc.h>
#include <mach/time.h>
#include "clock.h"
#define DAVINCI_I2C_BASE 0x01C21000
#define DAVINCI_ATA_BASE 0x01C66000
#define DAVINCI_MMCSD0_BASE 0x01E10000
#define DM355_MMCSD0_BASE 0x01E11000
#define DM355_MMCSD1_BASE 0x01E00000
@ -58,6 +61,49 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
(void) platform_device_register(&davinci_i2c_device);
}
static struct resource ide_resources[] = {
{
.start = DAVINCI_ATA_BASE,
.end = DAVINCI_ATA_BASE + 0x7ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IDE,
.end = IRQ_IDE,
.flags = IORESOURCE_IRQ,
},
};
static u64 ide_dma_mask = DMA_BIT_MASK(32);
static struct platform_device ide_device = {
.name = "palm_bk3710",
.id = -1,
.resource = ide_resources,
.num_resources = ARRAY_SIZE(ide_resources),
.dev = {
.dma_mask = &ide_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init davinci_init_ide(void)
{
if (cpu_is_davinci_dm644x()) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN);
davinci_cfg_reg(DM644X_HDIREN);
} else if (cpu_is_davinci_dm646x()) {
/* IRQ_DM646X_IDE is the same as IRQ_IDE */
davinci_cfg_reg(DM646X_ATAEN);
} else {
WARN_ON(1);
return;
}
platform_device_register(&ide_device);
}
#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
@ -251,12 +297,12 @@ static void davinci_init_wdt(void)
struct davinci_timer_instance davinci_timer_instance[2] = {
{
.base = IO_ADDRESS(DAVINCI_TIMER0_BASE),
.base = DAVINCI_TIMER0_BASE,
.bottom_irq = IRQ_TINT0_TINT12,
.top_irq = IRQ_TINT0_TINT34,
},
{
.base = IO_ADDRESS(DAVINCI_TIMER1_BASE),
.base = DAVINCI_TIMER1_BASE,
.bottom_irq = IRQ_TINT1_TINT12,
.top_irq = IRQ_TINT1_TINT34,
},

21
arch/arm/mach-davinci/dm355.c
View File

@ -450,11 +450,6 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
/*----------------------------------------------------------------------*/
#define PINMUX0 0x00
#define PINMUX1 0x04
#define PINMUX2 0x08
#define PINMUX3 0x0c
#define PINMUX4 0x10
#define INTMUX 0x18
#define EVTMUX 0x1c
@ -788,9 +783,7 @@ static struct davinci_id dm355_ids[] = {
},
};
static void __iomem *dm355_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@ -798,7 +791,7 @@ static void __iomem *dm355_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
struct davinci_timer_info dm355_timer_info = {
static struct davinci_timer_info dm355_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
@ -845,26 +838,28 @@ static struct platform_device dm355_serial_device = {
static struct davinci_soc_info davinci_soc_info_dm355 = {
.io_desc = dm355_io_desc,
.io_desc_num = ARRAY_SIZE(dm355_io_desc),
.jtag_id_base = IO_ADDRESS(0x01c40028),
.jtag_id_reg = 0x01c40028,
.ids = dm355_ids,
.ids_num = ARRAY_SIZE(dm355_ids),
.cpu_clks = dm355_clks,
.psc_bases = dm355_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm355_pins,
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm355_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm355_timer_info,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = DAVINCI_GPIO_BASE,
.gpio_num = 104,
.gpio_irq = IRQ_DM355_GPIOBNK0,
.serial_dev = &dm355_serial_device,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
};
void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)

34
arch/arm/mach-davinci/dm365.c
View File

@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = {
/*----------------------------------------------------------------------*/
#define PINMUX0 0x00
#define PINMUX1 0x04
#define PINMUX2 0x08
#define PINMUX3 0x0c
#define PINMUX4 0x10
#define INTMUX 0x18
#define EVTMUX 0x1c
@ -490,11 +485,14 @@ MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false)
MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
@ -573,9 +571,17 @@ MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
@ -1006,11 +1012,9 @@ static struct davinci_id dm365_ids[] = {
},
};
static void __iomem *dm365_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
struct davinci_timer_info dm365_timer_info = {
static struct davinci_timer_info dm365_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
@ -1049,21 +1053,22 @@ static struct platform_device dm365_serial_device = {
static struct davinci_soc_info davinci_soc_info_dm365 = {
.io_desc = dm365_io_desc,
.io_desc_num = ARRAY_SIZE(dm365_io_desc),
.jtag_id_base = IO_ADDRESS(0x01c40028),
.jtag_id_reg = 0x01c40028,
.ids = dm365_ids,
.ids_num = ARRAY_SIZE(dm365_ids),
.cpu_clks = dm365_clks,
.psc_bases = dm365_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm365_pins,
.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm365_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm365_timer_info,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = DAVINCI_GPIO_BASE,
.gpio_num = 104,
.gpio_irq = IRQ_DM365_GPIO0,
.gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
@ -1071,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
.emac_pdata = &dm365_emac_pdata,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
};
void __init dm365_init_asp(struct snd_platform_data *pdata)

21
arch/arm/mach-davinci/dm644x.c
View File

@ -277,7 +277,7 @@ static struct clk timer2_clk = {
.usecount = 1, /* REVISIT: why cant' this be disabled? */
};
struct clk_lookup dm644x_clks[] = {
static struct clk_lookup dm644x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll1", &pll1_clk),
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@ -350,9 +350,6 @@ static struct platform_device dm644x_emac_device = {
.resource = dm644x_emac_resources,
};
#define PINMUX0 0x00
#define PINMUX1 0x04
/*
* Device specific mux setup
*
@ -677,9 +674,7 @@ static struct davinci_id dm644x_ids[] = {
},
};
static void __iomem *dm644x_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@ -687,7 +682,7 @@ static void __iomem *dm644x_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
struct davinci_timer_info dm644x_timer_info = {
static struct davinci_timer_info dm644x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
@ -734,27 +729,29 @@ static struct platform_device dm644x_serial_device = {
static struct davinci_soc_info davinci_soc_info_dm644x = {
.io_desc = dm644x_io_desc,
.io_desc_num = ARRAY_SIZE(dm644x_io_desc),
.jtag_id_base = IO_ADDRESS(0x01c40028),
.jtag_id_reg = 0x01c40028,
.ids = dm644x_ids,
.ids_num = ARRAY_SIZE(dm644x_ids),
.cpu_clks = dm644x_clks,
.psc_bases = dm644x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm644x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm644x_timer_info,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = DAVINCI_GPIO_BASE,
.gpio_num = 71,
.gpio_irq = IRQ_GPIOBNK0,
.serial_dev = &dm644x_serial_device,
.emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000,
.sram_len = SZ_16K,
.reset_device = &davinci_wdt_device,
};
void __init dm644x_init_asp(struct snd_platform_data *pdata)

53
arch/arm/mach-davinci/dm646x.c
View File

@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
struct clk_lookup dm646x_clks[] = {
static struct clk_lookup dm646x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "aux", &aux_clkin),
CLK(NULL, "pll1", &pll1_clk),
@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = {
.resource = dm646x_emac_resources,
};
#define PINMUX0 0x00
#define PINMUX1 0x04
/*
* Device specific mux setup
*
@ -596,32 +593,6 @@ static struct platform_device dm646x_edma_device = {
.resource = edma_resources,
};
static struct resource ide_resources[] = {
{
.start = DM646X_ATA_REG_BASE,
.end = DM646X_ATA_REG_BASE + 0x7ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DM646X_IDE,
.end = IRQ_DM646X_IDE,
.flags = IORESOURCE_IRQ,
},
};
static u64 ide_dma_mask = DMA_BIT_MASK(32);
static struct platform_device ide_dev = {
.name = "palm_bk3710",
.id = -1,
.resource = ide_resources,
.num_resources = ARRAY_SIZE(ide_resources),
.dev = {
.dma_mask = &ide_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource dm646x_mcasp0_resources[] = {
{
.name = "mcasp0",
@ -787,9 +758,7 @@ static struct davinci_id dm646x_ids[] = {
},
};
static void __iomem *dm646x_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
@ -797,7 +766,7 @@ static void __iomem *dm646x_psc_bases[] = {
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
struct davinci_timer_info dm646x_timer_info = {
static struct davinci_timer_info dm646x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
@ -844,35 +813,31 @@ static struct platform_device dm646x_serial_device = {
static struct davinci_soc_info davinci_soc_info_dm646x = {
.io_desc = dm646x_io_desc,
.io_desc_num = ARRAY_SIZE(dm646x_io_desc),
.jtag_id_base = IO_ADDRESS(0x01c40028),
.jtag_id_reg = 0x01c40028,
.ids = dm646x_ids,
.ids_num = ARRAY_SIZE(dm646x_ids),
.cpu_clks = dm646x_clks,
.psc_bases = dm646x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm646x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm646x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm646x_timer_info,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = DAVINCI_GPIO_BASE,
.gpio_num = 43, /* Only 33 usable */
.gpio_irq = IRQ_DM646X_GPIOBNK0,
.serial_dev = &dm646x_serial_device,
.emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000,
.sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
};
void __init dm646x_init_ide()
{
davinci_cfg_reg(DM646X_ATAEN);
platform_device_register(&ide_dev);
}
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
{
dm646x_mcasp0_device.dev.platform_data = pdata;

234
arch/arm/mach-davinci/dma.c
View File

@ -243,7 +243,7 @@ struct edma {
} intr_data[EDMA_MAX_DMACH];
};
static struct edma *edma_info[EDMA_MAX_CC];
static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
/* dummy param set used to (re)initialize parameter RAM slots */
@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
/* default to low priority queue */
if (queue_no == EVENTQ_DEFAULT)
queue_no = edma_info[ctlr]->default_queue;
queue_no = edma_cc[ctlr]->default_queue;
queue_no &= 7;
edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
@ -310,29 +310,27 @@ setup_dma_interrupt(unsigned lch,
ctlr = EDMA_CTLR(lch);
lch = EDMA_CHAN_SLOT(lch);
if (!callback) {
if (!callback)
edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
(1 << (lch & 0x1f)));
}
BIT(lch & 0x1f));
edma_info[ctlr]->intr_data[lch].callback = callback;
edma_info[ctlr]->intr_data[lch].data = data;
edma_cc[ctlr]->intr_data[lch].callback = callback;
edma_cc[ctlr]->intr_data[lch].data = data;
if (callback) {
edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
(1 << (lch & 0x1f)));
BIT(lch & 0x1f));
edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
(1 << (lch & 0x1f)));
BIT(lch & 0x1f));
}
}
static int irq2ctlr(int irq)
{
if (irq >= edma_info[0]->irq_res_start &&
irq <= edma_info[0]->irq_res_end)
if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
return 0;
else if (irq >= edma_info[1]->irq_res_start &&
irq <= edma_info[1]->irq_res_end)
else if (irq >= edma_cc[1]->irq_res_start &&
irq <= edma_cc[1]->irq_res_end)
return 1;
return -1;
@ -353,15 +351,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
dev_dbg(data, "dma_irq_handler\n");
if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
&& (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
return IRQ_NONE;
while (1) {
int j;
if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
edma_shadow0_read_array(ctlr, SH_IER, 0))
j = 0;
else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
edma_shadow0_read_array(ctlr, SH_IER, 1))
j = 1;
else
break;
@ -369,17 +369,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
edma_shadow0_read_array(ctlr, SH_IPR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
(1 << i)) {
if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
&& (edma_shadow0_read_array(ctlr,
SH_IER, j) & BIT(i))) {
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1 << i));
if (edma_info[ctlr]->intr_data[k].callback) {
edma_info[ctlr]->intr_data[k].callback(
BIT(i));
if (edma_cc[ctlr]->intr_data[k].callback)
edma_cc[ctlr]->intr_data[k].callback(
k, DMA_COMPLETE,
edma_info[ctlr]->intr_data[k].
edma_cc[ctlr]->intr_data[k].
data);
}
}
}
cnt++;
@ -423,19 +423,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
if (edma_read_array(ctlr, EDMA_EMR, j) &
(1 << i)) {
BIT(i)) {
/* Clear the corresponding EMR bits */
edma_write_array(ctlr, EDMA_EMCR, j,
1 << i);
BIT(i));
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
j, (1 << i));
if (edma_info[ctlr]->intr_data[k].
j, BIT(i));
if (edma_cc[ctlr]->intr_data[k].
callback) {
edma_info[ctlr]->intr_data[k].
edma_cc[ctlr]->intr_data[k].
callback(k,
DMA_CC_ERROR,
edma_info[ctlr]->intr_data
edma_cc[ctlr]->intr_data
[k].data);
}
}
@ -444,11 +444,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(data, "QEMR %02x\n",
edma_read(ctlr, EDMA_QEMR));
for (i = 0; i < 8; i++) {
if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
/* Clear the corresponding IPR bits */
edma_write(ctlr, EDMA_QEMCR, 1 << i);
edma_write(ctlr, EDMA_QEMCR, BIT(i));
edma_shadow0_write(ctlr, SH_QSECR,
(1 << i));
BIT(i));
/* NOTE: not reported!! */
}
@ -460,20 +460,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
* to just write CCERRCLR with CCERR value...
*/
for (i = 0; i < 8; i++) {
if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
/* Clear the corresponding IPR bits */
edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
/* NOTE: not reported!! */
}
}
}
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
&& (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
&& (edma_read(ctlr, EDMA_QEMR) == 0)
&& (edma_read(ctlr, EDMA_CCERR) == 0)) {
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
(edma_read(ctlr, EDMA_QEMR) == 0) &&
(edma_read(ctlr, EDMA_CCERR) == 0))
break;
}
cnt++;
if (cnt > 10)
break;
@ -511,9 +510,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
int stop_slot = start_slot;
DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
j = EDMA_CHAN_SLOT(i);
if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
/* Record our current beginning slot */
if (count == num_slots)
stop_slot = i;
@ -529,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
stop_slot = i;
break;
} else
} else {
count = num_slots;
}
}
}
@ -540,12 +540,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
* of contiguous parameter RAM slots but do not find the exact number
* requested as we may reach the total number of parameter RAM slots
*/
if (i == edma_info[ctlr]->num_slots)
if (i == edma_cc[ctlr]->num_slots)
stop_slot = i;
for (j = start_slot; j < stop_slot; j++)
if (test_bit(j, tmp_inuse))
clear_bit(j, edma_info[ctlr]->edma_inuse);
clear_bit(j, edma_cc[ctlr]->edma_inuse);
if (count)
return -EBUSY;
@ -567,7 +567,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
(int)pdev->resource[i].start >= 0) {
ctlr = EDMA_CTLR(pdev->resource[i].start);
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
edma_info[ctlr]->edma_unused);
edma_cc[ctlr]->edma_unused);
}
}
@ -641,14 +641,13 @@ int edma_alloc_channel(int channel,
for (i = 0; i < arch_num_cc; i++) {
channel = 0;
for (;;) {
channel = find_next_bit(edma_info[i]->
edma_unused,
edma_info[i]->num_channels,
channel = find_next_bit(edma_cc[i]->edma_unused,
edma_cc[i]->num_channels,
channel);
if (channel == edma_info[i]->num_channels)
if (channel == edma_cc[i]->num_channels)
break;
if (!test_and_set_bit(channel,
edma_info[i]->edma_inuse)) {
edma_cc[i]->edma_inuse)) {
done = 1;
ctlr = i;
break;
@ -660,14 +659,14 @@ int edma_alloc_channel(int channel,
}
if (!done)
return -ENOMEM;
} else if (channel >= edma_info[ctlr]->num_channels) {
} else if (channel >= edma_cc[ctlr]->num_channels) {
return -EINVAL;
} else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
return -EBUSY;
}
/* ensure access through shadow region 0 */
edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
/* ensure no events are pending */
edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
@ -703,7 +702,7 @@ void edma_free_channel(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel >= edma_info[ctlr]->num_channels)
if (channel >= edma_cc[ctlr]->num_channels)
return;
setup_dma_interrupt(channel, NULL, NULL);
@ -711,7 +710,7 @@ void edma_free_channel(unsigned channel)
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
&dummy_paramset, PARM_SIZE);
clear_bit(channel, edma_info[ctlr]->edma_inuse);
clear_bit(channel, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@ -735,20 +734,19 @@ int edma_alloc_slot(unsigned ctlr, int slot)
slot = EDMA_CHAN_SLOT(slot);
if (slot < 0) {
slot = edma_info[ctlr]->num_channels;
slot = edma_cc[ctlr]->num_channels;
for (;;) {
slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
edma_info[ctlr]->num_slots, slot);
if (slot == edma_info[ctlr]->num_slots)
slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
edma_cc[ctlr]->num_slots, slot);
if (slot == edma_cc[ctlr]->num_slots)
return -ENOMEM;
if (!test_and_set_bit(slot,
edma_info[ctlr]->edma_inuse))
if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
break;
}
} else if (slot < edma_info[ctlr]->num_channels ||
slot >= edma_info[ctlr]->num_slots) {
} else if (slot < edma_cc[ctlr]->num_channels ||
slot >= edma_cc[ctlr]->num_slots) {
return -EINVAL;
} else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
return -EBUSY;
}
@ -774,13 +772,13 @@ void edma_free_slot(unsigned slot)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_channels ||
slot >= edma_info[ctlr]->num_slots)
if (slot < edma_cc[ctlr]->num_channels ||
slot >= edma_cc[ctlr]->num_slots)
return;
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
&dummy_paramset, PARM_SIZE);
clear_bit(slot, edma_info[ctlr]->edma_inuse);
clear_bit(slot, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@ -818,8 +816,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
* of slots
*/
if ((id != EDMA_CONT_PARAMS_ANY) &&
(slot < edma_info[ctlr]->num_channels ||
slot >= edma_info[ctlr]->num_slots))
(slot < edma_cc[ctlr]->num_channels ||
slot >= edma_cc[ctlr]->num_slots))
return -EINVAL;
/*
@ -828,13 +826,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
* channels
*/
if (count < 1 || count >
(edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
return -EINVAL;
switch (id) {
case EDMA_CONT_PARAMS_ANY:
return reserve_contiguous_slots(ctlr, id, count,
edma_info[ctlr]->num_channels);
edma_cc[ctlr]->num_channels);
case EDMA_CONT_PARAMS_FIXED_EXACT:
case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
return reserve_contiguous_slots(ctlr, id, count, slot);
@ -866,8 +864,8 @@ int edma_free_cont_slots(unsigned slot, int count)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_channels ||
slot >= edma_info[ctlr]->num_slots ||
if (slot < edma_cc[ctlr]->num_channels ||
slot >= edma_cc[ctlr]->num_slots ||
count < 1)
return -EINVAL;
@ -877,7 +875,7 @@ int edma_free_cont_slots(unsigned slot, int count)
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
&dummy_paramset, PARM_SIZE);
clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
}
return 0;
@ -907,7 +905,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_slots) {
if (slot < edma_cc[ctlr]->num_slots) {
unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
if (mode) {
@ -945,7 +943,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_slots) {
if (slot < edma_cc[ctlr]->num_slots) {
unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
if (mode) {
@ -1005,7 +1003,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_slots) {
if (slot < edma_cc[ctlr]->num_slots) {
edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
0xffff0000, src_bidx);
edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@ -1031,7 +1029,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_slots) {
if (slot < edma_cc[ctlr]->num_slots) {
edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
0x0000ffff, dest_bidx << 16);
edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@ -1078,7 +1076,7 @@ void edma_set_transfer_params(unsigned slot,
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot < edma_info[ctlr]->num_slots) {
if (slot < edma_cc[ctlr]->num_slots) {
edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
0x0000ffff, bcnt_rld << 16);
if (sync_mode == ASYNC)
@ -1108,9 +1106,9 @@ void edma_link(unsigned from, unsigned to)
ctlr_to = EDMA_CTLR(to);
to = EDMA_CHAN_SLOT(to);
if (from >= edma_info[ctlr_from]->num_slots)
if (from >= edma_cc[ctlr_from]->num_slots)
return;
if (to >= edma_info[ctlr_to]->num_slots)
if (to >= edma_cc[ctlr_to]->num_slots)
return;
edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
PARM_OFFSET(to));
@ -1131,7 +1129,7 @@ void edma_unlink(unsigned from)
ctlr = EDMA_CTLR(from);
from = EDMA_CHAN_SLOT(from);
if (from >= edma_info[ctlr]->num_slots)
if (from >= edma_cc[ctlr]->num_slots)
return;
edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
}
@ -1158,7 +1156,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot >= edma_info[ctlr]->num_slots)
if (slot >= edma_cc[ctlr]->num_slots)
return;
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
PARM_SIZE);
@ -1180,7 +1178,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
if (slot >= edma_info[ctlr]->num_slots)
if (slot >= edma_cc[ctlr]->num_slots)
return;
memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
PARM_SIZE);
@ -1205,8 +1203,8 @@ void edma_pause(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_info[ctlr]->num_channels) {
unsigned int mask = (1 << (channel & 0x1f));
if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
}
@ -1226,8 +1224,8 @@ void edma_resume(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_info[ctlr]->num_channels) {
unsigned int mask = (1 << (channel & 0x1f));
if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
}
@ -1252,12 +1250,12 @@ int edma_start(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_info[ctlr]->num_channels) {
if (channel < edma_cc[ctlr]->num_channels) {
int j = channel >> 5;
unsigned int mask = (1 << (channel & 0x1f));
unsigned int mask = BIT(channel & 0x1f);
/* EDMA channels without event association */
if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
pr_debug("EDMA: ESR%d %08x\n", j,
edma_shadow0_read_array(ctlr, SH_ESR, j));
edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@ -1298,9 +1296,9 @@ void edma_stop(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_info[ctlr]->num_channels) {
if (channel < edma_cc[ctlr]->num_channels) {
int j = channel >> 5;
unsigned int mask = (1 << (channel & 0x1f));
unsigned int mask = BIT(channel & 0x1f);
edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
@ -1337,9 +1335,9 @@ void edma_clean_channel(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_info[ctlr]->num_channels) {
if (channel < edma_cc[ctlr]->num_channels) {
int j = (channel >> 5);
unsigned int mask = 1 << (channel & 0x1f);
unsigned int mask = BIT(channel & 0x1f);
pr_debug("EDMA: EMR%d %08x\n", j,
edma_read_array(ctlr, EDMA_EMR, j));
@ -1348,7 +1346,7 @@ void edma_clean_channel(unsigned channel)
edma_write_array(ctlr, EDMA_EMCR, j, mask);
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
}
}
EXPORT_SYMBOL(edma_clean_channel);
@ -1365,12 +1363,12 @@ void edma_clear_event(unsigned channel)
ctlr = EDMA_CTLR(channel);
channel = EDMA_CHAN_SLOT(channel);
if (channel >= edma_info[ctlr]->num_channels)
if (channel >= edma_cc[ctlr]->num_channels)
return;
if (channel < 32)
edma_write(ctlr, EDMA_ECR, 1 << channel);
edma_write(ctlr, EDMA_ECR, BIT(channel));
else
edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
}
EXPORT_SYMBOL(edma_clear_event);
@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev)
break;
else
return -ENODEV;
} else
} else {
found = 1;
}
len[j] = resource_size(r[j]);
@ -1420,38 +1419,37 @@ static int __init edma_probe(struct platform_device *pdev)
goto fail1;
}
edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
if (!edma_info[j]) {
edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
if (!edma_cc[j]) {
status = -ENOMEM;
goto fail1;
}
memset(edma_info[j], 0, sizeof(struct edma));
memset(edma_cc[j], 0, sizeof(struct edma));
edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
EDMA_MAX_DMACH);
edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
EDMA_MAX_PARAMENTRY);
edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
EDMA_MAX_CC);
edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
edma_info[j]->default_queue = info[j].default_queue;
if (!edma_info[j]->default_queue)
edma_info[j]->default_queue = EVENTQ_1;
edma_cc[j]->default_queue = info[j].default_queue;
if (!edma_cc[j]->default_queue)
edma_cc[j]->default_queue = EVENTQ_1;
dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
edmacc_regs_base[j]);
for (i = 0; i < edma_info[j]->num_slots; i++)
for (i = 0; i < edma_cc[j]->num_slots; i++)
memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
&dummy_paramset, PARM_SIZE);
/* Mark all channels as unused */
memset(edma_info[j]->edma_unused, 0xff,
sizeof(edma_info[j]->edma_unused));
memset(edma_cc[j]->edma_unused, 0xff,
sizeof(edma_cc[j]->edma_unused));
sprintf(irq_name, "edma%d", j);
irq[j] = platform_get_irq_byname(pdev, irq_name);
edma_info[j]->irq_res_start = irq[j];
edma_cc[j]->irq_res_start = irq[j];
status = request_irq(irq[j], dma_irq_handler, 0, "edma",
&pdev->dev);
if (status < 0) {
@ -1462,7 +1460,7 @@ static int __init edma_probe(struct platform_device *pdev)
sprintf(irq_name, "edma%d_err", j);
err_irq[j] = platform_get_irq_byname(pdev, irq_name);
edma_info[j]->irq_res_end = err_irq[j];
edma_cc[j]->irq_res_end = err_irq[j];
status = request_irq(err_irq[j], dma_ccerr_handler, 0,
"edma_error", &pdev->dev);
if (status < 0) {
@ -1475,7 +1473,7 @@ static int __init edma_probe(struct platform_device *pdev)
* specified. This way, long transfers on the low priority queue
* started by the codec engine will not cause audio defects.
*/
for (i = 0; i < edma_info[j]->num_channels; i++)
for (i = 0; i < edma_cc[j]->num_channels; i++)
map_dmach_queue(j, i, EVENTQ_1);
queue_tc_mapping = info[j].queue_tc_mapping;
@ -1538,7 +1536,7 @@ fail1:
release_mem_region(r[i]->start, len[i]);
if (edmacc_regs_base[i])
iounmap(edmacc_regs_base[i]);
kfree(edma_info[i]);
kfree(edma_cc[i]);
}
return status;
}

166
arch/arm/mach-davinci/gpio.c
View File

@ -20,44 +20,90 @@
#include <asm/mach/irq.h>
static DEFINE_SPINLOCK(gpio_lock);
struct davinci_gpio {
struct gpio_chip chip;
struct gpio_controller *__iomem regs;
int irq_base;
struct davinci_gpio_regs {
u32 dir;
u32 out_data;
u32 set_data;
u32 clr_data;
u32 in_data;
u32 set_rising;
u32 clr_rising;
u32 set_falling;
u32 clr_falling;
u32 intstat;
};
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
#define chip2controller(chip) \
container_of(chip, struct davinci_gpio_controller, chip)
/* create a non-inlined version */
static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
static void __iomem *gpio_base;
static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
return __gpio_to_controller(gpio);
void __iomem *ptr;
if (gpio < 32 * 1)
ptr = gpio_base + 0x10;
else if (gpio < 32 * 2)
ptr = gpio_base + 0x38;
else if (gpio < 32 * 3)
ptr = gpio_base + 0x60;
else if (gpio < 32 * 4)
ptr = gpio_base + 0x88;
else if (gpio < 32 * 5)
ptr = gpio_base + 0xb0;
else
ptr = NULL;
return ptr;
}
static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
struct davinci_gpio_regs __iomem *g;
g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
return g;
}
static int __init davinci_gpio_irq_setup(void);
/*--------------------------------------------------------------------------*/
/*
* board setup code *MUST* set PINMUX0 and PINMUX1 as
* needed, and enable the GPIO clock.
*/
/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out, int value)
{
struct davinci_gpio_controller *d = chip2controller(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
unsigned long flags;
u32 temp;
u32 mask = 1 << offset;
spin_lock_irqsave(&d->lock, flags);
temp = __raw_readl(&g->dir);
if (out) {
temp &= ~mask;
__raw_writel(mask, value ? &g->set_data : &g->clr_data);
} else {
temp |= mask;
}
__raw_writel(temp, &g->dir);
spin_unlock_irqrestore(&d->lock, flags);
return 0;
}
static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
u32 temp;
return __davinci_direction(chip, offset, false, 0);
}
spin_lock(&gpio_lock);
temp = __raw_readl(&g->dir);
temp |= (1 << offset);
__raw_writel(temp, &g->dir);
spin_unlock(&gpio_lock);
return 0;
static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
return __davinci_direction(chip, offset, true, value);
}
/*
@ -69,37 +115,20 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
struct davinci_gpio_controller *d = chip2controller(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
return (1 << offset) & __raw_readl(&g->in_data);
}
static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
u32 temp;
u32 mask = 1 << offset;
spin_lock(&gpio_lock);
temp = __raw_readl(&g->dir);
temp &= ~mask;
__raw_writel(mask, value ? &g->set_data : &g->clr_data);
__raw_writel(temp, &g->dir);
spin_unlock(&gpio_lock);
return 0;
}
/*
* Assuming the pin is muxed as a gpio output, set its output value.
*/
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
struct davinci_gpio_controller *d = chip2controller(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}
@ -109,6 +138,10 @@ static int __init davinci_gpio_setup(void)
int i, base;
unsigned ngpio;
struct davinci_soc_info *soc_info = &davinci_soc_info;
struct davinci_gpio_regs *regs;
if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
return 0;
/*
* The gpio banks conceptually expose a segmented bitmap,
@ -124,6 +157,10 @@ static int __init davinci_gpio_setup(void)
if (WARN_ON(DAVINCI_N_GPIO < ngpio))
ngpio = DAVINCI_N_GPIO;
gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
if (WARN_ON(!gpio_base))
return -ENOMEM;
for (i = 0, base = 0; base < ngpio; i++, base += 32) {
chips[i].chip.label = "DaVinci";
@ -137,11 +174,20 @@ static int __init davinci_gpio_setup(void)
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
chips[i].regs = gpio2controller(base);
spin_lock_init(&chips[i].lock);
regs = gpio2regs(base);
chips[i].regs = regs;
chips[i].set_data = &regs->set_data;
chips[i].clr_data = &regs->clr_data;
chips[i].in_data = &regs->in_data;
gpiochip_add(&chips[i].chip);
}
soc_info->gpio_ctlrs = chips;
soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
davinci_gpio_irq_setup();
return 0;
}
@ -161,7 +207,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(unsigned irq)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
__raw_writel(mask, &g->clr_falling);
@ -170,7 +216,7 @@ static void gpio_irq_disable(unsigned irq)
static void gpio_irq_enable(unsigned irq)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
@ -186,7 +232,7 @@ static void gpio_irq_enable(unsigned irq)
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@ -215,7 +261,7 @@ static struct irq_chip gpio_irqchip = {
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = 0xffff;
/* we only care about one bank */
@ -253,7 +299,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct davinci_gpio_controller *d = chip2controller(chip);
if (d->irq_base >= 0)
return d->irq_base + offset;
@ -276,7 +322,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct davinci_gpio_regs __iomem *g = irq2regs(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@ -305,7 +351,7 @@ static int __init davinci_gpio_irq_setup(void)
u32 binten = 0;
unsigned ngpio, bank_irq;
struct davinci_soc_info *soc_info = &davinci_soc_info;
struct gpio_controller *__iomem g;
struct davinci_gpio_regs __iomem *g;
ngpio = soc_info->gpio_num;
@ -354,7 +400,7 @@ static int __init davinci_gpio_irq_setup(void)
gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
/* default trigger: both edges */
g = gpio2controller(0);
g = gpio2regs(0);
__raw_writel(~0, &g->set_falling);
__raw_writel(~0, &g->set_rising);
@ -362,7 +408,7 @@ static int __init davinci_gpio_irq_setup(void)
for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
set_irq_chip(irq, &gpio_irqchip_unbanked);
set_irq_data(irq, (void *) __gpio_mask(gpio));
set_irq_chip_data(irq, g);
set_irq_chip_data(irq, (__force void *) g);
irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
}
@ -379,18 +425,18 @@ static int __init davinci_gpio_irq_setup(void)
unsigned i;
/* disabled by default, enabled only as needed */
g = gpio2controller(gpio);
g = gpio2regs(gpio);
__raw_writel(~0, &g->clr_falling);
__raw_writel(~0, &g->clr_rising);
/* set up all irqs in this bank */
set_irq_chained_handler(bank_irq, gpio_irq_handler);
set_irq_chip_data(bank_irq, g);
set_irq_data(bank_irq, (void *)irq);
set_irq_chip_data(bank_irq, (__force void *) g);
set_irq_data(bank_irq, (void *) irq);
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
set_irq_chip(irq, &gpio_irqchip);
set_irq_chip_data(irq, g);
set_irq_chip_data(irq, (__force void *) g);
set_irq_data(irq, (void *) __gpio_mask(gpio));
set_irq_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
@ -403,7 +449,7 @@ done:
/* BINTEN -- per-bank interrupt enable. genirq would also let these
* bits be set/cleared dynamically.
*/
__raw_writel(binten, soc_info->gpio_base + 0x08);
__raw_writel(binten, gpio_base + 0x08);
printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));

32
arch/arm/mach-davinci/include/mach/common.h
View File

@ -12,6 +12,9 @@
#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
#include <linux/compiler.h>
#include <linux/types.h>
struct sys_timer;
extern struct sys_timer davinci_timer;
@ -21,7 +24,7 @@ extern void __iomem *davinci_intc_base;
extern int davinci_intc_type;
struct davinci_timer_instance {
void __iomem *base;
u32 base;
u32 bottom_irq;
u32 top_irq;
unsigned long cmp_off;
@ -34,39 +37,54 @@ struct davinci_timer_info {
unsigned int clocksource_id;
};
/* SoC specific init support */
struct davinci_gpio_controller;
/*
* SoC info passed into common davinci modules.
*
* Base addresses in this structure should be physical and not virtual.
* Modules that take such base addresses, should internally ioremap() them to
* use.
*/
struct davinci_soc_info {
struct map_desc *io_desc;
unsigned long io_desc_num;
u32 cpu_id;
u32 jtag_id;
void __iomem *jtag_id_base;
u32 jtag_id_reg;
struct davinci_id *ids;
unsigned long ids_num;
struct clk_lookup *cpu_clks;
void __iomem **psc_bases;
u32 *psc_bases;
unsigned long psc_bases_num;
void __iomem *pinmux_base;
u32 pinmux_base;
const struct mux_config *pinmux_pins;
unsigned long pinmux_pins_num;
void __iomem *intc_base;
u32 intc_base;
int intc_type;
u8 *intc_irq_prios;
unsigned long intc_irq_num;
u32 *intc_host_map;
struct davinci_timer_info *timer_info;
void __iomem *gpio_base;
int gpio_type;
u32 gpio_base;
unsigned gpio_num;
unsigned gpio_irq;
unsigned gpio_unbanked;
struct davinci_gpio_controller *gpio_ctlrs;
int gpio_ctlrs_num;
struct platform_device *serial_dev;
struct emac_platform_data *emac_pdata;
dma_addr_t sram_dma;
unsigned sram_len;
struct platform_device *reset_device;
void (*reset)(struct platform_device *);
};
extern struct davinci_soc_info davinci_soc_info;
extern void davinci_common_init(struct davinci_soc_info *soc_info);
extern void davinci_init_ide(void);
/* standard place to map on-chip SRAMs; they *may* support DMA */
#define SRAM_VIRT 0xfffe0000

3
arch/arm/mach-davinci/include/mach/cp_intc.h
View File

@ -51,7 +51,6 @@
#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
u8 *irq_prio);
void __init cp_intc_init(void);
#endif /* __ASM_HARDWARE_CP_INTC_H */

8
arch/arm/mach-davinci/include/mach/cputype.h
View File

@ -33,6 +33,7 @@ struct davinci_id {
#define DAVINCI_CPU_ID_DM365 0x03650000
#define DAVINCI_CPU_ID_DA830 0x08300000
#define DAVINCI_CPU_ID_DA850 0x08500000
#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
#define IS_DAVINCI_CPU(type, id) \
static inline int is_davinci_ ##type(void) \
@ -46,6 +47,7 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
#ifdef CONFIG_ARCH_DAVINCI_DM644x
#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@ -83,4 +85,10 @@ IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
#define cpu_is_davinci_da850() 0
#endif
#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
#else
#define cpu_is_davinci_tnetv107x() 0
#endif
#endif

29
arch/arm/mach-davinci/include/mach/da8xx.h
View File

@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base;
#define DA8XX_DDR2_CTL_BASE 0xb0000000
#define DA8XX_ARM_RAM_BASE 0xffff0000
#define PINMUX0 0x00
#define PINMUX1 0x04
#define PINMUX2 0x08
#define PINMUX3 0x0c
#define PINMUX4 0x10
#define PINMUX5 0x14
#define PINMUX6 0x18
#define PINMUX7 0x1c
#define PINMUX8 0x20
#define PINMUX9 0x24
#define PINMUX10 0x28
#define PINMUX11 0x2c
#define PINMUX12 0x30
#define PINMUX13 0x34
#define PINMUX14 0x38
#define PINMUX15 0x3c
#define PINMUX16 0x40
#define PINMUX17 0x44
#define PINMUX18 0x48
#define PINMUX19 0x4c
void __init da830_init(void);
void __init da850_init(void);
@ -108,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata;
extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
extern struct platform_device da8xx_wdt_device;
extern const short da830_emif25_pins[];
extern const short da830_spi0_pins[];
extern const short da830_spi1_pins[];
@ -146,10 +127,4 @@ extern const short da850_mmcsd0_pins[];
extern const short da850_nand_pins[];
extern const short da850_nor_pins[];
#ifdef CONFIG_DAVINCI_MUX
int da8xx_pinmux_setup(const short pins[]);
#else
static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
#endif
#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */

3
arch/arm/mach-davinci/include/mach/dm355.h
View File

@ -15,6 +15,9 @@
#include <mach/asp.h>
#include <media/davinci/vpfe_capture.h>
#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define ASP1_TX_EVT_EN 1
#define ASP1_RX_EVT_EN 2

4
arch/arm/mach-davinci/include/mach/dm365.h
View File

@ -36,6 +36,10 @@
#define DAVINCI_DMA_VC_TX 2
#define DAVINCI_DMA_VC_RX 3
#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
void __init dm365_init(void);
void __init dm365_init_asp(struct snd_platform_data *pdata);
void __init dm365_init_vc(struct snd_platform_data *pdata);

6
arch/arm/mach-davinci/include/mach/dm644x.h
View File

@ -34,6 +34,12 @@
#define DM644X_EMAC_MDIO_OFFSET (0x4000)
#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
void __init dm644x_init(void);
void __init dm644x_init_asp(struct snd_platform_data *pdata);
void dm644x_set_vpfe_config(struct vpfe_config *cfg);

4
arch/arm/mach-davinci/include/mach/dm646x.h
View File

@ -25,10 +25,10 @@
#define DM646X_EMAC_MDIO_OFFSET (0x4000)
#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
#define DM646X_ATA_REG_BASE (0x01C66000)
#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
void __init dm646x_init(void);
void __init dm646x_init_ide(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
void __init dm646x_board_setup_refclk(struct clk *clk);

70
arch/arm/mach-davinci/include/mach/gpio.h
View File

@ -14,6 +14,8 @@
#define __DAVINCI_GPIO_H
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm-generic/gpio.h>
#include <mach/irqs.h>
@ -21,6 +23,10 @@
#define DAVINCI_GPIO_BASE 0x01C67000
enum davinci_gpio_type {
GPIO_TYPE_DAVINCI = 0,
};
/*
* basic gpio routines
*
@ -45,17 +51,14 @@
/* Convert GPIO signal to GPIO pin number */
#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
struct gpio_controller {
u32 dir;
u32 out_data;
u32 set_data;
u32 clr_data;
u32 in_data;
u32 set_rising;
u32 clr_rising;
u32 set_falling;
u32 clr_falling;
u32 intstat;
struct davinci_gpio_controller {
struct gpio_chip chip;
int irq_base;
spinlock_t lock;
void __iomem *regs;
void __iomem *set_data;
void __iomem *clr_data;
void __iomem *in_data;
};
/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
@ -67,25 +70,16 @@ struct gpio_controller {
*
* These are NOT part of the cross-platform GPIO interface
*/
static inline struct gpio_controller *__iomem
static inline struct davinci_gpio_controller *
__gpio_to_controller(unsigned gpio)
{
void *__iomem ptr;
void __iomem *base = davinci_soc_info.gpio_base;
struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
int index = gpio / 32;
if (gpio < 32 * 1)
ptr = base + 0x10;
else if (gpio < 32 * 2)
ptr = base + 0x38;
else if (gpio < 32 * 3)
ptr = base + 0x60;
else if (gpio < 32 * 4)
ptr = base + 0x88;
else if (gpio < 32 * 5)
ptr = base + 0xb0;
else
ptr = NULL;
return ptr;
if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
return NULL;
return ctlrs + index;
}
static inline u32 __gpio_mask(unsigned gpio)
@ -101,16 +95,16 @@ static inline u32 __gpio_mask(unsigned gpio)
*/
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
struct gpio_controller *__iomem g;
u32 mask;
if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
struct davinci_gpio_controller *ctlr;
u32 mask;
g = __gpio_to_controller(gpio);
ctlr = __gpio_to_controller(gpio);
mask = __gpio_mask(gpio);
if (value)
__raw_writel(mask, &g->set_data);
__raw_writel(mask, ctlr->set_data);
else
__raw_writel(mask, &g->clr_data);
__raw_writel(mask, ctlr->clr_data);
return;
}
@ -128,18 +122,18 @@ static inline void gpio_set_value(unsigned gpio, int value)
*/
static inline int gpio_get_value(unsigned gpio)
{
struct gpio_controller *__iomem g;
struct davinci_gpio_controller *ctlr;
if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
return __gpio_get_value(gpio);
g = __gpio_to_controller(gpio);
return __gpio_mask(gpio) & __raw_readl(&g->in_data);
ctlr = __gpio_to_controller(gpio);
return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
}
static inline int gpio_cansleep(unsigned gpio)
{
if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
return 0;
else
return __gpio_cansleep(gpio);

97
arch/arm/mach-davinci/include/mach/irqs.h
View File

@ -401,6 +401,103 @@
#define DA850_N_CP_INTC_IRQ 101
/* TNETV107X specific interrupts */
#define IRQ_TNETV107X_TDM1_TXDMA 0
#define IRQ_TNETV107X_EXT_INT_0 1
#define IRQ_TNETV107X_EXT_INT_1 2
#define IRQ_TNETV107X_GPIO_INT12 3
#define IRQ_TNETV107X_GPIO_INT13 4
#define IRQ_TNETV107X_TIMER_0_TINT12 5
#define IRQ_TNETV107X_TIMER_1_TINT12 6
#define IRQ_TNETV107X_UART0 7
#define IRQ_TNETV107X_TDM1_RXDMA 8
#define IRQ_TNETV107X_MCDMA_INT0 9
#define IRQ_TNETV107X_MCDMA_INT1 10
#define IRQ_TNETV107X_TPCC 11
#define IRQ_TNETV107X_TPCC_INT0 12
#define IRQ_TNETV107X_TPCC_INT1 13
#define IRQ_TNETV107X_TPCC_INT2 14
#define IRQ_TNETV107X_TPCC_INT3 15
#define IRQ_TNETV107X_TPTC0 16
#define IRQ_TNETV107X_TPTC1 17
#define IRQ_TNETV107X_TIMER_0_TINT34 18
#define IRQ_TNETV107X_ETHSS 19
#define IRQ_TNETV107X_TIMER_1_TINT34 20
#define IRQ_TNETV107X_DSP2ARM_INT0 21
#define IRQ_TNETV107X_DSP2ARM_INT1 22
#define IRQ_TNETV107X_ARM_NPMUIRQ 23
#define IRQ_TNETV107X_USB1 24
#define IRQ_TNETV107X_VLYNQ 25
#define IRQ_TNETV107X_UART0_DMATX 26
#define IRQ_TNETV107X_UART0_DMARX 27
#define IRQ_TNETV107X_TDM1_TXMCSP 28
#define IRQ_TNETV107X_SSP 29
#define IRQ_TNETV107X_MCDMA_INT2 30
#define IRQ_TNETV107X_MCDMA_INT3 31
#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
#define IRQ_TNETV107X_USB0 34
#define IRQ_TNETV107X_USB_CDMA 35
#define IRQ_TNETV107X_LCD 36
#define IRQ_TNETV107X_KEYPAD 37
#define IRQ_TNETV107X_KEYPAD_FREE 38
#define IRQ_TNETV107X_RNG 39
#define IRQ_TNETV107X_PKA 40
#define IRQ_TNETV107X_TDM0_TXDMA 41
#define IRQ_TNETV107X_TDM0_RXDMA 42
#define IRQ_TNETV107X_TDM0_TXMCSP 43
#define IRQ_TNETV107X_TDM0_RXMCSP 44
#define IRQ_TNETV107X_TDM1_RXMCSP 45
#define IRQ_TNETV107X_SDIO1 46
#define IRQ_TNETV107X_SDIO0 47
#define IRQ_TNETV107X_TSC 48
#define IRQ_TNETV107X_TS 49
#define IRQ_TNETV107X_UART1 50
#define IRQ_TNETV107X_MBX_LITE 51
#define IRQ_TNETV107X_GPIO_INT00 52
#define IRQ_TNETV107X_GPIO_INT01 53
#define IRQ_TNETV107X_GPIO_INT02 54
#define IRQ_TNETV107X_GPIO_INT03 55
#define IRQ_TNETV107X_UART2 56
#define IRQ_TNETV107X_UART2_DMATX 57
#define IRQ_TNETV107X_UART2_DMARX 58
#define IRQ_TNETV107X_IMCOP_IMX 59
#define IRQ_TNETV107X_IMCOP_VLCD 60
#define IRQ_TNETV107X_AES 61
#define IRQ_TNETV107X_DES 62
#define IRQ_TNETV107X_SHAMD5 63
#define IRQ_TNETV107X_TPCC_ERR 68
#define IRQ_TNETV107X_TPCC_PROT 69
#define IRQ_TNETV107X_TPTC0_ERR 70
#define IRQ_TNETV107X_TPTC1_ERR 71
#define IRQ_TNETV107X_UART0_ERR 72
#define IRQ_TNETV107X_UART1_ERR 73
#define IRQ_TNETV107X_AEMIF_ERR 74
#define IRQ_TNETV107X_DDR_ERR 75
#define IRQ_TNETV107X_WDTARM_INT0 76
#define IRQ_TNETV107X_MCDMA_ERR 77
#define IRQ_TNETV107X_GPIO_ERR 78
#define IRQ_TNETV107X_MPU_ADDR 79
#define IRQ_TNETV107X_MPU_PROT 80
#define IRQ_TNETV107X_IOPU_ADDR 81
#define IRQ_TNETV107X_IOPU_PROT 82
#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
#define IRQ_TNETV107X_PLL_UNLOCK 87
#define IRQ_TNETV107X_WDTDSP_INT0 88
#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
#define IRQ_TNETV107X_PBIST_CPU 91
#define IRQ_TNETV107X_WDTARM 92
#define IRQ_TNETV107X_PSC 93
#define IRQ_TNETV107X_MMC0 94
#define IRQ_TNETV107X_MMC1 95
#define TNETV107X_N_CP_INTC_IRQ 96
/* da850 currently has the most gpio pins (144) */
#define DAVINCI_N_GPIO 144
/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */

290
arch/arm/mach-davinci/include/mach/mux.h
View File

@ -194,11 +194,14 @@ enum davinci_dm365_index {
DM365_I2C_SCL,
/* AEMIF */
DM365_AEMIF_AR,
DM365_AEMIF_AR_A14,
DM365_AEMIF_AR_BA0,
DM365_AEMIF_A3,
DM365_AEMIF_A7,
DM365_AEMIF_D15_8,
DM365_AEMIF_CE0,
DM365_AEMIF_CE1,
DM365_AEMIF_WE_OE,
/* ASP0 function */
DM365_MCBSP0_BDX,
@ -287,10 +290,19 @@ enum davinci_dm365_index {
DM365_SPI4_SDENA0,
DM365_SPI4_SDENA1,
/* Clock */
DM365_CLKOUT0,
DM365_CLKOUT1,
DM365_CLKOUT2,
/* GPIO */
DM365_GPIO20,
DM365_GPIO30,
DM365_GPIO31,
DM365_GPIO32,
DM365_GPIO33,
DM365_GPIO40,
DM365_GPIO64_57,
/* Video */
DM365_VOUT_FIELD,
@ -904,12 +916,288 @@ enum davinci_da850_index {
DA850_RTC_ALARM,
};
enum davinci_tnetv107x_index {
TNETV107X_ASR_A00,
TNETV107X_GPIO32,
TNETV107X_ASR_A01,
TNETV107X_GPIO33,
TNETV107X_ASR_A02,
TNETV107X_GPIO34,
TNETV107X_ASR_A03,
TNETV107X_GPIO35,
TNETV107X_ASR_A04,
TNETV107X_GPIO36,
TNETV107X_ASR_A05,
TNETV107X_GPIO37,
TNETV107X_ASR_A06,
TNETV107X_GPIO38,
TNETV107X_ASR_A07,
TNETV107X_GPIO39,
TNETV107X_ASR_A08,
TNETV107X_GPIO40,
TNETV107X_ASR_A09,
TNETV107X_GPIO41,
TNETV107X_ASR_A10,
TNETV107X_GPIO42,
TNETV107X_ASR_A11,
TNETV107X_BOOT_STRP_0,
TNETV107X_ASR_A12,
TNETV107X_BOOT_STRP_1,
TNETV107X_ASR_A13,
TNETV107X_GPIO43,
TNETV107X_ASR_A14,
TNETV107X_GPIO44,
TNETV107X_ASR_A15,
TNETV107X_GPIO45,
TNETV107X_ASR_A16,
TNETV107X_GPIO46,
TNETV107X_ASR_A17,
TNETV107X_GPIO47,
TNETV107X_ASR_A18,
TNETV107X_GPIO48,
TNETV107X_SDIO1_DATA3_0,
TNETV107X_ASR_A19,
TNETV107X_GPIO49,
TNETV107X_SDIO1_DATA2_0,
TNETV107X_ASR_A20,
TNETV107X_GPIO50,
TNETV107X_SDIO1_DATA1_0,
TNETV107X_ASR_A21,
TNETV107X_GPIO51,
TNETV107X_SDIO1_DATA0_0,
TNETV107X_ASR_A22,
TNETV107X_GPIO52,
TNETV107X_SDIO1_CMD_0,
TNETV107X_ASR_A23,
TNETV107X_GPIO53,
TNETV107X_SDIO1_CLK_0,
TNETV107X_ASR_BA_1,
TNETV107X_GPIO54,
TNETV107X_SYS_PLL_CLK,
TNETV107X_ASR_CS0,
TNETV107X_ASR_CS1,
TNETV107X_ASR_CS2,
TNETV107X_TDM_PLL_CLK,
TNETV107X_ASR_CS3,
TNETV107X_ETH_PHY_CLK,
TNETV107X_ASR_D00,
TNETV107X_GPIO55,
TNETV107X_ASR_D01,
TNETV107X_GPIO56,
TNETV107X_ASR_D02,
TNETV107X_GPIO57,
TNETV107X_ASR_D03,
TNETV107X_GPIO58,
TNETV107X_ASR_D04,
TNETV107X_GPIO59_0,
TNETV107X_ASR_D05,
TNETV107X_GPIO60_0,
TNETV107X_ASR_D06,
TNETV107X_GPIO61_0,
TNETV107X_ASR_D07,
TNETV107X_GPIO62_0,
TNETV107X_ASR_D08,
TNETV107X_GPIO63_0,
TNETV107X_ASR_D09,
TNETV107X_GPIO64_0,
TNETV107X_ASR_D10,
TNETV107X_SDIO1_DATA3_1,
TNETV107X_ASR_D11,
TNETV107X_SDIO1_DATA2_1,
TNETV107X_ASR_D12,
TNETV107X_SDIO1_DATA1_1,
TNETV107X_ASR_D13,
TNETV107X_SDIO1_DATA0_1,
TNETV107X_ASR_D14,
TNETV107X_SDIO1_CMD_1,
TNETV107X_ASR_D15,
TNETV107X_SDIO1_CLK_1,
TNETV107X_ASR_OE,
TNETV107X_BOOT_STRP_2,
TNETV107X_ASR_RNW,
TNETV107X_GPIO29_0,
TNETV107X_ASR_WAIT,
TNETV107X_GPIO30_0,
TNETV107X_ASR_WE,
TNETV107X_BOOT_STRP_3,
TNETV107X_ASR_WE_DQM0,
TNETV107X_GPIO31,
TNETV107X_LCD_PD17_0,
TNETV107X_ASR_WE_DQM1,
TNETV107X_ASR_BA0_0,
TNETV107X_VLYNQ_CLK,
TNETV107X_GPIO14,
TNETV107X_LCD_PD19_0,
TNETV107X_VLYNQ_RXD0,
TNETV107X_GPIO15,
TNETV107X_LCD_PD20_0,
TNETV107X_VLYNQ_RXD1,
TNETV107X_GPIO16,
TNETV107X_LCD_PD21_0,
TNETV107X_VLYNQ_TXD0,
TNETV107X_GPIO17,
TNETV107X_LCD_PD22_0,
TNETV107X_VLYNQ_TXD1,
TNETV107X_GPIO18,
TNETV107X_LCD_PD23_0,
TNETV107X_SDIO0_CLK,
TNETV107X_GPIO19,
TNETV107X_SDIO0_CMD,
TNETV107X_GPIO20,
TNETV107X_SDIO0_DATA0,
TNETV107X_GPIO21,
TNETV107X_SDIO0_DATA1,
TNETV107X_GPIO22,
TNETV107X_SDIO0_DATA2,
TNETV107X_GPIO23,
TNETV107X_SDIO0_DATA3,
TNETV107X_GPIO24,
TNETV107X_EMU0,
TNETV107X_EMU1,
TNETV107X_RTCK,
TNETV107X_TRST_N,
TNETV107X_TCK,
TNETV107X_TDI,
TNETV107X_TDO,
TNETV107X_TMS,
TNETV107X_TDM1_CLK,
TNETV107X_TDM1_RX,
TNETV107X_TDM1_TX,
TNETV107X_TDM1_FS,
TNETV107X_KEYPAD_R0,
TNETV107X_KEYPAD_R1,
TNETV107X_KEYPAD_R2,
TNETV107X_KEYPAD_R3,
TNETV107X_KEYPAD_R4,
TNETV107X_KEYPAD_R5,
TNETV107X_KEYPAD_R6,
TNETV107X_GPIO12,
TNETV107X_KEYPAD_R7,
TNETV107X_GPIO10,
TNETV107X_KEYPAD_C0,
TNETV107X_KEYPAD_C1,
TNETV107X_KEYPAD_C2,
TNETV107X_KEYPAD_C3,
TNETV107X_KEYPAD_C4,
TNETV107X_KEYPAD_C5,
TNETV107X_KEYPAD_C6,
TNETV107X_GPIO13,
TNETV107X_TEST_CLK_IN,
TNETV107X_KEYPAD_C7,
TNETV107X_GPIO11,
TNETV107X_SSP0_0,
TNETV107X_SCC_DCLK,
TNETV107X_LCD_PD20_1,
TNETV107X_SSP0_1,
TNETV107X_SCC_CS_N,
TNETV107X_LCD_PD21_1,
TNETV107X_SSP0_2,
TNETV107X_SCC_D,
TNETV107X_LCD_PD22_1,
TNETV107X_SSP0_3,
TNETV107X_SCC_RESETN,
TNETV107X_LCD_PD23_1,
TNETV107X_SSP1_0,
TNETV107X_GPIO25,
TNETV107X_UART2_CTS,
TNETV107X_SSP1_1,
TNETV107X_GPIO26,
TNETV107X_UART2_RD,
TNETV107X_SSP1_2,
TNETV107X_GPIO27,
TNETV107X_UART2_RTS,
TNETV107X_SSP1_3,
TNETV107X_GPIO28,
TNETV107X_UART2_TD,
TNETV107X_UART0_CTS,
TNETV107X_UART0_RD,
TNETV107X_UART0_RTS,
TNETV107X_UART0_TD,
TNETV107X_UART1_RD,
TNETV107X_UART1_TD,
TNETV107X_LCD_AC_NCS,
TNETV107X_LCD_HSYNC_RNW,
TNETV107X_LCD_VSYNC_A0,
TNETV107X_LCD_MCLK,
TNETV107X_LCD_PD16_0,
TNETV107X_LCD_PCLK_E,
TNETV107X_LCD_PD00,
TNETV107X_LCD_PD01,
TNETV107X_LCD_PD02,
TNETV107X_LCD_PD03,
TNETV107X_LCD_PD04,
TNETV107X_LCD_PD05,
TNETV107X_LCD_PD06,
TNETV107X_LCD_PD07,
TNETV107X_LCD_PD08,
TNETV107X_GPIO59_1,
TNETV107X_LCD_PD09,
TNETV107X_GPIO60_1,
TNETV107X_LCD_PD10,
TNETV107X_ASR_BA0_1,
TNETV107X_GPIO61_1,
TNETV107X_LCD_PD11,
TNETV107X_GPIO62_1,
TNETV107X_LCD_PD12,
TNETV107X_GPIO63_1,
TNETV107X_LCD_PD13,
TNETV107X_GPIO64_1,
TNETV107X_LCD_PD14,
TNETV107X_GPIO29_1,
TNETV107X_LCD_PD15,
TNETV107X_GPIO30_1,
TNETV107X_EINT0,
TNETV107X_GPIO08,
TNETV107X_EINT1,
TNETV107X_GPIO09,
TNETV107X_GPIO00,
TNETV107X_LCD_PD20_2,
TNETV107X_TDM_CLK_IN_2,
TNETV107X_GPIO01,
TNETV107X_LCD_PD21_2,
TNETV107X_24M_CLK_OUT_1,
TNETV107X_GPIO02,
TNETV107X_LCD_PD22_2,
TNETV107X_GPIO03,
TNETV107X_LCD_PD23_2,
TNETV107X_GPIO04,
TNETV107X_LCD_PD16_1,
TNETV107X_USB0_RXERR,
TNETV107X_GPIO05,
TNETV107X_LCD_PD17_1,
TNETV107X_TDM_CLK_IN_1,
TNETV107X_GPIO06,
TNETV107X_LCD_PD18,
TNETV107X_24M_CLK_OUT_2,
TNETV107X_GPIO07,
TNETV107X_LCD_PD19_1,
TNETV107X_USB1_RXERR,
TNETV107X_ETH_PLL_CLK,
TNETV107X_MDIO,
TNETV107X_MDC,
TNETV107X_AIC_MUTE_STAT_N,
TNETV107X_TDM0_CLK,
TNETV107X_AIC_HNS_EN_N,
TNETV107X_TDM0_FS,
TNETV107X_AIC_HDS_EN_STAT_N,
TNETV107X_TDM0_TX,
TNETV107X_AIC_HNF_EN_STAT_N,
TNETV107X_TDM0_RX,
};
#define PINMUX(x) (4 * (x))
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
extern int davinci_cfg_reg_list(const short pins[]);
#else
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
static inline int davinci_cfg_reg_list(const short pins[])
{
return 0;
}
#endif
#endif /* __INC_MACH_MUX_H */

55
arch/arm/mach-davinci/include/mach/psc.h
View File

@ -180,6 +180,53 @@
#define DA8XX_LPSC1_CR_P3_SS 26
#define DA8XX_LPSC1_L3_CBA_RAM 31
/* TNETV107X LPSC Assignments */
#define TNETV107X_LPSC_ARM 0
#define TNETV107X_LPSC_GEM 1
#define TNETV107X_LPSC_DDR2_PHY 2
#define TNETV107X_LPSC_TPCC 3
#define TNETV107X_LPSC_TPTC0 4
#define TNETV107X_LPSC_TPTC1 5
#define TNETV107X_LPSC_RAM 6
#define TNETV107X_LPSC_MBX_LITE 7
#define TNETV107X_LPSC_LCD 8
#define TNETV107X_LPSC_ETHSS 9
#define TNETV107X_LPSC_AEMIF 10
#define TNETV107X_LPSC_CHIP_CFG 11
#define TNETV107X_LPSC_TSC 12
#define TNETV107X_LPSC_ROM 13
#define TNETV107X_LPSC_UART2 14
#define TNETV107X_LPSC_PKTSEC 15
#define TNETV107X_LPSC_SECCTL 16
#define TNETV107X_LPSC_KEYMGR 17
#define TNETV107X_LPSC_KEYPAD 18
#define TNETV107X_LPSC_GPIO 19
#define TNETV107X_LPSC_MDIO 20
#define TNETV107X_LPSC_SDIO0 21
#define TNETV107X_LPSC_UART0 22
#define TNETV107X_LPSC_UART1 23
#define TNETV107X_LPSC_TIMER0 24
#define TNETV107X_LPSC_TIMER1 25
#define TNETV107X_LPSC_WDT_ARM 26
#define TNETV107X_LPSC_WDT_DSP 27
#define TNETV107X_LPSC_SSP 28
#define TNETV107X_LPSC_TDM0 29
#define TNETV107X_LPSC_VLYNQ 30
#define TNETV107X_LPSC_MCDMA 31
#define TNETV107X_LPSC_USB0 32
#define TNETV107X_LPSC_TDM1 33
#define TNETV107X_LPSC_DEBUGSS 34
#define TNETV107X_LPSC_ETHSS_RGMII 35
#define TNETV107X_LPSC_SYSTEM 36
#define TNETV107X_LPSC_IMCOP 37
#define TNETV107X_LPSC_SPARE 38
#define TNETV107X_LPSC_SDIO1 39
#define TNETV107X_LPSC_USB1 40
#define TNETV107X_LPSC_USBSS 41
#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
#define TNETV107X_LPSC_MAX 44
/* PSC register offsets */
#define EPCPR 0x070
#define PTCMD 0x120
@ -189,13 +236,19 @@
#define MDSTAT 0x800
#define MDCTL 0xA00
/* PSC module states */
#define PSC_STATE_SWRSTDISABLE 0
#define PSC_STATE_SYNCRST 1
#define PSC_STATE_DISABLE 2
#define PSC_STATE_ENABLE 3
#define MDSTAT_STATE_MASK 0x1f
#ifndef __ASSEMBLER__
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, char enable);
unsigned int id, u32 next_state);
#endif

1
arch/arm/mach-davinci/include/mach/serial.h
View File

@ -13,7 +13,6 @@
#include <mach/hardware.h>
#define DAVINCI_MAX_NR_UARTS 3
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)

5
arch/arm/mach-davinci/include/mach/system.h
View File

@ -11,7 +11,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
extern void davinci_watchdog_reset(void);
#include <mach/common.h>
static inline void arch_idle(void)
{
@ -20,7 +20,8 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode, const char *cmd)
{
davinci_watchdog_reset();
if (davinci_soc_info.reset)
davinci_soc_info.reset(davinci_soc_info.reset_device);
}
#endif /* __ASM_ARCH_SYSTEM_H */

20
arch/arm/mach-davinci/io.c
View File

@ -12,19 +12,29 @@
#include <linux/io.h>
#include <asm/tlb.h>
#include <asm/mach/map.h>
#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
#include <mach/common.h>
/*
* Intercept ioremap() requests for addresses in our fixed mapping regions.
*/
void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
{
if (BETWEEN(p, IO_PHYS, IO_SIZE))
return XLATE(p, IO_PHYS, IO_VIRT);
struct map_desc *desc = davinci_soc_info.io_desc;
int desc_num = davinci_soc_info.io_desc_num;
int i;
return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
for (i = 0; i < desc_num; i++, desc++) {
unsigned long iophys = __pfn_to_phys(desc->pfn);
unsigned long iosize = desc->length;
if (p >= iophys && (p + size) <= (iophys + iosize))
return __io(desc->virtual + p - iophys);
}
return __arm_ioremap_caller(p, size, type,
__builtin_return_address(0));
}
EXPORT_SYMBOL(davinci_ioremap);

7
arch/arm/mach-davinci/irq.c
View File

@ -116,6 +116,11 @@ void __init davinci_irq_init(void)
unsigned i;
const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
if (WARN_ON(!davinci_intc_base))
return;
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
@ -148,7 +153,7 @@ void __init davinci_irq_init(void)
}
/* set up genirq dispatch for ARM INTC */
for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
set_irq_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (i != IRQ_TINT1_TINT34)

19
arch/arm/mach-davinci/mux.c
View File

@ -22,6 +22,8 @@
#include <mach/mux.h>
#include <mach/common.h>
static void __iomem *pinmux_base;
/*
* Sets the DAVINCI MUX register based on the table
*/
@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
{
static DEFINE_SPINLOCK(mux_spin_lock);
struct davinci_soc_info *soc_info = &davinci_soc_info;
void __iomem *base = soc_info->pinmux_base;
unsigned long flags;
const struct mux_config *cfg;
unsigned int reg_orig = 0, reg = 0;
unsigned int mask, warn = 0;
if (!soc_info->pinmux_pins)
BUG();
if (WARN_ON(!soc_info->pinmux_pins))
return -ENODEV;
if (!pinmux_base) {
pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
if (WARN_ON(!pinmux_base))
return -ENOMEM;
}
if (index >= soc_info->pinmux_pins_num) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
reg_orig = __raw_readl(base + cfg->mux_reg);
reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
mask = (cfg->mask << cfg->mask_offset);
tmp1 = reg_orig & mask;
@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
if (tmp1 != tmp2)
warn = 1;
__raw_writel(reg, base + cfg->mux_reg);
__raw_writel(reg, pinmux_base + cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
@ -91,7 +98,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
}
EXPORT_SYMBOL(davinci_cfg_reg);
int da8xx_pinmux_setup(const short pins[])
int __init_or_module davinci_cfg_reg_list(const short pins[])
{
int i, error = -EINVAL;

2
arch/arm/mach-davinci/mux.h
View File

@ -20,7 +20,7 @@
.name = #desc, \
.debug = dbg, \
.mux_reg_name = "PINMUX"#muxreg, \
.mux_reg = PINMUX##muxreg, \
.mux_reg = PINMUX(muxreg), \
.mask_offset = mode_offset, \
.mask = mode_mask, \
.mode = mux_mode, \

10
arch/arm/mach-davinci/psc.c
View File

@ -38,8 +38,9 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
return 0;
}
psc_base = soc_info->psc_bases[ctlr];
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
iounmap(psc_base);
/* if clocked, state can be "Enable" or "SyncReset" */
return mdstat & BIT(12);
@ -47,12 +48,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, char enable)
unsigned int id, u32 next_state)
{
u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
void __iomem *psc_base;
struct davinci_soc_info *soc_info = &davinci_soc_info;
u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
@ -60,7 +60,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
return;
}
psc_base = soc_info->psc_bases[ctlr];
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
mdctl &= ~MDSTAT_STATE_MASK;
@ -100,4 +100,6 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
do {
mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
iounmap(psc_base);
}

34
arch/arm/mach-davinci/serial.c
View File

@ -35,14 +35,20 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
int offset)
{
offset <<= up->regshift;
return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
return (unsigned int)__raw_readl(up->membase + offset);
}
static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
int value)
{
offset <<= p->regshift;
__raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
__raw_writel(value, p->membase + offset);
}
static void __init davinci_serial_reset(struct plat_serial8250_port *p)
@ -77,20 +83,32 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on if not needed.
*/
for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) {
for (i = 0; p->flags; i++, p++) {
if (!(info->enabled_uarts & (1 << i)))
continue;
sprintf(name, "uart%d", i);
uart_clk = clk_get(dev, name);
if (IS_ERR(uart_clk))
if (IS_ERR(uart_clk)) {
printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
__func__, __LINE__, i);
else {
clk_enable(uart_clk);
p->uartclk = clk_get_rate(uart_clk);
davinci_serial_reset(p);
continue;
}
clk_enable(uart_clk);
p->uartclk = clk_get_rate(uart_clk);
if (!p->membase && p->mapbase) {
p->membase = ioremap(p->mapbase, SZ_4K);
if (p->membase)
p->flags &= ~UPF_IOREMAP;
else
pr_err("uart regs ioremap failed\n");
}
if (p->membase && p->type != PORT_AR7)
davinci_serial_reset(p);
}
return platform_device_register(soc_info->serial_dev);

37
arch/arm/mach-davinci/time.c
View File

@ -197,32 +197,36 @@ static void __init timer_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
void __iomem *base[2];
int i;
/* Global init of each 64-bit timer as a whole */
for(i=0; i<2; i++) {
u32 tgcr;
void __iomem *base = dtip[i].base;
base[i] = ioremap(dtip[i].base, SZ_4K);
if (WARN_ON(!base[i]))
continue;
/* Disabled, Internal clock source */
__raw_writel(0, base + TCR);
__raw_writel(0, base[i] + TCR);
/* reset both timers, no pre-scaler for timer34 */
tgcr = 0;
__raw_writel(tgcr, base + TGCR);
__raw_writel(tgcr, base[i] + TGCR);
/* Set both timers to unchained 32-bit */
tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
__raw_writel(tgcr, base + TGCR);
__raw_writel(tgcr, base[i] + TGCR);
/* Unreset timers */
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
__raw_writel(tgcr, base + TGCR);
__raw_writel(tgcr, base[i] + TGCR);
/* Init both counters to zero */
__raw_writel(0, base + TIM12);
__raw_writel(0, base + TIM34);
__raw_writel(0, base[i] + TIM12);
__raw_writel(0, base[i] + TIM34);
}
/* Init of each timer as a 32-bit timer */
@ -231,7 +235,9 @@ static void __init timer_init(void)
int timer = ID_TO_TIMER(t->id);
u32 irq;
t->base = dtip[timer].base;
t->base = base[timer];
if (!t->base)
continue;
if (IS_TIMER_BOT(t->id)) {
t->enamode_shift = 6;
@ -361,13 +367,13 @@ static void __init davinci_timer_init(void)
}
}
/* init timer hw */
timer_init();
timer_clk = clk_get(NULL, "timer0");
BUG_ON(IS_ERR(timer_clk));
clk_enable(timer_clk);
/* init timer hw */
timer_init();
davinci_clock_tick_rate = clk_get_rate(timer_clk);
/* setup clocksource */
@ -399,13 +405,16 @@ struct sys_timer davinci_timer = {
/* reset board using watchdog timer */
void davinci_watchdog_reset(void)
void davinci_watchdog_reset(struct platform_device *pdev)
{
u32 tgcr, wdtcr;
struct platform_device *pdev = &davinci_wdt_device;
void __iomem *base = IO_ADDRESS(pdev->resource[0].start);
void __iomem *base;
struct clk *wd_clk;
base = ioremap(pdev->resource[0].start, SZ_4K);
if (WARN_ON(!base))
return;
wd_clk = clk_get(&pdev->dev, NULL);
if (WARN_ON(IS_ERR(wd_clk)))
return;

10
drivers/rtc/Kconfig
View File

@ -620,6 +620,16 @@ config RTC_DRV_NUC900
comment "on-CPU RTC drivers"
config RTC_DRV_DAVINCI
tristate "TI DaVinci RTC"
depends on ARCH_DAVINCI_DM365
help
If you say yes here you get support for the RTC on the
DaVinci platforms (DM365).
This driver can also be built as a module. If so, the module
will be called rtc-davinci.
config RTC_DRV_OMAP
tristate "TI OMAP1"
depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX

1
drivers/rtc/Makefile
View File

@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o

673
drivers/rtc/rtc-davinci.c Normal file
View File

@ -0,0 +1,673 @@
/*
* DaVinci Power Management and Real Time Clock Driver for TI platforms
*
* Copyright (C) 2009 Texas Instruments, Inc
*
* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/io.h>
/*
* The DaVinci RTC is a simple RTC with the following
* Sec: 0 - 59 : BCD count
* Min: 0 - 59 : BCD count
* Hour: 0 - 23 : BCD count
* Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
*/
/* PRTC interface registers */
#define DAVINCI_PRTCIF_PID 0x00
#define PRTCIF_CTLR 0x04
#define PRTCIF_LDATA 0x08
#define PRTCIF_UDATA 0x0C
#define PRTCIF_INTEN 0x10
#define PRTCIF_INTFLG 0x14
/* PRTCIF_CTLR bit fields */
#define PRTCIF_CTLR_BUSY BIT(31)
#define PRTCIF_CTLR_SIZE BIT(25)
#define PRTCIF_CTLR_DIR BIT(24)
#define PRTCIF_CTLR_BENU_MSB BIT(23)
#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
#define PRTCIF_CTLR_BENU_LSB BIT(20)
#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
#define PRTCIF_CTLR_BENL_MSB BIT(19)
#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
#define PRTCIF_CTLR_BENL_LSB BIT(16)
#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
/* PRTCIF_INTEN bit fields */
#define PRTCIF_INTEN_RTCSS BIT(1)
#define PRTCIF_INTEN_RTCIF BIT(0)
#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
| PRTCIF_INTEN_RTCIF)
/* PRTCIF_INTFLG bit fields */
#define PRTCIF_INTFLG_RTCSS BIT(1)
#define PRTCIF_INTFLG_RTCIF BIT(0)
#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
| PRTCIF_INTFLG_RTCIF)
/* PRTC subsystem registers */
#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
#define PRTCSS_RTC_CTRL (0x10)
#define PRTCSS_RTC_WDT (0x11)
#define PRTCSS_RTC_TMR0 (0x12)
#define PRTCSS_RTC_TMR1 (0x13)
#define PRTCSS_RTC_CCTRL (0x14)
#define PRTCSS_RTC_SEC (0x15)
#define PRTCSS_RTC_MIN (0x16)
#define PRTCSS_RTC_HOUR (0x17)
#define PRTCSS_RTC_DAY0 (0x18)
#define PRTCSS_RTC_DAY1 (0x19)
#define PRTCSS_RTC_AMIN (0x1A)
#define PRTCSS_RTC_AHOUR (0x1B)
#define PRTCSS_RTC_ADAY0 (0x1C)
#define PRTCSS_RTC_ADAY1 (0x1D)
#define PRTCSS_RTC_CLKC_CNT (0x20)
/* PRTCSS_RTC_INTC_EXTENA1 */
#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
/* PRTCSS_RTC_CTRL bit fields */
#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
#define PRTCSS_RTC_CTRL_WEN BIT(6)
#define PRTCSS_RTC_CTRL_WDRT BIT(5)
#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
#define PRTCSS_RTC_CTRL_TE BIT(3)
#define PRTCSS_RTC_CTRL_TIEN BIT(2)
#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
#define PRTCSS_RTC_CTRL_TMMD BIT(0)
/* PRTCSS_RTC_CCTRL bit fields */
#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
static DEFINE_SPINLOCK(davinci_rtc_lock);
struct davinci_rtc {
struct rtc_device *rtc;
void __iomem *base;
resource_size_t pbase;
size_t base_size;
int irq;
};
static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
u32 val, u32 addr)
{
writel(val, davinci_rtc->base + addr);
}
static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
{
return readl(davinci_rtc->base + addr);
}
static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
{
while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
cpu_relax();
}
static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
unsigned long val, u8 addr)
{
rtcif_wait(davinci_rtc);
rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
rtcif_wait(davinci_rtc);
}
static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
{
rtcif_wait(davinci_rtc);
rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
PRTCIF_CTLR);
rtcif_wait(davinci_rtc);
return rtcif_read(davinci_rtc, PRTCIF_LDATA);
}
static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
{
while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
PRTCSS_RTC_CCTRL_CALBUSY)
cpu_relax();
}
static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
{
struct davinci_rtc *davinci_rtc = class_dev;
unsigned long events = 0;
u32 irq_flg;
u8 alm_irq, tmr_irq;
u8 rtc_ctrl, rtc_cctrl;
int ret = IRQ_NONE;
irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
PRTCIF_INTFLG_RTCSS;
alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
PRTCSS_RTC_CCTRL_ALMFLG;
tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
PRTCSS_RTC_CTRL_TMRFLG;
if (irq_flg) {
if (alm_irq) {
events |= RTC_IRQF | RTC_AF;
rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
} else if (tmr_irq) {
events |= RTC_IRQF | RTC_PF;
rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
}
rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
PRTCIF_INTFLG);
rtc_update_irq(davinci_rtc->rtc, 1, events);
ret = IRQ_HANDLED;
}
return ret;
}
static int
davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
u8 rtc_ctrl;
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&davinci_rtc_lock, flags);
rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
switch (cmd) {
case RTC_WIE_ON:
rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
break;
case RTC_WIE_OFF:
rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
break;
case RTC_UIE_OFF:
case RTC_UIE_ON:
ret = -ENOTTY;
break;
default:
ret = -ENOIOCTLCMD;
}
rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
return ret;
}
static int convertfromdays(u16 days, struct rtc_time *tm)
{
int tmp_days, year, mon;
for (year = 2000;; year++) {
tmp_days = rtc_year_days(1, 12, year);
if (days >= tmp_days)
days -= tmp_days;
else {
for (mon = 0;; mon++) {
tmp_days = rtc_month_days(mon, year);
if (days >= tmp_days) {
days -= tmp_days;
} else {
tm->tm_year = year - 1900;
tm->tm_mon = mon;
tm->tm_mday = days + 1;
break;
}
}
break;
}
}
return 0;
}
static int convert2days(u16 *days, struct rtc_time *tm)
{
int i;
*days = 0;
/* epoch == 1900 */
if (tm->tm_year < 100 || tm->tm_year > 199)
return -EINVAL;
for (i = 2000; i < 1900 + tm->tm_year; i++)
*days += rtc_year_days(1, 12, i);
*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
return 0;
}
static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
u16 days = 0;
u8 day0, day1;
unsigned long flags;
spin_lock_irqsave(&davinci_rtc_lock, flags);
davinci_rtcss_calendar_wait(davinci_rtc);
tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
davinci_rtcss_calendar_wait(davinci_rtc);
tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
davinci_rtcss_calendar_wait(davinci_rtc);
tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
davinci_rtcss_calendar_wait(davinci_rtc);
day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
davinci_rtcss_calendar_wait(davinci_rtc);
day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
days |= day1;
days <<= 8;
days |= day0;
if (convertfromdays(days, tm) < 0)
return -EINVAL;
return 0;
}
static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
u16 days;
u8 rtc_cctrl;
unsigned long flags;
if (convert2days(&days, tm) < 0)
return -EINVAL;
spin_lock_irqsave(&davinci_rtc_lock, flags);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
return 0;
}
static int davinci_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
unsigned long flags;
u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
spin_lock_irqsave(&davinci_rtc_lock, flags);
if (enabled)
rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
PRTCSS_RTC_CCTRL_HAEN |
PRTCSS_RTC_CCTRL_MAEN |
PRTCSS_RTC_CCTRL_ALMFLG |
PRTCSS_RTC_CCTRL_AIEN;
else
rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
return 0;
}
static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
u16 days = 0;
u8 day0, day1;
unsigned long flags;
spin_lock_irqsave(&davinci_rtc_lock, flags);
davinci_rtcss_calendar_wait(davinci_rtc);
alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
davinci_rtcss_calendar_wait(davinci_rtc);
alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
davinci_rtcss_calendar_wait(davinci_rtc);
day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
davinci_rtcss_calendar_wait(davinci_rtc);
day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
days |= day1;
days <<= 8;
days |= day0;
if (convertfromdays(days, &alm->time) < 0)
return -EINVAL;
alm->pending = !!(rtcss_read(davinci_rtc,
PRTCSS_RTC_CCTRL) &
PRTCSS_RTC_CCTRL_AIEN);
alm->enabled = alm->pending && device_may_wakeup(dev);
return 0;
}
static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
unsigned long flags;
u16 days;
if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
&& alm->time.tm_year < 0) {
struct rtc_time tm;
unsigned long now, then;
davinci_rtc_read_time(dev, &tm);
rtc_tm_to_time(&tm, &now);
alm->time.tm_mday = tm.tm_mday;
alm->time.tm_mon = tm.tm_mon;
alm->time.tm_year = tm.tm_year;
rtc_tm_to_time(&alm->time, &then);
if (then < now) {
rtc_time_to_tm(now + 24 * 60 * 60, &tm);
alm->time.tm_mday = tm.tm_mday;
alm->time.tm_mon = tm.tm_mon;
alm->time.tm_year = tm.tm_year;
}
}
if (convert2days(&days, &alm->time) < 0)
return -EINVAL;
spin_lock_irqsave(&davinci_rtc_lock, flags);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
davinci_rtcss_calendar_wait(davinci_rtc);
rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
return 0;
}
static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
unsigned long flags;
u8 rtc_ctrl;
spin_lock_irqsave(&davinci_rtc_lock, flags);
rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
if (enabled) {
while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
& PRTCSS_RTC_CTRL_WDTBUS)
cpu_relax();
rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
PRTCSS_RTC_CTRL_TMMD |
PRTCSS_RTC_CTRL_TMRFLG;
} else
rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
return 0;
}
static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
{
struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
unsigned long flags;
u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
spin_lock_irqsave(&davinci_rtc_lock, flags);
rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
spin_unlock_irqrestore(&davinci_rtc_lock, flags);
return 0;
}
static struct rtc_class_ops davinci_rtc_ops = {
.ioctl = davinci_rtc_ioctl,
.read_time = davinci_rtc_read_time,
.set_time = davinci_rtc_set_time,
.alarm_irq_enable = davinci_rtc_alarm_irq_enable,
.read_alarm = davinci_rtc_read_alarm,
.set_alarm = davinci_rtc_set_alarm,
.irq_set_state = davinci_rtc_irq_set_state,
.irq_set_freq = davinci_rtc_irq_set_freq,
};
static int __init davinci_rtc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct davinci_rtc *davinci_rtc;
struct resource *res, *mem;
int ret = 0;
davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
if (!davinci_rtc) {
dev_dbg(dev, "could not allocate memory for private data\n");
return -ENOMEM;
}
davinci_rtc->irq = platform_get_irq(pdev, 0);
if (davinci_rtc->irq < 0) {
dev_err(dev, "no RTC irq\n");
ret = davinci_rtc->irq;
goto fail1;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "no mem resource\n");
ret = -EINVAL;
goto fail1;
}
davinci_rtc->pbase = res->start;
davinci_rtc->base_size = resource_size(res);
mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
pdev->name);
if (!mem) {
dev_err(dev, "RTC registers at %08x are not free\n",
davinci_rtc->pbase);
ret = -EBUSY;
goto fail1;
}
davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
if (!davinci_rtc->base) {
dev_err(dev, "unable to ioremap MEM resource\n");
ret = -ENOMEM;
goto fail2;
}
davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
&davinci_rtc_ops, THIS_MODULE);
if (IS_ERR(davinci_rtc->rtc)) {
dev_err(dev, "unable to register RTC device, err %ld\n",
PTR_ERR(davinci_rtc->rtc));
goto fail3;
}
rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
IRQF_DISABLED, "davinci_rtc", davinci_rtc);
if (ret < 0) {
dev_err(dev, "unable to register davinci RTC interrupt\n");
goto fail4;
}
/* Enable interrupts */
rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
PRTCSS_RTC_INTC_EXTENA1);
rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
platform_set_drvdata(pdev, davinci_rtc);
device_init_wakeup(&pdev->dev, 0);
return 0;
fail4:
rtc_device_unregister(davinci_rtc->rtc);
fail3:
iounmap(davinci_rtc->base);
fail2:
release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
fail1:
kfree(davinci_rtc);
return ret;
}
static int __devexit davinci_rtc_remove(struct platform_device *pdev)
{
struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
device_init_wakeup(&pdev->dev, 0);
rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
free_irq(davinci_rtc->irq, davinci_rtc);
rtc_device_unregister(davinci_rtc->rtc);
iounmap(davinci_rtc->base);
release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
platform_set_drvdata(pdev, NULL);
kfree(davinci_rtc);
return 0;
}
static struct platform_driver davinci_rtc_driver = {
.probe = davinci_rtc_probe,
.remove = __devexit_p(davinci_rtc_remove),
.driver = {
.name = "rtc_davinci",
.owner = THIS_MODULE,
},
};
static int __init rtc_init(void)
{
return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
}
module_init(rtc_init);
static void __exit rtc_exit(void)
{
platform_driver_unregister(&davinci_rtc_driver);
}
module_exit(rtc_exit);
MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
MODULE_LICENSE("GPL");