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bpf, riscv: Enable missing verifier_zext optimizations on RV64
Commit66d0d5a854
("riscv: bpf: eliminate zero extension code-gen") added support for the verifier zero-extension optimization on RV64 and commit46dd3d7d28
("bpf, riscv: Enable zext optimization for more RV64G ALU ops") enabled it for more instruction cases. However, BPF_LSH BPF_X and BPF_{LSH,RSH,ARSH} BPF_K are still missing the optimization. This patch enables the zero-extension optimization for these remaining cases. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Björn Töpel <bjorn.topel@gmail.com> Acked-by: Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20200506000320.28965-2-luke.r.nels@gmail.com
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@ -515,7 +515,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
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case BPF_ALU | BPF_LSH | BPF_X:
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case BPF_ALU64 | BPF_LSH | BPF_X:
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emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx);
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if (!is64)
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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case BPF_ALU | BPF_RSH | BPF_X:
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@ -692,19 +692,19 @@ out_be:
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case BPF_ALU | BPF_LSH | BPF_K:
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case BPF_ALU64 | BPF_LSH | BPF_K:
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emit(is64 ? rv_slli(rd, rd, imm) : rv_slliw(rd, rd, imm), ctx);
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if (!is64)
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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case BPF_ALU | BPF_RSH | BPF_K:
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case BPF_ALU64 | BPF_RSH | BPF_K:
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emit(is64 ? rv_srli(rd, rd, imm) : rv_srliw(rd, rd, imm), ctx);
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if (!is64)
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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case BPF_ALU | BPF_ARSH | BPF_K:
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case BPF_ALU64 | BPF_ARSH | BPF_K:
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emit(is64 ? rv_srai(rd, rd, imm) : rv_sraiw(rd, rd, imm), ctx);
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if (!is64)
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if (!is64 && !aux->verifier_zext)
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emit_zext_32(rd, ctx);
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break;
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