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clk: mediatek: Add MT8192 imgsys clock support

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Add MT8192 imgsys and imgsys2 clock providers

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-13-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chun-Jie Chen 2021-07-26 18:57:10 +08:00 committed by Stephen Boyd
parent cebef18833
commit 014a4881a2
3 changed files with 77 additions and 0 deletions
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6
drivers/clk/mediatek/Kconfig
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@ -520,6 +520,12 @@ config COMMON_CLK_MT8192_CAMSYS
help
This driver supports MediaTek MT8192 camsys and camsys_raw clocks.
config COMMON_CLK_MT8192_IMGSYS
bool "Clock driver for MediaTek MT8192 imgsys"
depends on COMMON_CLK_MT8192
help
This driver supports MediaTek MT8192 imgsys and imgsys2 clocks.
config COMMON_CLK_MT8516
bool "Clock driver for MediaTek MT8516"
depends on ARCH_MEDIATEK || COMPILE_TEST

1
drivers/clk/mediatek/Makefile
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@ -70,5 +70,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o

70
drivers/clk/mediatek/clk-mt8192-img.c Normal file
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@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0),
GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1),
GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2),
GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12),
};
static const struct mtk_gate img2_clks[] = {
GATE_IMG(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0),
GATE_IMG(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1),
GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6),
GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7),
GATE_IMG(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8),
GATE_IMG(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct mtk_clk_desc img2_desc = {
.clks = img2_clks,
.num_clks = ARRAY_SIZE(img2_clks),
};
static const struct of_device_id of_match_clk_mt8192_img[] = {
{
.compatible = "mediatek,mt8192-imgsys",
.data = &img_desc,
}, {
.compatible = "mediatek,mt8192-imgsys2",
.data = &img2_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8192_img_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8192-img",
.of_match_table = of_match_clk_mt8192_img,
},
};
builtin_platform_driver(clk_mt8192_img_drv);