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drm/bridge: tc358768: Print logical values, not raw register values
The driver debug prints DSI related timings as raw register values in hex. It is much more useful to see the "logical" value of the timing, not the register value. Change the prints to print the values separately, in case a single register contains multiple values, and use %u to have it in a more human consumable form. Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> # Asus TF700T Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230906-tc358768-v4-7-31725f008a50@ideasonboard.com
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@ -739,57 +739,59 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
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/* LP11 > 100us for D-PHY Rx Init */
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val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
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dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
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dev_dbg(priv->dev, "LINEINITCNT: %u\n", val);
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tc358768_write(priv, TC358768_LINEINITCNT, val);
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/* LPTimeCnt > 50ns */
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val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
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lptxcnt = val;
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dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
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dev_dbg(priv->dev, "LPTXTIMECNT: %u\n", val);
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tc358768_write(priv, TC358768_LPTXTIMECNT, val);
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/* 38ns < TCLK_PREPARE < 95ns */
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val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
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dev_dbg(priv->dev, "TCLK_PREPARECNT %u\n", val);
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/* TCLK_PREPARE + TCLK_ZERO > 300ns */
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val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
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dsibclk_nsk) - 2;
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dev_dbg(priv->dev, "TCLK_ZEROCNT %u\n", val2);
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val |= val2 << 8;
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dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
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tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
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/* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
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raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5;
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val = clamp(raw_val, 0, 127);
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dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
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dev_dbg(priv->dev, "TCLK_TRAILCNT: %u\n", val);
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tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
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/* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
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val = 50 + tc358768_to_ns(4 * ui_nsk);
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val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
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dev_dbg(priv->dev, "THS_PREPARECNT %u\n", val);
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/* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
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raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10;
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val2 = clamp(raw_val, 0, 127);
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dev_dbg(priv->dev, "THS_ZEROCNT %u\n", val2);
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val |= val2 << 8;
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dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
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tc358768_write(priv, TC358768_THS_HEADERCNT, val);
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/* TWAKEUP > 1ms in lptxcnt steps */
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val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
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val = val / (lptxcnt + 1) - 1;
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dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
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dev_dbg(priv->dev, "TWAKEUP: %u\n", val);
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tc358768_write(priv, TC358768_TWAKEUP, val);
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/* TCLK_POSTCNT > 60ns + 52*UI */
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val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
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dsibclk_nsk) - 3;
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dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
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dev_dbg(priv->dev, "TCLK_POSTCNT: %u\n", val);
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tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
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/* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
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raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk),
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dsibclk_nsk) - 4;
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val = clamp(raw_val, 0, 15);
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dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
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dev_dbg(priv->dev, "THS_TRAILCNT: %u\n", val);
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tc358768_write(priv, TC358768_THS_TRAILCNT, val);
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val = BIT(0);
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@ -803,10 +805,11 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
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/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
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val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
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val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1;
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dev_dbg(priv->dev, "TXTAGOCNT: %u\n", val);
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val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
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dsibclk_nsk) - 2;
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dev_dbg(priv->dev, "RXTASURECNT: %u\n", val2);
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val = val << 16 | val2;
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dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
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tc358768_write(priv, TC358768_BTACNTRL1, val);
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/* START[0] */
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