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This pull request contains Broadcom ARM-based SoCs Device Tree changes

Browse Source 
for 5.14, please pull the following:
 
 - Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
   files to resolve a number of DT binding check warnings pertaining to
   NAND, pinmux, clocks, SPI
 
 - Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
   causing regressions on the Raspberry Pi 4B
 
 - Mateusz adds a BCM2711 specific VEC compatible string to allow keying
   off that variant properly
 
 - Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
   re-organization work and finally adding the DTS file proper
 -----BEGIN PGP SIGNATURE-----
 
 iQIyBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmDCa4cACgkQh9CWnEQH
 BwRszA/1Fed5AmheLNW0wEWfEvZ+uACS+jTINXV09rGuU1HZj0qeTv/bO1PJfl4m
 tdSfUWdBTRa0IHeQ9o00GC2Rm/6UJoStAU2rOABw+sKJpH9y+El20xNBnqx5iXzO
 GUlIGbm27S3XWZR5EF6f1ZCej4cJZbpv/Ms9sEHa3b1aT3fJfackiBEk3uyhYX8Q
 fdxG9VNMyZIDOkocWQDeBCD82/IsizN3anFx88FP3vUtTYn/CldCc4H7JDmMzXid
 o3uRTAYta/Ls4z3IsI5hSWZ5+Psv7rbO+Qa/crPZm0SKzPIxQ7drglRJkbMtRSJu
 E27+9bzdLq4ruvUdJF/Wa1B2FKvk4kPtdMRwvStV7hoMrR9+DJ9S2trUUS4aehbx
 /keSHahZSbwWuWtHlmkmsqjTSAxFHsFVfCE3tM9qUo8uWjtxYA+6JyWW4SRw9/nw
 IOcRdxCeLYI29rWeACRjJ2XXXlwHLZWvZr1OrJVwJM2lMxKgLVqiQ38+O8uHDIEx
 CVZE0IM5CqAy5nusOs4jibfBJrbnhhst77j3pDeqkjo/Nv2f2GcxEciw8D+uH+tU
 4mj7sT4nQGSj3+lGtFml+s4MwBcbClcoep3VfIm+30JF41Xwa6Knv3+okJKM0DJK
 VX/pCBkov6QuOwS2P3KIFxHGtamlzJnz4hu6zpOiuJVZoxqdGQ==
 =ZmMv
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.14, please pull the following:

- Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
  files to resolve a number of DT binding check warnings pertaining to
  NAND, pinmux, clocks, SPI

- Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
  causing regressions on the Raspberry Pi 4B

- Mateusz adds a BCM2711 specific VEC compatible string to allow keying
  off that variant properly

- Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
  re-organization work and finally adding the DTS file proper

* tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: Add reference to RPi 400
  ARM: dts: Add Raspberry Pi 400 support
  ARM: dts: bcm283x: Fix up GPIO LED node names
  dt-bindings: arm: bcm2835: Add Raspberry Pi 400 to DT schema
  ARM: dts: Move BCM2711 RPi specific into separate dtsi
  ARM: dts: bcm283x: Fix up MMC node names
  ARM: boot: dts: bcm2711: Add BCM2711 VEC compatible
  Revert "ARM: dts: bcm283x: increase dwc2's RX FIFO size"
  ARM: dts: BCM5301X: Fixup SPI binding
  dt-bindings: clock: brcm, iproc-clocks: convert to the json-schema
  ARM: dts: BCM5301X: Fix pinmux subnodes names
  ARM: dts: Hurricane 2: Fix NAND nodes names
  ARM: dts: BCM63xx: Fix NAND nodes names
  ARM: NSP: dts: fix NAND nodes names
  ARM: Cygnus: dts: fix NAND nodes names
  ARM: brcmstb: dts: fix NAND nodes names
  ARM: dts: BCM5301X: Fix NAND nodes names

Link: https://lore.kernel.org/r/20210610194836.309869-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2021-06-12 08:40:07 -07:00
commit 010bf7346f
52 changed files with 610 additions and 464 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
View File

@ -18,6 +18,7 @@ properties:
- description: BCM2711 based Boards
items:
- enum:
- raspberrypi,400
- raspberrypi,4-model-b
- const: brcm,bcm2711

313
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
View File

@ -1,313 +0,0 @@
Broadcom iProc Family Clocks
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The iProc clock controller manages clocks that are common to the iProc family.
An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
comprises of several leaf clocks
Required properties for a PLL and its leaf clocks:
- compatible:
Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
Cygnus has a compatible string of "brcm,cygnus-genpll"
- #clock-cells:
Have a value of <1> since there are more than 1 leaf clock of a given PLL
- reg:
Define the base and range of the I/O address space that contain the iProc
clock control registers required for the PLL
- clocks:
The input parent clock phandle for the PLL. For most iProc PLLs, this is an
onboard crystal with a fixed rate
- clock-output-names:
An ordered list of strings defining the names of the clocks
Example:
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
genpll: genpll {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
clocks = <&osc>;
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
"enet_sw", "audio_125", "can";
};
Required properties for ASIU clocks:
ASIU clocks are a special case. These clocks are derived directly from the
reference clock of the onboard crystal
- compatible:
Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
- #clock-cells:
Have a value of <1> since there are more than 1 ASIU clocks
- reg:
Define the base and range of the I/O address space that contain the iProc
clock control registers required for ASIU clocks
- clocks:
The input parent clock phandle for the ASIU clock, i.e., the onboard
crystal
- clock-output-names:
An ordered list of strings defining the names of the ASIU clocks
Example:
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
asiu_clks: asiu_clks {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
clocks = <&osc>;
clock-output-names = "keypad", "adc/touch", "pwm";
};
Cygnus
------
PLL and leaf clock compatible strings for Cygnus are:
"brcm,cygnus-armpll"
"brcm,cygnus-genpll"
"brcm,cygnus-lcpll0"
"brcm,cygnus-mipipll"
"brcm,cygnus-asiu-clk"
"brcm,cygnus-audiopll"
The following table defines the set of PLL/clock index and ID for Cygnus.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-cygnus.h"
Clock Source (Parent) Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
armpll crystal N/A N/A
keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
genpll crystal 0 BCM_CYGNUS_GENPLL
axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
mipipll crystal 0 BCM_CYGNUS_MIPIPLL
ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
Hurricane 2
------
PLL and leaf clock compatible strings for Hurricane 2 are:
"brcm,hr2-armpll"
The following table defines the set of PLL/clock for Hurricane 2:
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
armpll crystal N/A N/A
Northstar and Northstar Plus
------
PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
"brcm,nsp-armpll"
"brcm,nsp-genpll"
"brcm,nsp-lcpll0"
The following table defines the set of PLL/clock index and ID for Northstar and
Northstar Plus. These clock IDs are defined in:
"include/dt-bindings/clock/bcm-nsp.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
armpll crystal N/A N/A
genpll crystal 0 BCM_NSP_GENPLL
phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
lcpll0 crystal 0 BCM_NSP_LCPLL0
pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
Northstar 2
-----------
PLL and leaf clock compatible strings for Northstar 2 are:
"brcm,ns2-genpll-scr"
"brcm,ns2-genpll-sw"
"brcm,ns2-lcpll-ddr"
"brcm,ns2-lcpll-ports"
The following table defines the set of PLL/clock index and ID for Northstar 2.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-ns2.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
genpll_sw crystal 0 BCM_NS2_GENPLL_SW
rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
"brcm,bcm63138-armpll"
Stingray
-----------
PLL and leaf clock compatible strings for Stingray are:
"brcm,sr-genpll0"
"brcm,sr-genpll1"
"brcm,sr-genpll2"
"brcm,sr-genpll3"
"brcm,sr-genpll4"
"brcm,sr-genpll5"
"brcm,sr-genpll6"
"brcm,sr-lcpll0"
"brcm,sr-lcpll1"
"brcm,sr-lcpll-pcie"
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK

395
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml Normal file
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@ -0,0 +1,395 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom iProc Family Clocks
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
description: |
The iProc clock controller manages clocks that are common to the iProc family.
An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
comprises of several leaf clocks
ASIU clocks are a special case. These clocks are derived directly from the
reference clock of the onboard crystal.
properties:
compatible:
enum:
- brcm,bcm63138-armpll
- brcm,cygnus-armpll
- brcm,cygnus-genpll
- brcm,cygnus-lcpll0
- brcm,cygnus-mipipll
- brcm,cygnus-asiu-clk
- brcm,cygnus-audiopll
- brcm,hr2-armpll
- brcm,nsp-armpll
- brcm,nsp-genpll
- brcm,nsp-lcpll0
- brcm,ns2-genpll-scr
- brcm,ns2-genpll-sw
- brcm,ns2-lcpll-ddr
- brcm,ns2-lcpll-ports
- brcm,sr-genpll0
- brcm,sr-genpll1
- brcm,sr-genpll2
- brcm,sr-genpll3
- brcm,sr-genpll4
- brcm,sr-genpll5
- brcm,sr-genpll6
- brcm,sr-lcpll0
- brcm,sr-lcpll1
- brcm,sr-lcpll-pcie
reg:
minItems: 1
maxItems: 3
items:
- description: base register
- description: power register
- description: ASIU or split status register
clocks:
description: The input parent clock phandle for the PLL / ASIU clock. For
most iProc PLLs, this is an onboard crystal with a fixed rate.
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
minItems: 1
maxItems: 45
allOf:
- if:
properties:
compatible:
contains:
enum:
- brcm,cygnus-armpll
- brcm,cygnus-genpll
- brcm,cygnus-lcpll0
- brcm,cygnus-mipipll
- brcm,cygnus-asiu-clk
- brcm,cygnus-audiopll
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Cygnus.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-cygnus.h"
Clock Source (Parent) Index ID
----- --------------- ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
genpll crystal 0 BCM_CYGNUS_GENPLL
axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
mipipll crystal 0 BCM_CYGNUS_MIPIPLL
ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
- if:
properties:
compatible:
contains:
enum:
- brcm,hr2-armpll
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock for Hurricane 2:
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
- if:
properties:
compatible:
contains:
enum:
- brcm,nsp-armpll
- brcm,nsp-genpll
- brcm,nsp-lcpll0
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Northstar and
Northstar Plus. These clock IDs are defined in:
"include/dt-bindings/clock/bcm-nsp.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
genpll crystal 0 BCM_NSP_GENPLL
phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
lcpll0 crystal 0 BCM_NSP_LCPLL0
pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
- if:
properties:
compatible:
contains:
enum:
- brcm,ns2-genpll-scr
- brcm,ns2-genpll-sw
- brcm,ns2-lcpll-ddr
- brcm,ns2-lcpll-ports
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Northstar 2.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-ns2.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
genpll_sw crystal 0 BCM_NS2_GENPLL_SW
rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
- if:
properties:
compatible:
contains:
enum:
- brcm,sr-genpll0
- brcm,sr-genpll1
- brcm,sr-genpll2
- brcm,sr-genpll3
- brcm,sr-genpll4
- brcm,sr-genpll5
- brcm,sr-genpll6
- brcm,sr-lcpll0
- brcm,sr-lcpll1
- brcm,sr-lcpll-pcie
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
- if:
properties:
compatible:
contains:
const: brcm,cygnus-genpll
then:
properties:
clock-output-names:
items:
- const: genpll
- const: axi21
- const: 250mhz
- const: ihost_sys
- const: enet_sw
- const: audio_125
- const: can
- if:
properties:
compatible:
contains:
const: brcm,nsp-lcpll0
then:
properties:
clock-output-names:
items:
- const: lcpll0
- const: pcie_phy
- const: sdio
- const: ddr_phy
- if:
properties:
compatible:
contains:
const: brcm,nsp-genpll
then:
properties:
clock-output-names:
items:
- const: genpll
- const: phy
- const: ethernetclk
- const: usbclk
- const: iprocfast
- const: sata1
- const: sata2
required:
- reg
- clocks
- '#clock-cells'
- clock-output-names
additionalProperties: false
examples:
- |
osc1: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
genpll@301d000 {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x301d000 0x2c>, <0x301c020 0x4>;
clocks = <&os1c>;
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
"enet_sw", "audio_125", "can";
};
- |
osc2: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
asiu_clks@301d048 {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x301d048 0xc>, <0x180aa024 0x4>;
clocks = <&osc2>;
clock-output-names = "keypad", "adc/touch", "pwm";
};

1
arch/arm/boot/dts/Makefile
View File

@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb

2
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -460,7 +460,7 @@
status = "disabled";
};
nand: nand@18046000 {
nand_controller: nand-controller@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>;

2
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -179,7 +179,7 @@
status = "disabled";
};
nand: nand@26000 {
nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x26000 0x600>,
<0x11b408 0x600>,

2
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -269,7 +269,7 @@
dma-coherent;
};
nand: nand@26000 {
nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
<0x11b408 0x600>,

85
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
model = "Raspberry Pi 4 Model B";
@ -15,25 +13,12 @@
stdout-path = "serial1:115200n8";
};
/* Will be filled by the bootloader */
memory@0 {
device_type = "memory";
reg = <0 0 0>;
};
aliases {
emmc2bus = &emmc2bus;
ethernet0 = &genet;
pcie0 = &pcie0;
blconfig = &blconfig;
};
leds {
act {
led-act {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
pwr {
led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
@ -79,31 +64,15 @@
status = "okay";
};
&firmware {
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
expgpio: gpio {
compatible = "raspberrypi,firmware-gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "BT_ON",
"WL_ON",
"PWR_LED_OFF",
"GLOBAL_RESET",
"VDD_SD_IO_SEL",
"CAM_GPIO",
"SD_PWR_ON",
"";
status = "okay";
};
reset: reset {
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
&expgpio {
gpio-line-names = "BT_ON",
"WL_ON",
"PWR_LED_OFF",
"GLOBAL_RESET",
"VDD_SD_IO_SEL",
"CAM_GPIO",
"SD_PWR_ON",
"";
};
&gpio {
@ -180,23 +149,13 @@
};
&hdmi0 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
wifi-2.4ghz-coexistence;
status = "okay";
};
&hdmi1 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
wifi-2.4ghz-coexistence;
status = "okay";
};
&hvs {
clocks = <&firmware_clocks 4>;
};
&pixelvalve0 {
status = "okay";
};
@ -219,22 +178,6 @@
status = "okay";
};
&rmem {
/*
* RPi4's co-processor will copy the board's bootloader configuration
* into memory for the OS to consume. It'll also update this node with
* its placement information.
*/
blconfig: nvram@0 {
compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x0>;
no-map;
status = "disabled";
};
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
@ -309,10 +252,6 @@
status = "okay";
};
&vchiq {
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
&vc4 {
status = "okay";
};

45
arch/arm/boot/dts/bcm2711-rpi-400.dts Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711-rpi-4-b.dts"
/ {
compatible = "raspberrypi,400", "brcm,bcm2711";
model = "Raspberry Pi 400";
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
leds {
/delete-node/ led-act;
led-pwr {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>;
};
};
&expgpio {
gpio-line-names = "BT_ON",
"WL_ON",
"",
"GLOBAL_RESET",
"VDD_SD_IO_SEL",
"CAM_GPIO",
"SD_PWR_ON",
"SD_OC_N";
};
&genet_mdio {
clock-frequency = <1950000>;
};
&pm {
/delete-property/ system-power-controller;
};

74
arch/arm/boot/dts/bcm2711-rpi.dtsi Normal file
View File

@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm2835-rpi.dtsi"
#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
/ {
/* Will be filled by the bootloader */
memory@0 {
device_type = "memory";
reg = <0 0 0>;
};
aliases {
emmc2bus = &emmc2bus;
ethernet0 = &genet;
pcie0 = &pcie0;
blconfig = &blconfig;
};
};
&firmware {
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
expgpio: gpio {
compatible = "raspberrypi,firmware-gpio";
gpio-controller;
#gpio-cells = <2>;
status = "okay";
};
reset: reset {
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
};
&hdmi0 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
wifi-2.4ghz-coexistence;
};
&hdmi1 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
wifi-2.4ghz-coexistence;
};
&hvs {
clocks = <&firmware_clocks 4>;
};
&rmem {
/*
* RPi4's co-processor will copy the board's bootloader configuration
* into memory for the OS to consume. It'll also update this node with
* its placement information.
*/
blconfig: nvram@0 {
compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x0>;
no-map;
status = "disabled";
};
};
&vchiq {
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};

3
arch/arm/boot/dts/bcm2711.dtsi
View File

@ -413,7 +413,7 @@
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
emmc2: emmc2@7e340000 {
emmc2: mmc@7e340000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
@ -1087,5 +1087,6 @@
};
&vec {
compatible = "brcm,bcm2711-vec";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
};

4
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
View File

@ -14,11 +14,11 @@
};
leds {
act {
led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";

2
arch/arm/boot/dts/bcm2835-rpi-a.dts
View File

@ -14,7 +14,7 @@
};
leds {
act {
led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};

4
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
View File

@ -15,11 +15,11 @@
};
leds {
act {
led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";

2
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
View File

@ -15,7 +15,7 @@
};
leds {
act {
led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};

2
arch/arm/boot/dts/bcm2835-rpi-b.dts
View File

@ -15,7 +15,7 @@
};
leds {
act {
led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};

2
arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
View File

@ -5,7 +5,7 @@
/ {
leds {
act {
led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};

2
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@ -23,7 +23,7 @@
};
leds {
act {
led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};

2
arch/arm/boot/dts/bcm2835-rpi-zero.dts
View File

@ -18,7 +18,7 @@
};
leds {
act {
led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};

2
arch/arm/boot/dts/bcm2835-rpi.dtsi
View File

@ -4,7 +4,7 @@
leds {
compatible = "gpio-leds";
act {
led-act {
label = "ACT";
default-state = "keep";
linux,default-trigger = "heartbeat";

4
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
View File

@ -15,11 +15,11 @@
};
leds {
act {
led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";

4
arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
View File

@ -19,11 +19,11 @@
};
leds {
act {
led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
pwr {
led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";

4
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
View File

@ -20,11 +20,11 @@
};
leds {
act {
led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
pwr {
led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";

2
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
View File

@ -20,7 +20,7 @@
};
leds {
act {
led-act {
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};

2
arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
View File

@ -14,7 +14,7 @@
* Since there is no upstream GPIO driver yet,
* remove the incomplete node.
*/
/delete-node/ act;
/delete-node/ led-act;
};
reg_3v3: fixed-regulator {

2
arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
&usb {
dr_mode = "otg";
g-rx-fifo-size = <558>;
g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
/*
* According to dwc2 the sum of all device EP

2
arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
&usb {
dr_mode = "peripheral";
g-rx-fifo-size = <558>;
g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 256 512 512 512 768 768>;
};

2
arch/arm/boot/dts/bcm283x.dtsi
View File

@ -420,7 +420,7 @@
status = "disabled";
};
sdhci: sdhci@7e300000 {
sdhci: mmc@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;

4
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
View File

@ -24,8 +24,8 @@
reg = <0x00000000 0x08000000>;
};
nand: nand@18028000 {
nandcs@0 {
nand_controller: nand-controller@18028000 {
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

4
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
View File

@ -25,8 +25,8 @@
<0x88000000 0x08000000>;
};
nand: nand@18028000 {
nandcs@0 {
nand_controller: nand-controller@18028000 {
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

2
arch/arm/boot/dts/bcm47094.dtsi
View File

@ -11,7 +11,7 @@
&pinctrl {
compatible = "brcm,bcm4709-pinmux";
pinmux_mdio: mdio {
pinmux_mdio: mdio-pins {
groups = "mdio_grp";
function = "mdio";
};

4
arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
View File

@ -6,8 +6,8 @@
*/
/ {
nand@18028000 {
nandcs: nandcs@0 {
nand-controller@18028000 {
nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
#address-cells = <1>;

26
arch/arm/boot/dts/bcm5301x.dtsi
View File

@ -458,18 +458,18 @@
function = "spi";
};
pinmux_i2c: i2c {
pinmux_i2c: i2c-pins {
groups = "i2c_grp";
function = "i2c";
};
pinmux_pwm: pwm {
pinmux_pwm: pwm-pins {
groups = "pwm0_grp", "pwm1_grp",
"pwm2_grp", "pwm3_grp";
function = "pwm";
};
pinmux_uart1: uart1 {
pinmux_uart1: uart1-pins {
groups = "uart1_grp";
function = "uart1";
};
@ -501,7 +501,7 @@
reg = <0x18004000 0x14>;
};
nand: nand@18028000 {
nand_controller: nand-controller@18028000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
@ -520,27 +520,27 @@
<0x1811b408 0x004>,
<0x180293a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "spi_lr_fullness_reached",
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mspi_done",
"mspi_halted",
"spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overhead",
"mspi_done",
"mspi_halted";
"spi_lr_overread";
clocks = <&iprocmed>;
clock-names = "iprocmed";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
spi_nor: spi-nor@0 {
spi_nor: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;

2
arch/arm/boot/dts/bcm63138.dtsi
View File

@ -203,7 +203,7 @@
status = "disabled";
};
nand: nand@2000 {
nand_controller: nand-controller@2000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";

4
arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
View File

@ -14,10 +14,10 @@
};
};
&nand {
&nand_controller {
status = "okay";
nandcs@1 {
nand@1 {
compatible = "brcm,nandcs";
reg = <1>;
nand-ecc-step-size = <512>;

2
arch/arm/boot/dts/bcm7445.dtsi
View File

@ -148,7 +148,7 @@
reg-names = "aon-ctrl", "aon-sram";
};
nand: nand@3e2800 {
nand_controller: nand-controller@3e2800 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm/boot/dts/bcm911360_entphn.dts
View File

@ -82,8 +82,8 @@
status = "okay";
};
&nand {
nandcs@1 {
&nand_controller {
nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm953012k.dts
View File

@ -49,8 +49,8 @@
};
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958300k.dts
View File

@ -60,8 +60,8 @@
status = "okay";
};
&nand {
nandcs@1 {
&nand_controller {
nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958305k.dts
View File

@ -68,8 +68,8 @@
status = "okay";
};
&nand {
nandcs@1 {
&nand_controller {
nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958522er.dts
View File

@ -74,8 +74,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958525er.dts
View File

@ -74,8 +74,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958525xmc.dts
View File

@ -90,8 +90,8 @@
};
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958622hr.dts
View File

@ -78,8 +78,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958623hr.dts
View File

@ -78,8 +78,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958625hr.dts
View File

@ -89,8 +89,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958625k.dts
View File

@ -68,8 +68,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm963138dvt.dts
View File

@ -31,10 +31,10 @@
status = "okay";
};
&nand {
&nand_controller {
status = "okay";
nandcs@0 {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;

4
arch/arm/boot/dts/bcm988312hr.dts
View File

@ -74,8 +74,8 @@
status = "okay";
};
&nand {
nandcs@0 {
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;

3
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \

2
arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts Normal file
View File

@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2711-rpi-400.dts"

2
arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
View File

@ -306,7 +306,7 @@
interrupt-names = "nand";
status = "okay";
nandcs: nandcs@0 {
nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
};